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Commit | Line | Data |
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edf79e66 HC |
1 | /* |
2 | * VT82C686B south bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) | |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
7 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
edf79e66 HC |
11 | */ |
12 | ||
0430891c | 13 | #include "qemu/osdep.h" |
0d09e41a | 14 | #include "hw/isa/vt82c686.h" |
83c9f4ca | 15 | #include "hw/pci/pci.h" |
a27bd6c7 | 16 | #include "hw/qdev-properties.h" |
0d09e41a | 17 | #include "hw/isa/isa.h" |
98cf824b | 18 | #include "hw/isa/superio.h" |
3dc31cb8 BZ |
19 | #include "hw/intc/i8259.h" |
20 | #include "hw/irq.h" | |
21 | #include "hw/dma/i8257.h" | |
22 | #include "hw/timer/i8254.h" | |
23 | #include "hw/rtc/mc146818rtc.h" | |
d6454270 | 24 | #include "migration/vmstate.h" |
0d09e41a PB |
25 | #include "hw/isa/apm.h" |
26 | #include "hw/acpi/acpi.h" | |
27 | #include "hw/i2c/pm_smbus.h" | |
9307d06d | 28 | #include "qapi/error.h" |
2c4c556e | 29 | #include "qemu/log.h" |
0b8fa32f | 30 | #include "qemu/module.h" |
911629e6 | 31 | #include "qemu/range.h" |
1de7afc9 | 32 | #include "qemu/timer.h" |
022c62cb | 33 | #include "exec/address-spaces.h" |
ff413a1f | 34 | #include "trace.h" |
edf79e66 | 35 | |
e1a69736 BZ |
36 | #define TYPE_VIA_PM "via-pm" |
37 | OBJECT_DECLARE_SIMPLE_TYPE(ViaPMState, VIA_PM) | |
edf79e66 | 38 | |
e1a69736 | 39 | struct ViaPMState { |
edf79e66 | 40 | PCIDevice dev; |
a2902821 | 41 | MemoryRegion io; |
355bf2e5 | 42 | ACPIREGS ar; |
edf79e66 | 43 | APMState apm; |
edf79e66 | 44 | PMSMBus smb; |
db1015e9 | 45 | }; |
edf79e66 | 46 | |
e1a69736 | 47 | static void pm_io_space_update(ViaPMState *s) |
edf79e66 | 48 | { |
3ab1eea6 | 49 | uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL; |
edf79e66 | 50 | |
a2902821 | 51 | memory_region_transaction_begin(); |
3ab1eea6 BZ |
52 | memory_region_set_address(&s->io, pmbase); |
53 | memory_region_set_enabled(&s->io, s->dev.config[0x41] & BIT(7)); | |
a2902821 | 54 | memory_region_transaction_commit(); |
edf79e66 HC |
55 | } |
56 | ||
e1a69736 | 57 | static void smb_io_space_update(ViaPMState *s) |
911629e6 BZ |
58 | { |
59 | uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL; | |
60 | ||
61 | memory_region_transaction_begin(); | |
62 | memory_region_set_address(&s->smb.io, smbase); | |
63 | memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0)); | |
64 | memory_region_transaction_commit(); | |
65 | } | |
66 | ||
edf79e66 HC |
67 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
68 | { | |
e1a69736 | 69 | ViaPMState *s = opaque; |
edf79e66 HC |
70 | |
71 | pm_io_space_update(s); | |
911629e6 | 72 | smb_io_space_update(s); |
edf79e66 HC |
73 | return 0; |
74 | } | |
75 | ||
76 | static const VMStateDescription vmstate_acpi = { | |
77 | .name = "vt82c686b_pm", | |
78 | .version_id = 1, | |
79 | .minimum_version_id = 1, | |
edf79e66 | 80 | .post_load = vmstate_acpi_post_load, |
d49805ae | 81 | .fields = (VMStateField[]) { |
e1a69736 BZ |
82 | VMSTATE_PCI_DEVICE(dev, ViaPMState), |
83 | VMSTATE_UINT16(ar.pm1.evt.sts, ViaPMState), | |
84 | VMSTATE_UINT16(ar.pm1.evt.en, ViaPMState), | |
85 | VMSTATE_UINT16(ar.pm1.cnt.cnt, ViaPMState), | |
86 | VMSTATE_STRUCT(apm, ViaPMState, 0, vmstate_apm, APMState), | |
87 | VMSTATE_TIMER_PTR(ar.tmr.timer, ViaPMState), | |
88 | VMSTATE_INT64(ar.tmr.overflow_time, ViaPMState), | |
edf79e66 HC |
89 | VMSTATE_END_OF_LIST() |
90 | } | |
91 | }; | |
92 | ||
94349bff BZ |
93 | static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) |
94 | { | |
e1a69736 | 95 | ViaPMState *s = VIA_PM(d); |
911629e6 | 96 | |
94349bff BZ |
97 | trace_via_pm_write(addr, val, len); |
98 | pci_default_write_config(d, addr, val, len); | |
3ab1eea6 BZ |
99 | if (ranges_overlap(addr, len, 0x48, 4)) { |
100 | uint32_t v = pci_get_long(s->dev.config + 0x48); | |
101 | pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1); | |
102 | } | |
103 | if (range_covers_byte(addr, len, 0x41)) { | |
104 | pm_io_space_update(s); | |
105 | } | |
911629e6 BZ |
106 | if (ranges_overlap(addr, len, 0x90, 4)) { |
107 | uint32_t v = pci_get_long(s->dev.config + 0x90); | |
108 | pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1); | |
109 | } | |
110 | if (range_covers_byte(addr, len, 0xd2)) { | |
111 | s->dev.config[0xd2] &= 0xf; | |
112 | smb_io_space_update(s); | |
113 | } | |
94349bff BZ |
114 | } |
115 | ||
35e360ed BZ |
116 | static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size) |
117 | { | |
118 | trace_via_pm_io_write(addr, data, size); | |
119 | } | |
120 | ||
121 | static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size) | |
122 | { | |
123 | trace_via_pm_io_read(addr, 0, size); | |
124 | return 0; | |
125 | } | |
126 | ||
127 | static const MemoryRegionOps pm_io_ops = { | |
128 | .read = pm_io_read, | |
129 | .write = pm_io_write, | |
130 | .endianness = DEVICE_NATIVE_ENDIAN, | |
131 | .impl = { | |
132 | .min_access_size = 1, | |
133 | .max_access_size = 1, | |
134 | }, | |
135 | }; | |
136 | ||
e1a69736 | 137 | static void pm_update_sci(ViaPMState *s) |
94349bff BZ |
138 | { |
139 | int sci_level, pmsts; | |
140 | ||
141 | pmsts = acpi_pm1_evt_get_sts(&s->ar); | |
142 | sci_level = (((pmsts & s->ar.pm1.evt.en) & | |
143 | (ACPI_BITMASK_RT_CLOCK_ENABLE | | |
144 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
145 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
146 | ACPI_BITMASK_TIMER_ENABLE)) != 0); | |
0fae92a3 IY |
147 | if (pci_get_byte(s->dev.config + PCI_INTERRUPT_PIN)) { |
148 | /* | |
149 | * FIXME: | |
150 | * Fix device model that realizes this PM device and remove | |
151 | * this work around. | |
152 | * The device model should wire SCI and setup | |
153 | * PCI_INTERRUPT_PIN properly. | |
154 | * If PIN# = 0(interrupt pin isn't used), don't raise SCI as | |
155 | * work around. | |
156 | */ | |
157 | pci_set_irq(&s->dev, sci_level); | |
158 | } | |
94349bff BZ |
159 | /* schedule a timer interruption if needed */ |
160 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && | |
161 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); | |
162 | } | |
163 | ||
164 | static void pm_tmr_timer(ACPIREGS *ar) | |
165 | { | |
e1a69736 | 166 | ViaPMState *s = container_of(ar, ViaPMState, ar); |
94349bff BZ |
167 | pm_update_sci(s); |
168 | } | |
169 | ||
e1a69736 | 170 | static void via_pm_reset(DeviceState *d) |
911629e6 | 171 | { |
e1a69736 | 172 | ViaPMState *s = VIA_PM(d); |
911629e6 | 173 | |
9af8e529 BZ |
174 | memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0, |
175 | PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE); | |
176 | /* Power Management IO base */ | |
177 | pci_set_long(s->dev.config + 0x48, 1); | |
911629e6 BZ |
178 | /* SMBus IO base */ |
179 | pci_set_long(s->dev.config + 0x90, 1); | |
911629e6 | 180 | |
44421c60 IY |
181 | acpi_pm1_evt_reset(&s->ar); |
182 | acpi_pm1_cnt_reset(&s->ar); | |
183 | acpi_pm_tmr_reset(&s->ar); | |
184 | pm_update_sci(s); | |
185 | ||
3ab1eea6 | 186 | pm_io_space_update(s); |
911629e6 BZ |
187 | smb_io_space_update(s); |
188 | } | |
189 | ||
e1a69736 | 190 | static void via_pm_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 191 | { |
e1a69736 | 192 | ViaPMState *s = VIA_PM(dev); |
edf79e66 | 193 | |
3ab1eea6 | 194 | pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK | |
edf79e66 HC |
195 | PCI_STATUS_DEVSEL_MEDIUM); |
196 | ||
a30c34d2 | 197 | pm_smbus_init(DEVICE(s), &s->smb, false); |
911629e6 BZ |
198 | memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io); |
199 | memory_region_set_enabled(&s->smb.io, false); | |
edf79e66 | 200 | |
42d8a3cf | 201 | apm_init(dev, &s->apm, NULL, s); |
edf79e66 | 202 | |
e1a69736 | 203 | memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s, "via-pm", 128); |
35e360ed | 204 | memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io); |
a2902821 | 205 | memory_region_set_enabled(&s->io, false); |
edf79e66 | 206 | |
77d58b1e | 207 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 208 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
6be8cf56 | 209 | acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2, false); |
edf79e66 HC |
210 | } |
211 | ||
e1a69736 BZ |
212 | typedef struct via_pm_init_info { |
213 | uint16_t device_id; | |
214 | } ViaPMInitInfo; | |
215 | ||
40021f08 AL |
216 | static void via_pm_class_init(ObjectClass *klass, void *data) |
217 | { | |
39bffca2 | 218 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 219 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
e1a69736 | 220 | ViaPMInitInfo *info = data; |
40021f08 | 221 | |
e1a69736 | 222 | k->realize = via_pm_realize; |
40021f08 AL |
223 | k->config_write = pm_write_config; |
224 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
e1a69736 | 225 | k->device_id = info->device_id; |
40021f08 AL |
226 | k->class_id = PCI_CLASS_BRIDGE_OTHER; |
227 | k->revision = 0x40; | |
e1a69736 | 228 | dc->reset = via_pm_reset; |
084bf4b4 BZ |
229 | /* Reason: part of VIA south bridge, does not exist stand alone */ |
230 | dc->user_creatable = false; | |
39bffca2 | 231 | dc->vmsd = &vmstate_acpi; |
40021f08 AL |
232 | } |
233 | ||
8c43a6f0 | 234 | static const TypeInfo via_pm_info = { |
e1a69736 | 235 | .name = TYPE_VIA_PM, |
39bffca2 | 236 | .parent = TYPE_PCI_DEVICE, |
e1a69736 BZ |
237 | .instance_size = sizeof(ViaPMState), |
238 | .abstract = true, | |
fd3b02c8 EH |
239 | .interfaces = (InterfaceInfo[]) { |
240 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
241 | { }, | |
242 | }, | |
edf79e66 HC |
243 | }; |
244 | ||
e1a69736 BZ |
245 | static const ViaPMInitInfo vt82c686b_pm_init_info = { |
246 | .device_id = PCI_DEVICE_ID_VIA_82C686B_PM, | |
247 | }; | |
248 | ||
249 | static const TypeInfo vt82c686b_pm_info = { | |
250 | .name = TYPE_VT82C686B_PM, | |
251 | .parent = TYPE_VIA_PM, | |
252 | .class_init = via_pm_class_init, | |
253 | .class_data = (void *)&vt82c686b_pm_init_info, | |
254 | }; | |
255 | ||
256 | static const ViaPMInitInfo vt8231_pm_init_info = { | |
257 | .device_id = PCI_DEVICE_ID_VIA_8231_PM, | |
258 | }; | |
259 | ||
260 | static const TypeInfo vt8231_pm_info = { | |
261 | .name = TYPE_VT8231_PM, | |
262 | .parent = TYPE_VIA_PM, | |
263 | .class_init = via_pm_class_init, | |
264 | .class_data = (void *)&vt8231_pm_init_info, | |
265 | }; | |
266 | ||
94349bff BZ |
267 | |
268 | typedef struct SuperIOConfig { | |
269 | uint8_t regs[0x100]; | |
94349bff BZ |
270 | MemoryRegion io; |
271 | } SuperIOConfig; | |
272 | ||
273 | static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, | |
274 | unsigned size) | |
275 | { | |
276 | SuperIOConfig *sc = opaque; | |
c953bf71 | 277 | uint8_t idx = sc->regs[0]; |
94349bff | 278 | |
cc2b4550 BZ |
279 | if (addr == 0) { /* config index register */ |
280 | sc->regs[0] = data; | |
2b98dca9 BZ |
281 | return; |
282 | } | |
cc2b4550 BZ |
283 | |
284 | /* config data register */ | |
285 | trace_via_superio_write(idx, data); | |
2b98dca9 BZ |
286 | switch (idx) { |
287 | case 0x00 ... 0xdf: | |
288 | case 0xe4: | |
289 | case 0xe5: | |
290 | case 0xe9 ... 0xed: | |
291 | case 0xf3: | |
292 | case 0xf5: | |
293 | case 0xf7: | |
294 | case 0xf9 ... 0xfb: | |
295 | case 0xfd ... 0xff: | |
b7741b77 BZ |
296 | /* ignore write to read only registers */ |
297 | return; | |
2b98dca9 BZ |
298 | /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */ |
299 | default: | |
2c4c556e BZ |
300 | qemu_log_mask(LOG_UNIMP, |
301 | "via_superio_cfg: unimplemented register 0x%x\n", idx); | |
2b98dca9 BZ |
302 | break; |
303 | } | |
cc2b4550 | 304 | sc->regs[idx] = data; |
94349bff BZ |
305 | } |
306 | ||
307 | static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size) | |
308 | { | |
309 | SuperIOConfig *sc = opaque; | |
c953bf71 BZ |
310 | uint8_t idx = sc->regs[0]; |
311 | uint8_t val = sc->regs[idx]; | |
94349bff | 312 | |
c953bf71 BZ |
313 | if (addr == 0) { |
314 | return idx; | |
315 | } | |
316 | if (addr == 1 && idx == 0) { | |
317 | val = 0; /* reading reg 0 where we store index value */ | |
318 | } | |
319 | trace_via_superio_read(idx, val); | |
94349bff BZ |
320 | return val; |
321 | } | |
322 | ||
323 | static const MemoryRegionOps superio_cfg_ops = { | |
324 | .read = superio_cfg_read, | |
325 | .write = superio_cfg_write, | |
326 | .endianness = DEVICE_NATIVE_ENDIAN, | |
327 | .impl = { | |
328 | .min_access_size = 1, | |
329 | .max_access_size = 1, | |
330 | }, | |
331 | }; | |
332 | ||
333 | ||
334 | OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA) | |
335 | ||
336 | struct VT82C686BISAState { | |
337 | PCIDevice dev; | |
3dc31cb8 | 338 | qemu_irq cpu_intr; |
94349bff BZ |
339 | SuperIOConfig superio_cfg; |
340 | }; | |
341 | ||
3dc31cb8 BZ |
342 | static void via_isa_request_i8259_irq(void *opaque, int irq, int level) |
343 | { | |
344 | VT82C686BISAState *s = opaque; | |
345 | qemu_set_irq(s->cpu_intr, level); | |
346 | } | |
347 | ||
94349bff BZ |
348 | static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, |
349 | uint32_t val, int len) | |
350 | { | |
351 | VT82C686BISAState *s = VT82C686B_ISA(d); | |
352 | ||
353 | trace_via_isa_write(addr, val, len); | |
354 | pci_default_write_config(d, addr, val, len); | |
355 | if (addr == 0x85) { | |
356 | /* BIT(1): enable or disable superio config io ports */ | |
357 | memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1)); | |
358 | } | |
359 | } | |
360 | ||
edf79e66 HC |
361 | static const VMStateDescription vmstate_via = { |
362 | .name = "vt82c686b", | |
363 | .version_id = 1, | |
364 | .minimum_version_id = 1, | |
d49805ae | 365 | .fields = (VMStateField[]) { |
0f798461 | 366 | VMSTATE_PCI_DEVICE(dev, VT82C686BISAState), |
edf79e66 HC |
367 | VMSTATE_END_OF_LIST() |
368 | } | |
369 | }; | |
370 | ||
94349bff BZ |
371 | static void vt82c686b_isa_reset(DeviceState *dev) |
372 | { | |
373 | VT82C686BISAState *s = VT82C686B_ISA(dev); | |
374 | uint8_t *pci_conf = s->dev.config; | |
375 | ||
376 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
377 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
378 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
379 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
380 | ||
381 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ | |
382 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ | |
383 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ | |
384 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ | |
385 | pci_conf[0x59] = 0x04; | |
386 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ | |
387 | pci_conf[0x5f] = 0x04; | |
388 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ | |
389 | ||
390 | s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */ | |
391 | s->superio_cfg.regs[0xe2] = 0x03; /* Function select */ | |
392 | s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */ | |
393 | s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */ | |
394 | s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */ | |
395 | s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */ | |
396 | } | |
397 | ||
9af21dbe | 398 | static void vt82c686b_realize(PCIDevice *d, Error **errp) |
edf79e66 | 399 | { |
007b3103 | 400 | VT82C686BISAState *s = VT82C686B_ISA(d); |
9859ad1c | 401 | DeviceState *dev = DEVICE(d); |
bcc37e24 | 402 | ISABus *isa_bus; |
3dc31cb8 | 403 | qemu_irq *isa_irq; |
edf79e66 HC |
404 | int i; |
405 | ||
3dc31cb8 BZ |
406 | qdev_init_gpio_out(dev, &s->cpu_intr, 1); |
407 | isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); | |
9859ad1c BZ |
408 | isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d), |
409 | &error_fatal); | |
3dc31cb8 BZ |
410 | isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq)); |
411 | i8254_pit_init(isa_bus, 0x40, 0, NULL); | |
412 | i8257_dma_init(isa_bus, 0); | |
413 | isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO); | |
414 | mc146818_rtc_init(isa_bus, 2000, NULL); | |
edf79e66 | 415 | |
9859ad1c BZ |
416 | for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) { |
417 | if (i < PCI_COMMAND || i >= PCI_REVISION_ID) { | |
418 | d->wmask[i] = 0; | |
f3db354c | 419 | } |
edf79e66 HC |
420 | } |
421 | ||
6be6e4bc BZ |
422 | memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops, |
423 | &s->superio_cfg, "superio_cfg", 2); | |
424 | memory_region_set_enabled(&s->superio_cfg.io, false); | |
f3db354c FB |
425 | /* |
426 | * The floppy also uses 0x3f0 and 0x3f1. | |
427 | * But we do not emulate a floppy, so just set it here. | |
428 | */ | |
bcc37e24 | 429 | memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, |
6be6e4bc | 430 | &s->superio_cfg.io); |
edf79e66 HC |
431 | } |
432 | ||
40021f08 AL |
433 | static void via_class_init(ObjectClass *klass, void *data) |
434 | { | |
39bffca2 | 435 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
436 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
437 | ||
9af21dbe | 438 | k->realize = vt82c686b_realize; |
40021f08 AL |
439 | k->config_write = vt82c686b_write_config; |
440 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
441 | k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; | |
442 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
443 | k->revision = 0x40; | |
9dc1a769 | 444 | dc->reset = vt82c686b_isa_reset; |
39bffca2 | 445 | dc->desc = "ISA bridge"; |
39bffca2 | 446 | dc->vmsd = &vmstate_via; |
04916ee9 MA |
447 | /* |
448 | * Reason: part of VIA VT82C686 southbridge, needs to be wired up, | |
c3a09ff6 | 449 | * e.g. by mips_fuloong2e_init() |
04916ee9 | 450 | */ |
e90f2a8c | 451 | dc->user_creatable = false; |
40021f08 AL |
452 | } |
453 | ||
8c43a6f0 | 454 | static const TypeInfo via_info = { |
0f798461 | 455 | .name = TYPE_VT82C686B_ISA, |
39bffca2 | 456 | .parent = TYPE_PCI_DEVICE, |
0f798461 | 457 | .instance_size = sizeof(VT82C686BISAState), |
39bffca2 | 458 | .class_init = via_class_init, |
fd3b02c8 EH |
459 | .interfaces = (InterfaceInfo[]) { |
460 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
461 | { }, | |
462 | }, | |
edf79e66 HC |
463 | }; |
464 | ||
94349bff | 465 | |
98cf824b PMD |
466 | static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) |
467 | { | |
468 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | |
469 | ||
470 | sc->serial.count = 2; | |
471 | sc->parallel.count = 1; | |
472 | sc->ide.count = 0; | |
473 | sc->floppy.count = 1; | |
474 | } | |
475 | ||
476 | static const TypeInfo via_superio_info = { | |
477 | .name = TYPE_VT82C686B_SUPERIO, | |
478 | .parent = TYPE_ISA_SUPERIO, | |
479 | .instance_size = sizeof(ISASuperIODevice), | |
480 | .class_size = sizeof(ISASuperIOClass), | |
481 | .class_init = vt82c686b_superio_class_init, | |
482 | }; | |
483 | ||
94349bff | 484 | |
83f7d43a | 485 | static void vt82c686b_register_types(void) |
edf79e66 | 486 | { |
83f7d43a | 487 | type_register_static(&via_pm_info); |
e1a69736 BZ |
488 | type_register_static(&vt82c686b_pm_info); |
489 | type_register_static(&vt8231_pm_info); | |
39bffca2 | 490 | type_register_static(&via_info); |
94349bff | 491 | type_register_static(&via_superio_info); |
edf79e66 | 492 | } |
83f7d43a AF |
493 | |
494 | type_init(vt82c686b_register_types) |