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Commit | Line | Data |
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edf79e66 HC |
1 | /* |
2 | * VT82C686B south bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) | |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
7 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
edf79e66 HC |
11 | */ |
12 | ||
0430891c | 13 | #include "qemu/osdep.h" |
0d09e41a PB |
14 | #include "hw/isa/vt82c686.h" |
15 | #include "hw/i2c/i2c.h" | |
83c9f4ca | 16 | #include "hw/pci/pci.h" |
a27bd6c7 | 17 | #include "hw/qdev-properties.h" |
0d09e41a | 18 | #include "hw/isa/isa.h" |
98cf824b | 19 | #include "hw/isa/superio.h" |
83c9f4ca | 20 | #include "hw/sysbus.h" |
d6454270 | 21 | #include "migration/vmstate.h" |
0d09e41a PB |
22 | #include "hw/mips/mips.h" |
23 | #include "hw/isa/apm.h" | |
24 | #include "hw/acpi/acpi.h" | |
25 | #include "hw/i2c/pm_smbus.h" | |
9307d06d | 26 | #include "qapi/error.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
1de7afc9 | 28 | #include "qemu/timer.h" |
022c62cb | 29 | #include "exec/address-spaces.h" |
db1015e9 | 30 | #include "qom/object.h" |
edf79e66 | 31 | |
f3db354c | 32 | /* #define DEBUG_VT82C686B */ |
edf79e66 HC |
33 | |
34 | #ifdef DEBUG_VT82C686B | |
a89f364a | 35 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) |
edf79e66 HC |
36 | #else |
37 | #define DPRINTF(fmt, ...) | |
38 | #endif | |
39 | ||
f3db354c | 40 | typedef struct SuperIOConfig { |
9feb8ade | 41 | uint8_t config[0x100]; |
edf79e66 HC |
42 | uint8_t index; |
43 | uint8_t data; | |
44 | } SuperIOConfig; | |
45 | ||
db1015e9 | 46 | struct VT82C686BState { |
edf79e66 | 47 | PCIDevice dev; |
bcc37e24 | 48 | MemoryRegion superio; |
edf79e66 | 49 | SuperIOConfig superio_conf; |
db1015e9 EH |
50 | }; |
51 | typedef struct VT82C686BState VT82C686BState; | |
edf79e66 | 52 | |
417349e6 | 53 | #define TYPE_VT82C686B_DEVICE "VT82C686B" |
8110fa1d EH |
54 | DECLARE_INSTANCE_CHECKER(VT82C686BState, VT82C686B_DEVICE, |
55 | TYPE_VT82C686B_DEVICE) | |
417349e6 | 56 | |
bcc37e24 JK |
57 | static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, |
58 | unsigned size) | |
edf79e66 | 59 | { |
edf79e66 HC |
60 | SuperIOConfig *superio_conf = opaque; |
61 | ||
b2bedb21 | 62 | DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); |
edf79e66 HC |
63 | if (addr == 0x3f0) { |
64 | superio_conf->index = data & 0xff; | |
65 | } else { | |
b196d969 | 66 | bool can_write = true; |
edf79e66 HC |
67 | /* 0x3f1 */ |
68 | switch (superio_conf->index) { | |
69 | case 0x00 ... 0xdf: | |
70 | case 0xe4: | |
71 | case 0xe5: | |
72 | case 0xe9 ... 0xed: | |
73 | case 0xf3: | |
74 | case 0xf5: | |
75 | case 0xf7: | |
76 | case 0xf9 ... 0xfb: | |
77 | case 0xfd ... 0xff: | |
b196d969 HZ |
78 | can_write = false; |
79 | break; | |
80 | case 0xe7: | |
81 | if ((data & 0xff) != 0xfe) { | |
82 | DPRINTF("change uart 1 base. unsupported yet\n"); | |
83 | can_write = false; | |
84 | } | |
85 | break; | |
86 | case 0xe8: | |
87 | if ((data & 0xff) != 0xbe) { | |
88 | DPRINTF("change uart 2 base. unsupported yet\n"); | |
89 | can_write = false; | |
90 | } | |
edf79e66 HC |
91 | break; |
92 | default: | |
b196d969 | 93 | break; |
edf79e66 | 94 | |
edf79e66 | 95 | } |
b196d969 HZ |
96 | if (can_write) { |
97 | superio_conf->config[superio_conf->index] = data & 0xff; | |
98 | } | |
edf79e66 HC |
99 | } |
100 | } | |
101 | ||
bcc37e24 | 102 | static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) |
edf79e66 HC |
103 | { |
104 | SuperIOConfig *superio_conf = opaque; | |
105 | ||
b2bedb21 | 106 | DPRINTF("superio_ioport_readb address 0x%x\n", addr); |
f3db354c | 107 | return superio_conf->config[superio_conf->index]; |
edf79e66 HC |
108 | } |
109 | ||
bcc37e24 JK |
110 | static const MemoryRegionOps superio_ops = { |
111 | .read = superio_ioport_readb, | |
112 | .write = superio_ioport_writeb, | |
113 | .endianness = DEVICE_NATIVE_ENDIAN, | |
114 | .impl = { | |
115 | .min_access_size = 1, | |
116 | .max_access_size = 1, | |
117 | }, | |
118 | }; | |
119 | ||
9dc1a769 | 120 | static void vt82c686b_isa_reset(DeviceState *dev) |
edf79e66 | 121 | { |
9dc1a769 PMD |
122 | VT82C686BState *vt82c = VT82C686B_DEVICE(dev); |
123 | uint8_t *pci_conf = vt82c->dev.config; | |
edf79e66 HC |
124 | |
125 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
126 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
127 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
128 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
129 | ||
130 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ | |
131 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ | |
132 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ | |
133 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ | |
134 | pci_conf[0x59] = 0x04; | |
135 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ | |
136 | pci_conf[0x5f] = 0x04; | |
137 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ | |
138 | ||
139 | vt82c->superio_conf.config[0xe0] = 0x3c; | |
140 | vt82c->superio_conf.config[0xe2] = 0x03; | |
141 | vt82c->superio_conf.config[0xe3] = 0xfc; | |
142 | vt82c->superio_conf.config[0xe6] = 0xde; | |
143 | vt82c->superio_conf.config[0xe7] = 0xfe; | |
144 | vt82c->superio_conf.config[0xe8] = 0xbe; | |
145 | } | |
146 | ||
147 | /* write config pci function0 registers. PCI-ISA bridge */ | |
f3db354c | 148 | static void vt82c686b_write_config(PCIDevice *d, uint32_t address, |
edf79e66 HC |
149 | uint32_t val, int len) |
150 | { | |
417349e6 | 151 | VT82C686BState *vt686 = VT82C686B_DEVICE(d); |
edf79e66 | 152 | |
b2bedb21 | 153 | DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", |
edf79e66 HC |
154 | address, val, len); |
155 | ||
156 | pci_default_write_config(d, address, val, len); | |
157 | if (address == 0x85) { /* enable or disable super IO configure */ | |
bcc37e24 | 158 | memory_region_set_enabled(&vt686->superio, val & 0x2); |
edf79e66 HC |
159 | } |
160 | } | |
161 | ||
162 | #define ACPI_DBG_IO_ADDR 0xb044 | |
163 | ||
db1015e9 | 164 | struct VT686PMState { |
edf79e66 | 165 | PCIDevice dev; |
a2902821 | 166 | MemoryRegion io; |
355bf2e5 | 167 | ACPIREGS ar; |
edf79e66 | 168 | APMState apm; |
edf79e66 HC |
169 | PMSMBus smb; |
170 | uint32_t smb_io_base; | |
db1015e9 EH |
171 | }; |
172 | typedef struct VT686PMState VT686PMState; | |
edf79e66 | 173 | |
db1015e9 | 174 | struct VT686AC97State { |
edf79e66 | 175 | PCIDevice dev; |
db1015e9 EH |
176 | }; |
177 | typedef struct VT686AC97State VT686AC97State; | |
edf79e66 | 178 | |
db1015e9 | 179 | struct VT686MC97State { |
edf79e66 | 180 | PCIDevice dev; |
db1015e9 EH |
181 | }; |
182 | typedef struct VT686MC97State VT686MC97State; | |
edf79e66 | 183 | |
417349e6 | 184 | #define TYPE_VT82C686B_PM_DEVICE "VT82C686B_PM" |
8110fa1d EH |
185 | DECLARE_INSTANCE_CHECKER(VT686PMState, VT82C686B_PM_DEVICE, |
186 | TYPE_VT82C686B_PM_DEVICE) | |
417349e6 GA |
187 | |
188 | #define TYPE_VT82C686B_MC97_DEVICE "VT82C686B_MC97" | |
8110fa1d EH |
189 | DECLARE_INSTANCE_CHECKER(VT686MC97State, VT82C686B_MC97_DEVICE, |
190 | TYPE_VT82C686B_MC97_DEVICE) | |
417349e6 GA |
191 | |
192 | #define TYPE_VT82C686B_AC97_DEVICE "VT82C686B_AC97" | |
8110fa1d EH |
193 | DECLARE_INSTANCE_CHECKER(VT686AC97State, VT82C686B_AC97_DEVICE, |
194 | TYPE_VT82C686B_AC97_DEVICE) | |
417349e6 | 195 | |
edf79e66 HC |
196 | static void pm_update_sci(VT686PMState *s) |
197 | { | |
198 | int sci_level, pmsts; | |
edf79e66 | 199 | |
2886be1b | 200 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 201 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
04dc308f IY |
202 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
203 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
204 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
205 | ACPI_BITMASK_TIMER_ENABLE)) != 0); | |
9e64f8a3 | 206 | pci_set_irq(&s->dev, sci_level); |
edf79e66 | 207 | /* schedule a timer interruption if needed */ |
355bf2e5 | 208 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 209 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
edf79e66 HC |
210 | } |
211 | ||
355bf2e5 | 212 | static void pm_tmr_timer(ACPIREGS *ar) |
edf79e66 | 213 | { |
355bf2e5 | 214 | VT686PMState *s = container_of(ar, VT686PMState, ar); |
edf79e66 HC |
215 | pm_update_sci(s); |
216 | } | |
217 | ||
edf79e66 HC |
218 | static void pm_io_space_update(VT686PMState *s) |
219 | { | |
220 | uint32_t pm_io_base; | |
221 | ||
a2902821 GH |
222 | pm_io_base = pci_get_long(s->dev.config + 0x40); |
223 | pm_io_base &= 0xffc0; | |
edf79e66 | 224 | |
a2902821 GH |
225 | memory_region_transaction_begin(); |
226 | memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); | |
227 | memory_region_set_address(&s->io, pm_io_base); | |
228 | memory_region_transaction_commit(); | |
edf79e66 HC |
229 | } |
230 | ||
231 | static void pm_write_config(PCIDevice *d, | |
232 | uint32_t address, uint32_t val, int len) | |
233 | { | |
b2bedb21 | 234 | DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", |
edf79e66 HC |
235 | address, val, len); |
236 | pci_default_write_config(d, address, val, len); | |
237 | } | |
238 | ||
239 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
240 | { | |
241 | VT686PMState *s = opaque; | |
242 | ||
243 | pm_io_space_update(s); | |
244 | return 0; | |
245 | } | |
246 | ||
247 | static const VMStateDescription vmstate_acpi = { | |
248 | .name = "vt82c686b_pm", | |
249 | .version_id = 1, | |
250 | .minimum_version_id = 1, | |
edf79e66 | 251 | .post_load = vmstate_acpi_post_load, |
d49805ae | 252 | .fields = (VMStateField[]) { |
edf79e66 | 253 | VMSTATE_PCI_DEVICE(dev, VT686PMState), |
355bf2e5 GH |
254 | VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), |
255 | VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), | |
256 | VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), | |
edf79e66 | 257 | VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), |
e720677e | 258 | VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState), |
355bf2e5 | 259 | VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), |
edf79e66 HC |
260 | VMSTATE_END_OF_LIST() |
261 | } | |
262 | }; | |
263 | ||
264 | /* | |
265 | * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() | |
266 | * just register a PCI device now, functionalities will be implemented later. | |
267 | */ | |
268 | ||
9af21dbe | 269 | static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 270 | { |
417349e6 | 271 | VT686AC97State *s = VT82C686B_AC97_DEVICE(dev); |
edf79e66 HC |
272 | uint8_t *pci_conf = s->dev.config; |
273 | ||
edf79e66 HC |
274 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
275 | PCI_COMMAND_PARITY); | |
276 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | | |
277 | PCI_STATUS_DEVSEL_MEDIUM); | |
278 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); | |
edf79e66 HC |
279 | } |
280 | ||
281 | void vt82c686b_ac97_init(PCIBus *bus, int devfn) | |
282 | { | |
283 | PCIDevice *dev; | |
284 | ||
9307d06d MA |
285 | dev = pci_new(devfn, TYPE_VT82C686B_AC97_DEVICE); |
286 | pci_realize_and_unref(dev, bus, &error_fatal); | |
edf79e66 HC |
287 | } |
288 | ||
40021f08 AL |
289 | static void via_ac97_class_init(ObjectClass *klass, void *data) |
290 | { | |
39bffca2 | 291 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
292 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
293 | ||
9af21dbe | 294 | k->realize = vt82c686b_ac97_realize; |
40021f08 AL |
295 | k->vendor_id = PCI_VENDOR_ID_VIA; |
296 | k->device_id = PCI_DEVICE_ID_VIA_AC97; | |
297 | k->revision = 0x50; | |
298 | k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; | |
125ee0ed | 299 | set_bit(DEVICE_CATEGORY_SOUND, dc->categories); |
39bffca2 | 300 | dc->desc = "AC97"; |
40021f08 AL |
301 | } |
302 | ||
8c43a6f0 | 303 | static const TypeInfo via_ac97_info = { |
417349e6 | 304 | .name = TYPE_VT82C686B_AC97_DEVICE, |
39bffca2 AL |
305 | .parent = TYPE_PCI_DEVICE, |
306 | .instance_size = sizeof(VT686AC97State), | |
307 | .class_init = via_ac97_class_init, | |
fd3b02c8 EH |
308 | .interfaces = (InterfaceInfo[]) { |
309 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
310 | { }, | |
311 | }, | |
edf79e66 HC |
312 | }; |
313 | ||
9af21dbe | 314 | static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 315 | { |
417349e6 | 316 | VT686MC97State *s = VT82C686B_MC97_DEVICE(dev); |
edf79e66 HC |
317 | uint8_t *pci_conf = s->dev.config; |
318 | ||
edf79e66 HC |
319 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
320 | PCI_COMMAND_VGA_PALETTE); | |
321 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
322 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); | |
edf79e66 HC |
323 | } |
324 | ||
325 | void vt82c686b_mc97_init(PCIBus *bus, int devfn) | |
326 | { | |
327 | PCIDevice *dev; | |
328 | ||
9307d06d MA |
329 | dev = pci_new(devfn, TYPE_VT82C686B_MC97_DEVICE); |
330 | pci_realize_and_unref(dev, bus, &error_fatal); | |
edf79e66 HC |
331 | } |
332 | ||
40021f08 AL |
333 | static void via_mc97_class_init(ObjectClass *klass, void *data) |
334 | { | |
39bffca2 | 335 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
336 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
337 | ||
9af21dbe | 338 | k->realize = vt82c686b_mc97_realize; |
40021f08 AL |
339 | k->vendor_id = PCI_VENDOR_ID_VIA; |
340 | k->device_id = PCI_DEVICE_ID_VIA_MC97; | |
341 | k->class_id = PCI_CLASS_COMMUNICATION_OTHER; | |
342 | k->revision = 0x30; | |
125ee0ed | 343 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
39bffca2 | 344 | dc->desc = "MC97"; |
40021f08 AL |
345 | } |
346 | ||
8c43a6f0 | 347 | static const TypeInfo via_mc97_info = { |
417349e6 | 348 | .name = TYPE_VT82C686B_MC97_DEVICE, |
39bffca2 AL |
349 | .parent = TYPE_PCI_DEVICE, |
350 | .instance_size = sizeof(VT686MC97State), | |
351 | .class_init = via_mc97_class_init, | |
fd3b02c8 EH |
352 | .interfaces = (InterfaceInfo[]) { |
353 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
354 | { }, | |
355 | }, | |
edf79e66 HC |
356 | }; |
357 | ||
edf79e66 | 358 | /* vt82c686 pm init */ |
9af21dbe | 359 | static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 360 | { |
417349e6 | 361 | VT686PMState *s = VT82C686B_PM_DEVICE(dev); |
edf79e66 HC |
362 | uint8_t *pci_conf; |
363 | ||
364 | pci_conf = s->dev.config; | |
edf79e66 HC |
365 | pci_set_word(pci_conf + PCI_COMMAND, 0); |
366 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | | |
367 | PCI_STATUS_DEVSEL_MEDIUM); | |
368 | ||
369 | /* 0x48-0x4B is Power Management I/O Base */ | |
370 | pci_set_long(pci_conf + 0x48, 0x00000001); | |
371 | ||
372 | /* SMB ports:0xeee0~0xeeef */ | |
f3db354c | 373 | s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0); |
edf79e66 HC |
374 | pci_conf[0x90] = s->smb_io_base | 1; |
375 | pci_conf[0x91] = s->smb_io_base >> 8; | |
376 | pci_conf[0xd2] = 0x90; | |
a30c34d2 | 377 | pm_smbus_init(DEVICE(s), &s->smb, false); |
798512e5 | 378 | memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); |
edf79e66 | 379 | |
42d8a3cf | 380 | apm_init(dev, &s->apm, NULL, s); |
edf79e66 | 381 | |
1437c94b | 382 | memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64); |
a2902821 GH |
383 | memory_region_set_enabled(&s->io, false); |
384 | memory_region_add_subregion(get_system_io(), 0, &s->io); | |
edf79e66 | 385 | |
77d58b1e | 386 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 387 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
9a10bbb4 | 388 | acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); |
edf79e66 HC |
389 | } |
390 | ||
a5c82852 AF |
391 | I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
392 | qemu_irq sci_irq) | |
edf79e66 HC |
393 | { |
394 | PCIDevice *dev; | |
395 | VT686PMState *s; | |
396 | ||
9307d06d | 397 | dev = pci_new(devfn, TYPE_VT82C686B_PM_DEVICE); |
edf79e66 HC |
398 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); |
399 | ||
417349e6 | 400 | s = VT82C686B_PM_DEVICE(dev); |
edf79e66 | 401 | |
9307d06d | 402 | pci_realize_and_unref(dev, bus, &error_fatal); |
edf79e66 HC |
403 | |
404 | return s->smb.smbus; | |
405 | } | |
406 | ||
40021f08 AL |
407 | static Property via_pm_properties[] = { |
408 | DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), | |
409 | DEFINE_PROP_END_OF_LIST(), | |
410 | }; | |
411 | ||
412 | static void via_pm_class_init(ObjectClass *klass, void *data) | |
413 | { | |
39bffca2 | 414 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
415 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
416 | ||
9af21dbe | 417 | k->realize = vt82c686b_pm_realize; |
40021f08 AL |
418 | k->config_write = pm_write_config; |
419 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
420 | k->device_id = PCI_DEVICE_ID_VIA_ACPI; | |
421 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
422 | k->revision = 0x40; | |
39bffca2 AL |
423 | dc->desc = "PM"; |
424 | dc->vmsd = &vmstate_acpi; | |
125ee0ed | 425 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
4f67d30b | 426 | device_class_set_props(dc, via_pm_properties); |
40021f08 AL |
427 | } |
428 | ||
8c43a6f0 | 429 | static const TypeInfo via_pm_info = { |
417349e6 | 430 | .name = TYPE_VT82C686B_PM_DEVICE, |
39bffca2 AL |
431 | .parent = TYPE_PCI_DEVICE, |
432 | .instance_size = sizeof(VT686PMState), | |
433 | .class_init = via_pm_class_init, | |
fd3b02c8 EH |
434 | .interfaces = (InterfaceInfo[]) { |
435 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
436 | { }, | |
437 | }, | |
edf79e66 HC |
438 | }; |
439 | ||
edf79e66 HC |
440 | static const VMStateDescription vmstate_via = { |
441 | .name = "vt82c686b", | |
442 | .version_id = 1, | |
443 | .minimum_version_id = 1, | |
d49805ae | 444 | .fields = (VMStateField[]) { |
edf79e66 HC |
445 | VMSTATE_PCI_DEVICE(dev, VT82C686BState), |
446 | VMSTATE_END_OF_LIST() | |
447 | } | |
448 | }; | |
449 | ||
450 | /* init the PCI-to-ISA bridge */ | |
9af21dbe | 451 | static void vt82c686b_realize(PCIDevice *d, Error **errp) |
edf79e66 | 452 | { |
417349e6 | 453 | VT82C686BState *vt82c = VT82C686B_DEVICE(d); |
edf79e66 | 454 | uint8_t *pci_conf; |
bcc37e24 | 455 | ISABus *isa_bus; |
edf79e66 HC |
456 | uint8_t *wmask; |
457 | int i; | |
458 | ||
bb2ed009 | 459 | isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), |
d10e5432 MA |
460 | pci_address_space_io(d), errp); |
461 | if (!isa_bus) { | |
462 | return; | |
463 | } | |
edf79e66 HC |
464 | |
465 | pci_conf = d->config; | |
edf79e66 | 466 | pci_config_set_prog_interface(pci_conf, 0x0); |
edf79e66 HC |
467 | |
468 | wmask = d->wmask; | |
469 | for (i = 0x00; i < 0xff; i++) { | |
f3db354c FB |
470 | if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) { |
471 | wmask[i] = 0x00; | |
472 | } | |
edf79e66 HC |
473 | } |
474 | ||
db10ca90 | 475 | memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops, |
2c9b15ca | 476 | &vt82c->superio_conf, "superio", 2); |
bcc37e24 | 477 | memory_region_set_enabled(&vt82c->superio, false); |
f3db354c FB |
478 | /* |
479 | * The floppy also uses 0x3f0 and 0x3f1. | |
480 | * But we do not emulate a floppy, so just set it here. | |
481 | */ | |
bcc37e24 JK |
482 | memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, |
483 | &vt82c->superio); | |
edf79e66 HC |
484 | } |
485 | ||
728d8910 | 486 | ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn) |
edf79e66 HC |
487 | { |
488 | PCIDevice *d; | |
489 | ||
417349e6 GA |
490 | d = pci_create_simple_multifunction(bus, devfn, true, |
491 | TYPE_VT82C686B_DEVICE); | |
edf79e66 | 492 | |
2ae0e48d | 493 | return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); |
edf79e66 HC |
494 | } |
495 | ||
40021f08 AL |
496 | static void via_class_init(ObjectClass *klass, void *data) |
497 | { | |
39bffca2 | 498 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
499 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
500 | ||
9af21dbe | 501 | k->realize = vt82c686b_realize; |
40021f08 AL |
502 | k->config_write = vt82c686b_write_config; |
503 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
504 | k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; | |
505 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
506 | k->revision = 0x40; | |
9dc1a769 | 507 | dc->reset = vt82c686b_isa_reset; |
39bffca2 | 508 | dc->desc = "ISA bridge"; |
39bffca2 | 509 | dc->vmsd = &vmstate_via; |
04916ee9 MA |
510 | /* |
511 | * Reason: part of VIA VT82C686 southbridge, needs to be wired up, | |
c3a09ff6 | 512 | * e.g. by mips_fuloong2e_init() |
04916ee9 | 513 | */ |
e90f2a8c | 514 | dc->user_creatable = false; |
40021f08 AL |
515 | } |
516 | ||
8c43a6f0 | 517 | static const TypeInfo via_info = { |
417349e6 | 518 | .name = TYPE_VT82C686B_DEVICE, |
39bffca2 AL |
519 | .parent = TYPE_PCI_DEVICE, |
520 | .instance_size = sizeof(VT82C686BState), | |
521 | .class_init = via_class_init, | |
fd3b02c8 EH |
522 | .interfaces = (InterfaceInfo[]) { |
523 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
524 | { }, | |
525 | }, | |
edf79e66 HC |
526 | }; |
527 | ||
98cf824b PMD |
528 | static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) |
529 | { | |
530 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | |
531 | ||
532 | sc->serial.count = 2; | |
533 | sc->parallel.count = 1; | |
534 | sc->ide.count = 0; | |
535 | sc->floppy.count = 1; | |
536 | } | |
537 | ||
538 | static const TypeInfo via_superio_info = { | |
539 | .name = TYPE_VT82C686B_SUPERIO, | |
540 | .parent = TYPE_ISA_SUPERIO, | |
541 | .instance_size = sizeof(ISASuperIODevice), | |
542 | .class_size = sizeof(ISASuperIOClass), | |
543 | .class_init = vt82c686b_superio_class_init, | |
544 | }; | |
545 | ||
83f7d43a | 546 | static void vt82c686b_register_types(void) |
edf79e66 | 547 | { |
83f7d43a AF |
548 | type_register_static(&via_ac97_info); |
549 | type_register_static(&via_mc97_info); | |
550 | type_register_static(&via_pm_info); | |
98cf824b | 551 | type_register_static(&via_superio_info); |
39bffca2 | 552 | type_register_static(&via_info); |
edf79e66 | 553 | } |
83f7d43a AF |
554 | |
555 | type_init(vt82c686b_register_types) |