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Commit | Line | Data |
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edf79e66 HC |
1 | /* |
2 | * VT82C686B south bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) | |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
7 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
edf79e66 HC |
11 | */ |
12 | ||
0430891c | 13 | #include "qemu/osdep.h" |
0d09e41a | 14 | #include "hw/isa/vt82c686.h" |
83c9f4ca | 15 | #include "hw/pci/pci.h" |
a27bd6c7 | 16 | #include "hw/qdev-properties.h" |
0d09e41a | 17 | #include "hw/isa/isa.h" |
98cf824b | 18 | #include "hw/isa/superio.h" |
83c9f4ca | 19 | #include "hw/sysbus.h" |
d6454270 | 20 | #include "migration/vmstate.h" |
0d09e41a PB |
21 | #include "hw/mips/mips.h" |
22 | #include "hw/isa/apm.h" | |
23 | #include "hw/acpi/acpi.h" | |
24 | #include "hw/i2c/pm_smbus.h" | |
9307d06d | 25 | #include "qapi/error.h" |
0b8fa32f | 26 | #include "qemu/module.h" |
1de7afc9 | 27 | #include "qemu/timer.h" |
022c62cb | 28 | #include "exec/address-spaces.h" |
db1015e9 | 29 | #include "qom/object.h" |
edf79e66 | 30 | |
f3db354c | 31 | /* #define DEBUG_VT82C686B */ |
edf79e66 HC |
32 | |
33 | #ifdef DEBUG_VT82C686B | |
a89f364a | 34 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) |
edf79e66 HC |
35 | #else |
36 | #define DPRINTF(fmt, ...) | |
37 | #endif | |
38 | ||
f3db354c | 39 | typedef struct SuperIOConfig { |
9feb8ade | 40 | uint8_t config[0x100]; |
edf79e66 HC |
41 | uint8_t index; |
42 | uint8_t data; | |
43 | } SuperIOConfig; | |
44 | ||
0f798461 | 45 | struct VT82C686BISAState { |
edf79e66 | 46 | PCIDevice dev; |
bcc37e24 | 47 | MemoryRegion superio; |
edf79e66 | 48 | SuperIOConfig superio_conf; |
db1015e9 | 49 | }; |
edf79e66 | 50 | |
0f798461 | 51 | OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA) |
417349e6 | 52 | |
bcc37e24 JK |
53 | static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, |
54 | unsigned size) | |
edf79e66 | 55 | { |
edf79e66 HC |
56 | SuperIOConfig *superio_conf = opaque; |
57 | ||
b2bedb21 | 58 | DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); |
edf79e66 HC |
59 | if (addr == 0x3f0) { |
60 | superio_conf->index = data & 0xff; | |
61 | } else { | |
b196d969 | 62 | bool can_write = true; |
edf79e66 HC |
63 | /* 0x3f1 */ |
64 | switch (superio_conf->index) { | |
65 | case 0x00 ... 0xdf: | |
66 | case 0xe4: | |
67 | case 0xe5: | |
68 | case 0xe9 ... 0xed: | |
69 | case 0xf3: | |
70 | case 0xf5: | |
71 | case 0xf7: | |
72 | case 0xf9 ... 0xfb: | |
73 | case 0xfd ... 0xff: | |
b196d969 HZ |
74 | can_write = false; |
75 | break; | |
76 | case 0xe7: | |
77 | if ((data & 0xff) != 0xfe) { | |
78 | DPRINTF("change uart 1 base. unsupported yet\n"); | |
79 | can_write = false; | |
80 | } | |
81 | break; | |
82 | case 0xe8: | |
83 | if ((data & 0xff) != 0xbe) { | |
84 | DPRINTF("change uart 2 base. unsupported yet\n"); | |
85 | can_write = false; | |
86 | } | |
edf79e66 HC |
87 | break; |
88 | default: | |
b196d969 | 89 | break; |
edf79e66 | 90 | |
edf79e66 | 91 | } |
b196d969 HZ |
92 | if (can_write) { |
93 | superio_conf->config[superio_conf->index] = data & 0xff; | |
94 | } | |
edf79e66 HC |
95 | } |
96 | } | |
97 | ||
bcc37e24 | 98 | static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) |
edf79e66 HC |
99 | { |
100 | SuperIOConfig *superio_conf = opaque; | |
101 | ||
b2bedb21 | 102 | DPRINTF("superio_ioport_readb address 0x%x\n", addr); |
f3db354c | 103 | return superio_conf->config[superio_conf->index]; |
edf79e66 HC |
104 | } |
105 | ||
bcc37e24 JK |
106 | static const MemoryRegionOps superio_ops = { |
107 | .read = superio_ioport_readb, | |
108 | .write = superio_ioport_writeb, | |
109 | .endianness = DEVICE_NATIVE_ENDIAN, | |
110 | .impl = { | |
111 | .min_access_size = 1, | |
112 | .max_access_size = 1, | |
113 | }, | |
114 | }; | |
115 | ||
9dc1a769 | 116 | static void vt82c686b_isa_reset(DeviceState *dev) |
edf79e66 | 117 | { |
0f798461 | 118 | VT82C686BISAState *vt82c = VT82C686B_ISA(dev); |
9dc1a769 | 119 | uint8_t *pci_conf = vt82c->dev.config; |
edf79e66 HC |
120 | |
121 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
122 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
123 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
124 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
125 | ||
126 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ | |
127 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ | |
128 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ | |
129 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ | |
130 | pci_conf[0x59] = 0x04; | |
131 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ | |
132 | pci_conf[0x5f] = 0x04; | |
133 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ | |
134 | ||
135 | vt82c->superio_conf.config[0xe0] = 0x3c; | |
136 | vt82c->superio_conf.config[0xe2] = 0x03; | |
137 | vt82c->superio_conf.config[0xe3] = 0xfc; | |
138 | vt82c->superio_conf.config[0xe6] = 0xde; | |
139 | vt82c->superio_conf.config[0xe7] = 0xfe; | |
140 | vt82c->superio_conf.config[0xe8] = 0xbe; | |
141 | } | |
142 | ||
143 | /* write config pci function0 registers. PCI-ISA bridge */ | |
f3db354c | 144 | static void vt82c686b_write_config(PCIDevice *d, uint32_t address, |
edf79e66 HC |
145 | uint32_t val, int len) |
146 | { | |
0f798461 | 147 | VT82C686BISAState *vt686 = VT82C686B_ISA(d); |
edf79e66 | 148 | |
b2bedb21 | 149 | DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", |
edf79e66 HC |
150 | address, val, len); |
151 | ||
152 | pci_default_write_config(d, address, val, len); | |
153 | if (address == 0x85) { /* enable or disable super IO configure */ | |
bcc37e24 | 154 | memory_region_set_enabled(&vt686->superio, val & 0x2); |
edf79e66 HC |
155 | } |
156 | } | |
157 | ||
158 | #define ACPI_DBG_IO_ADDR 0xb044 | |
159 | ||
db1015e9 | 160 | struct VT686PMState { |
edf79e66 | 161 | PCIDevice dev; |
a2902821 | 162 | MemoryRegion io; |
355bf2e5 | 163 | ACPIREGS ar; |
edf79e66 | 164 | APMState apm; |
edf79e66 HC |
165 | PMSMBus smb; |
166 | uint32_t smb_io_base; | |
db1015e9 | 167 | }; |
edf79e66 | 168 | |
e6340505 | 169 | OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM) |
417349e6 | 170 | |
edf79e66 HC |
171 | static void pm_update_sci(VT686PMState *s) |
172 | { | |
173 | int sci_level, pmsts; | |
edf79e66 | 174 | |
2886be1b | 175 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 176 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
04dc308f IY |
177 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
178 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
179 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
180 | ACPI_BITMASK_TIMER_ENABLE)) != 0); | |
9e64f8a3 | 181 | pci_set_irq(&s->dev, sci_level); |
edf79e66 | 182 | /* schedule a timer interruption if needed */ |
355bf2e5 | 183 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 184 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
edf79e66 HC |
185 | } |
186 | ||
355bf2e5 | 187 | static void pm_tmr_timer(ACPIREGS *ar) |
edf79e66 | 188 | { |
355bf2e5 | 189 | VT686PMState *s = container_of(ar, VT686PMState, ar); |
edf79e66 HC |
190 | pm_update_sci(s); |
191 | } | |
192 | ||
edf79e66 HC |
193 | static void pm_io_space_update(VT686PMState *s) |
194 | { | |
195 | uint32_t pm_io_base; | |
196 | ||
a2902821 GH |
197 | pm_io_base = pci_get_long(s->dev.config + 0x40); |
198 | pm_io_base &= 0xffc0; | |
edf79e66 | 199 | |
a2902821 GH |
200 | memory_region_transaction_begin(); |
201 | memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); | |
202 | memory_region_set_address(&s->io, pm_io_base); | |
203 | memory_region_transaction_commit(); | |
edf79e66 HC |
204 | } |
205 | ||
206 | static void pm_write_config(PCIDevice *d, | |
207 | uint32_t address, uint32_t val, int len) | |
208 | { | |
b2bedb21 | 209 | DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", |
edf79e66 HC |
210 | address, val, len); |
211 | pci_default_write_config(d, address, val, len); | |
212 | } | |
213 | ||
214 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
215 | { | |
216 | VT686PMState *s = opaque; | |
217 | ||
218 | pm_io_space_update(s); | |
219 | return 0; | |
220 | } | |
221 | ||
222 | static const VMStateDescription vmstate_acpi = { | |
223 | .name = "vt82c686b_pm", | |
224 | .version_id = 1, | |
225 | .minimum_version_id = 1, | |
edf79e66 | 226 | .post_load = vmstate_acpi_post_load, |
d49805ae | 227 | .fields = (VMStateField[]) { |
edf79e66 | 228 | VMSTATE_PCI_DEVICE(dev, VT686PMState), |
355bf2e5 GH |
229 | VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), |
230 | VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), | |
231 | VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), | |
edf79e66 | 232 | VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), |
e720677e | 233 | VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState), |
355bf2e5 | 234 | VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), |
edf79e66 HC |
235 | VMSTATE_END_OF_LIST() |
236 | } | |
237 | }; | |
238 | ||
edf79e66 | 239 | /* vt82c686 pm init */ |
9af21dbe | 240 | static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 241 | { |
e6340505 | 242 | VT686PMState *s = VT82C686B_PM(dev); |
edf79e66 HC |
243 | uint8_t *pci_conf; |
244 | ||
245 | pci_conf = s->dev.config; | |
edf79e66 HC |
246 | pci_set_word(pci_conf + PCI_COMMAND, 0); |
247 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | | |
248 | PCI_STATUS_DEVSEL_MEDIUM); | |
249 | ||
250 | /* 0x48-0x4B is Power Management I/O Base */ | |
251 | pci_set_long(pci_conf + 0x48, 0x00000001); | |
252 | ||
253 | /* SMB ports:0xeee0~0xeeef */ | |
f3db354c | 254 | s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0); |
edf79e66 HC |
255 | pci_conf[0x90] = s->smb_io_base | 1; |
256 | pci_conf[0x91] = s->smb_io_base >> 8; | |
257 | pci_conf[0xd2] = 0x90; | |
a30c34d2 | 258 | pm_smbus_init(DEVICE(s), &s->smb, false); |
798512e5 | 259 | memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); |
edf79e66 | 260 | |
42d8a3cf | 261 | apm_init(dev, &s->apm, NULL, s); |
edf79e66 | 262 | |
1437c94b | 263 | memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64); |
a2902821 GH |
264 | memory_region_set_enabled(&s->io, false); |
265 | memory_region_add_subregion(get_system_io(), 0, &s->io); | |
edf79e66 | 266 | |
77d58b1e | 267 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 268 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
9a10bbb4 | 269 | acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); |
edf79e66 HC |
270 | } |
271 | ||
40021f08 AL |
272 | static Property via_pm_properties[] = { |
273 | DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), | |
274 | DEFINE_PROP_END_OF_LIST(), | |
275 | }; | |
276 | ||
277 | static void via_pm_class_init(ObjectClass *klass, void *data) | |
278 | { | |
39bffca2 | 279 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
280 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
281 | ||
9af21dbe | 282 | k->realize = vt82c686b_pm_realize; |
40021f08 AL |
283 | k->config_write = pm_write_config; |
284 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
285 | k->device_id = PCI_DEVICE_ID_VIA_ACPI; | |
286 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
287 | k->revision = 0x40; | |
39bffca2 AL |
288 | dc->desc = "PM"; |
289 | dc->vmsd = &vmstate_acpi; | |
125ee0ed | 290 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
4f67d30b | 291 | device_class_set_props(dc, via_pm_properties); |
40021f08 AL |
292 | } |
293 | ||
8c43a6f0 | 294 | static const TypeInfo via_pm_info = { |
e6340505 | 295 | .name = TYPE_VT82C686B_PM, |
39bffca2 AL |
296 | .parent = TYPE_PCI_DEVICE, |
297 | .instance_size = sizeof(VT686PMState), | |
298 | .class_init = via_pm_class_init, | |
fd3b02c8 EH |
299 | .interfaces = (InterfaceInfo[]) { |
300 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
301 | { }, | |
302 | }, | |
edf79e66 HC |
303 | }; |
304 | ||
edf79e66 HC |
305 | static const VMStateDescription vmstate_via = { |
306 | .name = "vt82c686b", | |
307 | .version_id = 1, | |
308 | .minimum_version_id = 1, | |
d49805ae | 309 | .fields = (VMStateField[]) { |
0f798461 | 310 | VMSTATE_PCI_DEVICE(dev, VT82C686BISAState), |
edf79e66 HC |
311 | VMSTATE_END_OF_LIST() |
312 | } | |
313 | }; | |
314 | ||
315 | /* init the PCI-to-ISA bridge */ | |
9af21dbe | 316 | static void vt82c686b_realize(PCIDevice *d, Error **errp) |
edf79e66 | 317 | { |
0f798461 | 318 | VT82C686BISAState *vt82c = VT82C686B_ISA(d); |
edf79e66 | 319 | uint8_t *pci_conf; |
bcc37e24 | 320 | ISABus *isa_bus; |
edf79e66 HC |
321 | uint8_t *wmask; |
322 | int i; | |
323 | ||
bb2ed009 | 324 | isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), |
d10e5432 MA |
325 | pci_address_space_io(d), errp); |
326 | if (!isa_bus) { | |
327 | return; | |
328 | } | |
edf79e66 HC |
329 | |
330 | pci_conf = d->config; | |
edf79e66 | 331 | pci_config_set_prog_interface(pci_conf, 0x0); |
edf79e66 HC |
332 | |
333 | wmask = d->wmask; | |
334 | for (i = 0x00; i < 0xff; i++) { | |
f3db354c FB |
335 | if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) { |
336 | wmask[i] = 0x00; | |
337 | } | |
edf79e66 HC |
338 | } |
339 | ||
db10ca90 | 340 | memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops, |
2c9b15ca | 341 | &vt82c->superio_conf, "superio", 2); |
bcc37e24 | 342 | memory_region_set_enabled(&vt82c->superio, false); |
f3db354c FB |
343 | /* |
344 | * The floppy also uses 0x3f0 and 0x3f1. | |
345 | * But we do not emulate a floppy, so just set it here. | |
346 | */ | |
bcc37e24 JK |
347 | memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, |
348 | &vt82c->superio); | |
edf79e66 HC |
349 | } |
350 | ||
40021f08 AL |
351 | static void via_class_init(ObjectClass *klass, void *data) |
352 | { | |
39bffca2 | 353 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
354 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
355 | ||
9af21dbe | 356 | k->realize = vt82c686b_realize; |
40021f08 AL |
357 | k->config_write = vt82c686b_write_config; |
358 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
359 | k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; | |
360 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
361 | k->revision = 0x40; | |
9dc1a769 | 362 | dc->reset = vt82c686b_isa_reset; |
39bffca2 | 363 | dc->desc = "ISA bridge"; |
39bffca2 | 364 | dc->vmsd = &vmstate_via; |
04916ee9 MA |
365 | /* |
366 | * Reason: part of VIA VT82C686 southbridge, needs to be wired up, | |
c3a09ff6 | 367 | * e.g. by mips_fuloong2e_init() |
04916ee9 | 368 | */ |
e90f2a8c | 369 | dc->user_creatable = false; |
40021f08 AL |
370 | } |
371 | ||
8c43a6f0 | 372 | static const TypeInfo via_info = { |
0f798461 | 373 | .name = TYPE_VT82C686B_ISA, |
39bffca2 | 374 | .parent = TYPE_PCI_DEVICE, |
0f798461 | 375 | .instance_size = sizeof(VT82C686BISAState), |
39bffca2 | 376 | .class_init = via_class_init, |
fd3b02c8 EH |
377 | .interfaces = (InterfaceInfo[]) { |
378 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
379 | { }, | |
380 | }, | |
edf79e66 HC |
381 | }; |
382 | ||
98cf824b PMD |
383 | static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) |
384 | { | |
385 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | |
386 | ||
387 | sc->serial.count = 2; | |
388 | sc->parallel.count = 1; | |
389 | sc->ide.count = 0; | |
390 | sc->floppy.count = 1; | |
391 | } | |
392 | ||
393 | static const TypeInfo via_superio_info = { | |
394 | .name = TYPE_VT82C686B_SUPERIO, | |
395 | .parent = TYPE_ISA_SUPERIO, | |
396 | .instance_size = sizeof(ISASuperIODevice), | |
397 | .class_size = sizeof(ISASuperIOClass), | |
398 | .class_init = vt82c686b_superio_class_init, | |
399 | }; | |
400 | ||
83f7d43a | 401 | static void vt82c686b_register_types(void) |
edf79e66 | 402 | { |
83f7d43a | 403 | type_register_static(&via_pm_info); |
98cf824b | 404 | type_register_static(&via_superio_info); |
39bffca2 | 405 | type_register_static(&via_info); |
edf79e66 | 406 | } |
83f7d43a AF |
407 | |
408 | type_init(vt82c686b_register_types) |