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Commit | Line | Data |
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edf79e66 HC |
1 | /* |
2 | * VT82C686B south bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) | |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
7 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
edf79e66 HC |
11 | */ |
12 | ||
0430891c | 13 | #include "qemu/osdep.h" |
0d09e41a PB |
14 | #include "hw/isa/vt82c686.h" |
15 | #include "hw/i2c/i2c.h" | |
83c9f4ca | 16 | #include "hw/pci/pci.h" |
a27bd6c7 | 17 | #include "hw/qdev-properties.h" |
0d09e41a | 18 | #include "hw/isa/isa.h" |
98cf824b | 19 | #include "hw/isa/superio.h" |
83c9f4ca | 20 | #include "hw/sysbus.h" |
d6454270 | 21 | #include "migration/vmstate.h" |
0d09e41a PB |
22 | #include "hw/mips/mips.h" |
23 | #include "hw/isa/apm.h" | |
24 | #include "hw/acpi/acpi.h" | |
25 | #include "hw/i2c/pm_smbus.h" | |
9307d06d | 26 | #include "qapi/error.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
1de7afc9 | 28 | #include "qemu/timer.h" |
022c62cb | 29 | #include "exec/address-spaces.h" |
db1015e9 | 30 | #include "qom/object.h" |
edf79e66 | 31 | |
f3db354c | 32 | /* #define DEBUG_VT82C686B */ |
edf79e66 HC |
33 | |
34 | #ifdef DEBUG_VT82C686B | |
a89f364a | 35 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) |
edf79e66 HC |
36 | #else |
37 | #define DPRINTF(fmt, ...) | |
38 | #endif | |
39 | ||
f3db354c | 40 | typedef struct SuperIOConfig { |
9feb8ade | 41 | uint8_t config[0x100]; |
edf79e66 HC |
42 | uint8_t index; |
43 | uint8_t data; | |
44 | } SuperIOConfig; | |
45 | ||
db1015e9 | 46 | struct VT82C686BState { |
edf79e66 | 47 | PCIDevice dev; |
bcc37e24 | 48 | MemoryRegion superio; |
edf79e66 | 49 | SuperIOConfig superio_conf; |
db1015e9 | 50 | }; |
edf79e66 | 51 | |
e6340505 BZ |
52 | #define TYPE_VT82C686B "VT82C686B" |
53 | OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BState, VT82C686B) | |
417349e6 | 54 | |
bcc37e24 JK |
55 | static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, |
56 | unsigned size) | |
edf79e66 | 57 | { |
edf79e66 HC |
58 | SuperIOConfig *superio_conf = opaque; |
59 | ||
b2bedb21 | 60 | DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); |
edf79e66 HC |
61 | if (addr == 0x3f0) { |
62 | superio_conf->index = data & 0xff; | |
63 | } else { | |
b196d969 | 64 | bool can_write = true; |
edf79e66 HC |
65 | /* 0x3f1 */ |
66 | switch (superio_conf->index) { | |
67 | case 0x00 ... 0xdf: | |
68 | case 0xe4: | |
69 | case 0xe5: | |
70 | case 0xe9 ... 0xed: | |
71 | case 0xf3: | |
72 | case 0xf5: | |
73 | case 0xf7: | |
74 | case 0xf9 ... 0xfb: | |
75 | case 0xfd ... 0xff: | |
b196d969 HZ |
76 | can_write = false; |
77 | break; | |
78 | case 0xe7: | |
79 | if ((data & 0xff) != 0xfe) { | |
80 | DPRINTF("change uart 1 base. unsupported yet\n"); | |
81 | can_write = false; | |
82 | } | |
83 | break; | |
84 | case 0xe8: | |
85 | if ((data & 0xff) != 0xbe) { | |
86 | DPRINTF("change uart 2 base. unsupported yet\n"); | |
87 | can_write = false; | |
88 | } | |
edf79e66 HC |
89 | break; |
90 | default: | |
b196d969 | 91 | break; |
edf79e66 | 92 | |
edf79e66 | 93 | } |
b196d969 HZ |
94 | if (can_write) { |
95 | superio_conf->config[superio_conf->index] = data & 0xff; | |
96 | } | |
edf79e66 HC |
97 | } |
98 | } | |
99 | ||
bcc37e24 | 100 | static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) |
edf79e66 HC |
101 | { |
102 | SuperIOConfig *superio_conf = opaque; | |
103 | ||
b2bedb21 | 104 | DPRINTF("superio_ioport_readb address 0x%x\n", addr); |
f3db354c | 105 | return superio_conf->config[superio_conf->index]; |
edf79e66 HC |
106 | } |
107 | ||
bcc37e24 JK |
108 | static const MemoryRegionOps superio_ops = { |
109 | .read = superio_ioport_readb, | |
110 | .write = superio_ioport_writeb, | |
111 | .endianness = DEVICE_NATIVE_ENDIAN, | |
112 | .impl = { | |
113 | .min_access_size = 1, | |
114 | .max_access_size = 1, | |
115 | }, | |
116 | }; | |
117 | ||
9dc1a769 | 118 | static void vt82c686b_isa_reset(DeviceState *dev) |
edf79e66 | 119 | { |
e6340505 | 120 | VT82C686BState *vt82c = VT82C686B(dev); |
9dc1a769 | 121 | uint8_t *pci_conf = vt82c->dev.config; |
edf79e66 HC |
122 | |
123 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
124 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
125 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
126 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
127 | ||
128 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ | |
129 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ | |
130 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ | |
131 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ | |
132 | pci_conf[0x59] = 0x04; | |
133 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ | |
134 | pci_conf[0x5f] = 0x04; | |
135 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ | |
136 | ||
137 | vt82c->superio_conf.config[0xe0] = 0x3c; | |
138 | vt82c->superio_conf.config[0xe2] = 0x03; | |
139 | vt82c->superio_conf.config[0xe3] = 0xfc; | |
140 | vt82c->superio_conf.config[0xe6] = 0xde; | |
141 | vt82c->superio_conf.config[0xe7] = 0xfe; | |
142 | vt82c->superio_conf.config[0xe8] = 0xbe; | |
143 | } | |
144 | ||
145 | /* write config pci function0 registers. PCI-ISA bridge */ | |
f3db354c | 146 | static void vt82c686b_write_config(PCIDevice *d, uint32_t address, |
edf79e66 HC |
147 | uint32_t val, int len) |
148 | { | |
e6340505 | 149 | VT82C686BState *vt686 = VT82C686B(d); |
edf79e66 | 150 | |
b2bedb21 | 151 | DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", |
edf79e66 HC |
152 | address, val, len); |
153 | ||
154 | pci_default_write_config(d, address, val, len); | |
155 | if (address == 0x85) { /* enable or disable super IO configure */ | |
bcc37e24 | 156 | memory_region_set_enabled(&vt686->superio, val & 0x2); |
edf79e66 HC |
157 | } |
158 | } | |
159 | ||
160 | #define ACPI_DBG_IO_ADDR 0xb044 | |
161 | ||
db1015e9 | 162 | struct VT686PMState { |
edf79e66 | 163 | PCIDevice dev; |
a2902821 | 164 | MemoryRegion io; |
355bf2e5 | 165 | ACPIREGS ar; |
edf79e66 | 166 | APMState apm; |
edf79e66 HC |
167 | PMSMBus smb; |
168 | uint32_t smb_io_base; | |
db1015e9 | 169 | }; |
edf79e66 | 170 | |
5a4856ed | 171 | struct VIAAC97State { |
edf79e66 | 172 | PCIDevice dev; |
db1015e9 | 173 | }; |
edf79e66 | 174 | |
5a4856ed | 175 | struct VIAMC97State { |
edf79e66 | 176 | PCIDevice dev; |
db1015e9 | 177 | }; |
edf79e66 | 178 | |
e6340505 BZ |
179 | #define TYPE_VT82C686B_PM "VT82C686B_PM" |
180 | OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM) | |
417349e6 | 181 | |
e6340505 BZ |
182 | #define TYPE_VIA_MC97 "VIA_MC97" |
183 | OBJECT_DECLARE_SIMPLE_TYPE(VIAMC97State, VIA_MC97) | |
417349e6 | 184 | |
e6340505 BZ |
185 | #define TYPE_VIA_AC97 "VIA_AC97" |
186 | OBJECT_DECLARE_SIMPLE_TYPE(VIAAC97State, VIA_AC97) | |
417349e6 | 187 | |
edf79e66 HC |
188 | static void pm_update_sci(VT686PMState *s) |
189 | { | |
190 | int sci_level, pmsts; | |
edf79e66 | 191 | |
2886be1b | 192 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 193 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
04dc308f IY |
194 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
195 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
196 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
197 | ACPI_BITMASK_TIMER_ENABLE)) != 0); | |
9e64f8a3 | 198 | pci_set_irq(&s->dev, sci_level); |
edf79e66 | 199 | /* schedule a timer interruption if needed */ |
355bf2e5 | 200 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 201 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
edf79e66 HC |
202 | } |
203 | ||
355bf2e5 | 204 | static void pm_tmr_timer(ACPIREGS *ar) |
edf79e66 | 205 | { |
355bf2e5 | 206 | VT686PMState *s = container_of(ar, VT686PMState, ar); |
edf79e66 HC |
207 | pm_update_sci(s); |
208 | } | |
209 | ||
edf79e66 HC |
210 | static void pm_io_space_update(VT686PMState *s) |
211 | { | |
212 | uint32_t pm_io_base; | |
213 | ||
a2902821 GH |
214 | pm_io_base = pci_get_long(s->dev.config + 0x40); |
215 | pm_io_base &= 0xffc0; | |
edf79e66 | 216 | |
a2902821 GH |
217 | memory_region_transaction_begin(); |
218 | memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); | |
219 | memory_region_set_address(&s->io, pm_io_base); | |
220 | memory_region_transaction_commit(); | |
edf79e66 HC |
221 | } |
222 | ||
223 | static void pm_write_config(PCIDevice *d, | |
224 | uint32_t address, uint32_t val, int len) | |
225 | { | |
b2bedb21 | 226 | DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", |
edf79e66 HC |
227 | address, val, len); |
228 | pci_default_write_config(d, address, val, len); | |
229 | } | |
230 | ||
231 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
232 | { | |
233 | VT686PMState *s = opaque; | |
234 | ||
235 | pm_io_space_update(s); | |
236 | return 0; | |
237 | } | |
238 | ||
239 | static const VMStateDescription vmstate_acpi = { | |
240 | .name = "vt82c686b_pm", | |
241 | .version_id = 1, | |
242 | .minimum_version_id = 1, | |
edf79e66 | 243 | .post_load = vmstate_acpi_post_load, |
d49805ae | 244 | .fields = (VMStateField[]) { |
edf79e66 | 245 | VMSTATE_PCI_DEVICE(dev, VT686PMState), |
355bf2e5 GH |
246 | VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), |
247 | VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), | |
248 | VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), | |
edf79e66 | 249 | VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), |
e720677e | 250 | VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState), |
355bf2e5 | 251 | VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), |
edf79e66 HC |
252 | VMSTATE_END_OF_LIST() |
253 | } | |
254 | }; | |
255 | ||
256 | /* | |
257 | * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() | |
258 | * just register a PCI device now, functionalities will be implemented later. | |
259 | */ | |
260 | ||
9af21dbe | 261 | static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 262 | { |
e6340505 | 263 | VIAAC97State *s = VIA_AC97(dev); |
edf79e66 HC |
264 | uint8_t *pci_conf = s->dev.config; |
265 | ||
edf79e66 HC |
266 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
267 | PCI_COMMAND_PARITY); | |
268 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | | |
269 | PCI_STATUS_DEVSEL_MEDIUM); | |
270 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); | |
edf79e66 HC |
271 | } |
272 | ||
273 | void vt82c686b_ac97_init(PCIBus *bus, int devfn) | |
274 | { | |
275 | PCIDevice *dev; | |
276 | ||
e6340505 | 277 | dev = pci_new(devfn, TYPE_VIA_AC97); |
9307d06d | 278 | pci_realize_and_unref(dev, bus, &error_fatal); |
edf79e66 HC |
279 | } |
280 | ||
40021f08 AL |
281 | static void via_ac97_class_init(ObjectClass *klass, void *data) |
282 | { | |
39bffca2 | 283 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
284 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
285 | ||
9af21dbe | 286 | k->realize = vt82c686b_ac97_realize; |
40021f08 AL |
287 | k->vendor_id = PCI_VENDOR_ID_VIA; |
288 | k->device_id = PCI_DEVICE_ID_VIA_AC97; | |
289 | k->revision = 0x50; | |
290 | k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; | |
125ee0ed | 291 | set_bit(DEVICE_CATEGORY_SOUND, dc->categories); |
39bffca2 | 292 | dc->desc = "AC97"; |
40021f08 AL |
293 | } |
294 | ||
8c43a6f0 | 295 | static const TypeInfo via_ac97_info = { |
e6340505 | 296 | .name = TYPE_VIA_AC97, |
39bffca2 | 297 | .parent = TYPE_PCI_DEVICE, |
5a4856ed | 298 | .instance_size = sizeof(VIAAC97State), |
39bffca2 | 299 | .class_init = via_ac97_class_init, |
fd3b02c8 EH |
300 | .interfaces = (InterfaceInfo[]) { |
301 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
302 | { }, | |
303 | }, | |
edf79e66 HC |
304 | }; |
305 | ||
9af21dbe | 306 | static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 307 | { |
e6340505 | 308 | VIAMC97State *s = VIA_MC97(dev); |
edf79e66 HC |
309 | uint8_t *pci_conf = s->dev.config; |
310 | ||
edf79e66 HC |
311 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
312 | PCI_COMMAND_VGA_PALETTE); | |
313 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
314 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); | |
edf79e66 HC |
315 | } |
316 | ||
317 | void vt82c686b_mc97_init(PCIBus *bus, int devfn) | |
318 | { | |
319 | PCIDevice *dev; | |
320 | ||
e6340505 | 321 | dev = pci_new(devfn, TYPE_VIA_MC97); |
9307d06d | 322 | pci_realize_and_unref(dev, bus, &error_fatal); |
edf79e66 HC |
323 | } |
324 | ||
40021f08 AL |
325 | static void via_mc97_class_init(ObjectClass *klass, void *data) |
326 | { | |
39bffca2 | 327 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
328 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
329 | ||
9af21dbe | 330 | k->realize = vt82c686b_mc97_realize; |
40021f08 AL |
331 | k->vendor_id = PCI_VENDOR_ID_VIA; |
332 | k->device_id = PCI_DEVICE_ID_VIA_MC97; | |
333 | k->class_id = PCI_CLASS_COMMUNICATION_OTHER; | |
334 | k->revision = 0x30; | |
125ee0ed | 335 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
39bffca2 | 336 | dc->desc = "MC97"; |
40021f08 AL |
337 | } |
338 | ||
8c43a6f0 | 339 | static const TypeInfo via_mc97_info = { |
e6340505 | 340 | .name = TYPE_VIA_MC97, |
39bffca2 | 341 | .parent = TYPE_PCI_DEVICE, |
5a4856ed | 342 | .instance_size = sizeof(VIAMC97State), |
39bffca2 | 343 | .class_init = via_mc97_class_init, |
fd3b02c8 EH |
344 | .interfaces = (InterfaceInfo[]) { |
345 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
346 | { }, | |
347 | }, | |
edf79e66 HC |
348 | }; |
349 | ||
edf79e66 | 350 | /* vt82c686 pm init */ |
9af21dbe | 351 | static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 352 | { |
e6340505 | 353 | VT686PMState *s = VT82C686B_PM(dev); |
edf79e66 HC |
354 | uint8_t *pci_conf; |
355 | ||
356 | pci_conf = s->dev.config; | |
edf79e66 HC |
357 | pci_set_word(pci_conf + PCI_COMMAND, 0); |
358 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | | |
359 | PCI_STATUS_DEVSEL_MEDIUM); | |
360 | ||
361 | /* 0x48-0x4B is Power Management I/O Base */ | |
362 | pci_set_long(pci_conf + 0x48, 0x00000001); | |
363 | ||
364 | /* SMB ports:0xeee0~0xeeef */ | |
f3db354c | 365 | s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0); |
edf79e66 HC |
366 | pci_conf[0x90] = s->smb_io_base | 1; |
367 | pci_conf[0x91] = s->smb_io_base >> 8; | |
368 | pci_conf[0xd2] = 0x90; | |
a30c34d2 | 369 | pm_smbus_init(DEVICE(s), &s->smb, false); |
798512e5 | 370 | memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); |
edf79e66 | 371 | |
42d8a3cf | 372 | apm_init(dev, &s->apm, NULL, s); |
edf79e66 | 373 | |
1437c94b | 374 | memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64); |
a2902821 GH |
375 | memory_region_set_enabled(&s->io, false); |
376 | memory_region_add_subregion(get_system_io(), 0, &s->io); | |
edf79e66 | 377 | |
77d58b1e | 378 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 379 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
9a10bbb4 | 380 | acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); |
edf79e66 HC |
381 | } |
382 | ||
a5c82852 AF |
383 | I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
384 | qemu_irq sci_irq) | |
edf79e66 HC |
385 | { |
386 | PCIDevice *dev; | |
387 | VT686PMState *s; | |
388 | ||
e6340505 | 389 | dev = pci_new(devfn, TYPE_VT82C686B_PM); |
edf79e66 HC |
390 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); |
391 | ||
e6340505 | 392 | s = VT82C686B_PM(dev); |
edf79e66 | 393 | |
9307d06d | 394 | pci_realize_and_unref(dev, bus, &error_fatal); |
edf79e66 HC |
395 | |
396 | return s->smb.smbus; | |
397 | } | |
398 | ||
40021f08 AL |
399 | static Property via_pm_properties[] = { |
400 | DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), | |
401 | DEFINE_PROP_END_OF_LIST(), | |
402 | }; | |
403 | ||
404 | static void via_pm_class_init(ObjectClass *klass, void *data) | |
405 | { | |
39bffca2 | 406 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
407 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
408 | ||
9af21dbe | 409 | k->realize = vt82c686b_pm_realize; |
40021f08 AL |
410 | k->config_write = pm_write_config; |
411 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
412 | k->device_id = PCI_DEVICE_ID_VIA_ACPI; | |
413 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
414 | k->revision = 0x40; | |
39bffca2 AL |
415 | dc->desc = "PM"; |
416 | dc->vmsd = &vmstate_acpi; | |
125ee0ed | 417 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
4f67d30b | 418 | device_class_set_props(dc, via_pm_properties); |
40021f08 AL |
419 | } |
420 | ||
8c43a6f0 | 421 | static const TypeInfo via_pm_info = { |
e6340505 | 422 | .name = TYPE_VT82C686B_PM, |
39bffca2 AL |
423 | .parent = TYPE_PCI_DEVICE, |
424 | .instance_size = sizeof(VT686PMState), | |
425 | .class_init = via_pm_class_init, | |
fd3b02c8 EH |
426 | .interfaces = (InterfaceInfo[]) { |
427 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
428 | { }, | |
429 | }, | |
edf79e66 HC |
430 | }; |
431 | ||
edf79e66 HC |
432 | static const VMStateDescription vmstate_via = { |
433 | .name = "vt82c686b", | |
434 | .version_id = 1, | |
435 | .minimum_version_id = 1, | |
d49805ae | 436 | .fields = (VMStateField[]) { |
edf79e66 HC |
437 | VMSTATE_PCI_DEVICE(dev, VT82C686BState), |
438 | VMSTATE_END_OF_LIST() | |
439 | } | |
440 | }; | |
441 | ||
442 | /* init the PCI-to-ISA bridge */ | |
9af21dbe | 443 | static void vt82c686b_realize(PCIDevice *d, Error **errp) |
edf79e66 | 444 | { |
e6340505 | 445 | VT82C686BState *vt82c = VT82C686B(d); |
edf79e66 | 446 | uint8_t *pci_conf; |
bcc37e24 | 447 | ISABus *isa_bus; |
edf79e66 HC |
448 | uint8_t *wmask; |
449 | int i; | |
450 | ||
bb2ed009 | 451 | isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), |
d10e5432 MA |
452 | pci_address_space_io(d), errp); |
453 | if (!isa_bus) { | |
454 | return; | |
455 | } | |
edf79e66 HC |
456 | |
457 | pci_conf = d->config; | |
edf79e66 | 458 | pci_config_set_prog_interface(pci_conf, 0x0); |
edf79e66 HC |
459 | |
460 | wmask = d->wmask; | |
461 | for (i = 0x00; i < 0xff; i++) { | |
f3db354c FB |
462 | if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) { |
463 | wmask[i] = 0x00; | |
464 | } | |
edf79e66 HC |
465 | } |
466 | ||
db10ca90 | 467 | memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops, |
2c9b15ca | 468 | &vt82c->superio_conf, "superio", 2); |
bcc37e24 | 469 | memory_region_set_enabled(&vt82c->superio, false); |
f3db354c FB |
470 | /* |
471 | * The floppy also uses 0x3f0 and 0x3f1. | |
472 | * But we do not emulate a floppy, so just set it here. | |
473 | */ | |
bcc37e24 JK |
474 | memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, |
475 | &vt82c->superio); | |
edf79e66 HC |
476 | } |
477 | ||
728d8910 | 478 | ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn) |
edf79e66 HC |
479 | { |
480 | PCIDevice *d; | |
481 | ||
e6340505 | 482 | d = pci_create_simple_multifunction(bus, devfn, true, TYPE_VT82C686B); |
2ae0e48d | 483 | return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); |
edf79e66 HC |
484 | } |
485 | ||
40021f08 AL |
486 | static void via_class_init(ObjectClass *klass, void *data) |
487 | { | |
39bffca2 | 488 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
489 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
490 | ||
9af21dbe | 491 | k->realize = vt82c686b_realize; |
40021f08 AL |
492 | k->config_write = vt82c686b_write_config; |
493 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
494 | k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; | |
495 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
496 | k->revision = 0x40; | |
9dc1a769 | 497 | dc->reset = vt82c686b_isa_reset; |
39bffca2 | 498 | dc->desc = "ISA bridge"; |
39bffca2 | 499 | dc->vmsd = &vmstate_via; |
04916ee9 MA |
500 | /* |
501 | * Reason: part of VIA VT82C686 southbridge, needs to be wired up, | |
c3a09ff6 | 502 | * e.g. by mips_fuloong2e_init() |
04916ee9 | 503 | */ |
e90f2a8c | 504 | dc->user_creatable = false; |
40021f08 AL |
505 | } |
506 | ||
8c43a6f0 | 507 | static const TypeInfo via_info = { |
e6340505 | 508 | .name = TYPE_VT82C686B, |
39bffca2 AL |
509 | .parent = TYPE_PCI_DEVICE, |
510 | .instance_size = sizeof(VT82C686BState), | |
511 | .class_init = via_class_init, | |
fd3b02c8 EH |
512 | .interfaces = (InterfaceInfo[]) { |
513 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
514 | { }, | |
515 | }, | |
edf79e66 HC |
516 | }; |
517 | ||
98cf824b PMD |
518 | static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) |
519 | { | |
520 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | |
521 | ||
522 | sc->serial.count = 2; | |
523 | sc->parallel.count = 1; | |
524 | sc->ide.count = 0; | |
525 | sc->floppy.count = 1; | |
526 | } | |
527 | ||
528 | static const TypeInfo via_superio_info = { | |
529 | .name = TYPE_VT82C686B_SUPERIO, | |
530 | .parent = TYPE_ISA_SUPERIO, | |
531 | .instance_size = sizeof(ISASuperIODevice), | |
532 | .class_size = sizeof(ISASuperIOClass), | |
533 | .class_init = vt82c686b_superio_class_init, | |
534 | }; | |
535 | ||
83f7d43a | 536 | static void vt82c686b_register_types(void) |
edf79e66 | 537 | { |
83f7d43a AF |
538 | type_register_static(&via_ac97_info); |
539 | type_register_static(&via_mc97_info); | |
540 | type_register_static(&via_pm_info); | |
98cf824b | 541 | type_register_static(&via_superio_info); |
39bffca2 | 542 | type_register_static(&via_info); |
edf79e66 | 543 | } |
83f7d43a AF |
544 | |
545 | type_init(vt82c686b_register_types) |