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d821732a MW |
1 | /* |
2 | * QEMU models for LatticeMico32 uclinux and evr32 boards. | |
3 | * | |
4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
ea99dde1 | 20 | #include "qemu/osdep.h" |
fc0187cb | 21 | #include "qemu/units.h" |
0a094a54 | 22 | #include "qemu/error-report.h" |
4771d756 | 23 | #include "cpu.h" |
83c9f4ca PB |
24 | #include "hw/sysbus.h" |
25 | #include "hw/hw.h" | |
0d09e41a | 26 | #include "hw/block/flash.h" |
83c9f4ca PB |
27 | #include "hw/boards.h" |
28 | #include "hw/loader.h" | |
d821732a | 29 | #include "elf.h" |
47b43a1f PB |
30 | #include "lm32_hwsetup.h" |
31 | #include "lm32.h" | |
022c62cb | 32 | #include "exec/address-spaces.h" |
c2ddaa62 | 33 | #include "sysemu/sysemu.h" |
d821732a MW |
34 | |
35 | typedef struct { | |
b1435596 | 36 | LM32CPU *cpu; |
a8170e5e AK |
37 | hwaddr bootstrap_pc; |
38 | hwaddr flash_base; | |
39 | hwaddr hwsetup_base; | |
40 | hwaddr initrd_base; | |
d821732a | 41 | size_t initrd_size; |
a8170e5e | 42 | hwaddr cmdline_base; |
d821732a MW |
43 | } ResetInfo; |
44 | ||
45 | static void cpu_irq_handler(void *opaque, int irq, int level) | |
46 | { | |
d8ed887b | 47 | LM32CPU *cpu = opaque; |
d8ed887b | 48 | CPUState *cs = CPU(cpu); |
d821732a MW |
49 | |
50 | if (level) { | |
c3affe56 | 51 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
d821732a | 52 | } else { |
d8ed887b | 53 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
d821732a MW |
54 | } |
55 | } | |
56 | ||
57 | static void main_cpu_reset(void *opaque) | |
58 | { | |
59 | ResetInfo *reset_info = opaque; | |
b1435596 | 60 | CPULM32State *env = &reset_info->cpu->env; |
d821732a | 61 | |
b1435596 | 62 | cpu_reset(CPU(reset_info->cpu)); |
d821732a MW |
63 | |
64 | /* init defaults */ | |
65 | env->pc = (uint32_t)reset_info->bootstrap_pc; | |
66 | env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base; | |
67 | env->regs[R_R2] = (uint32_t)reset_info->cmdline_base; | |
68 | env->regs[R_R3] = (uint32_t)reset_info->initrd_base; | |
69 | env->regs[R_R4] = (uint32_t)(reset_info->initrd_base + | |
70 | reset_info->initrd_size); | |
71 | env->eba = reset_info->flash_base; | |
72 | env->deba = reset_info->flash_base; | |
73 | } | |
74 | ||
3ef96221 | 75 | static void lm32_evr_init(MachineState *machine) |
d821732a | 76 | { |
3ef96221 | 77 | const char *kernel_filename = machine->kernel_filename; |
47dc4fa2 | 78 | LM32CPU *cpu; |
93a67402 | 79 | CPULM32State *env; |
d821732a | 80 | DriveInfo *dinfo; |
88fa8031 AK |
81 | MemoryRegion *address_space_mem = get_system_memory(); |
82 | MemoryRegion *phys_ram = g_new(MemoryRegion, 1); | |
d4ef00af | 83 | qemu_irq irq[32]; |
d821732a MW |
84 | ResetInfo *reset_info; |
85 | int i; | |
86 | ||
87 | /* memory map */ | |
a8170e5e | 88 | hwaddr flash_base = 0x04000000; |
fc0187cb PMD |
89 | size_t flash_sector_size = 256 * KiB; |
90 | size_t flash_size = 32 * MiB; | |
a8170e5e | 91 | hwaddr ram_base = 0x08000000; |
fc0187cb | 92 | size_t ram_size = 64 * MiB; |
a8170e5e AK |
93 | hwaddr timer0_base = 0x80002000; |
94 | hwaddr uart0_base = 0x80006000; | |
95 | hwaddr timer1_base = 0x8000a000; | |
d821732a MW |
96 | int uart0_irq = 0; |
97 | int timer0_irq = 1; | |
98 | int timer1_irq = 3; | |
99 | ||
7267c094 | 100 | reset_info = g_malloc0(sizeof(ResetInfo)); |
d821732a | 101 | |
6e0f9a23 | 102 | cpu = LM32_CPU(cpu_create(machine->cpu_type)); |
f41152bd | 103 | |
47dc4fa2 | 104 | env = &cpu->env; |
b1435596 | 105 | reset_info->cpu = cpu; |
d821732a MW |
106 | |
107 | reset_info->flash_base = flash_base; | |
108 | ||
b7ccb83f DM |
109 | memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram", |
110 | ram_size); | |
88fa8031 | 111 | memory_region_add_subregion(address_space_mem, ram_base, phys_ram); |
d821732a | 112 | |
d821732a MW |
113 | dinfo = drive_get(IF_PFLASH, 0, 0); |
114 | /* Spansion S29NS128P */ | |
940d5b13 | 115 | pflash_cfi02_register(flash_base, "lm32_evr.flash", flash_size, |
4be74634 | 116 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
ce14710f | 117 | flash_sector_size, |
fa1d36df | 118 | 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); |
d821732a MW |
119 | |
120 | /* create irq lines */ | |
d4ef00af | 121 | env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0)); |
d821732a MW |
122 | for (i = 0; i < 32; i++) { |
123 | irq[i] = qdev_get_gpio_in(env->pic_state, i); | |
124 | } | |
125 | ||
9bca0edb | 126 | lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0)); |
d821732a MW |
127 | sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]); |
128 | sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]); | |
129 | ||
130 | /* make sure juart isn't the first chardev */ | |
9bca0edb | 131 | env->juart_state = lm32_juart_init(serial_hd(1)); |
d821732a MW |
132 | |
133 | reset_info->bootstrap_pc = flash_base; | |
134 | ||
135 | if (kernel_filename) { | |
136 | uint64_t entry; | |
137 | int kernel_size; | |
138 | ||
4366e1db LM |
139 | kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, |
140 | &entry, NULL, NULL, | |
7ef295ea | 141 | 1, EM_LATTICEMICO32, 0, 0); |
d821732a MW |
142 | reset_info->bootstrap_pc = entry; |
143 | ||
144 | if (kernel_size < 0) { | |
145 | kernel_size = load_image_targphys(kernel_filename, ram_base, | |
146 | ram_size); | |
147 | reset_info->bootstrap_pc = ram_base; | |
148 | } | |
149 | ||
150 | if (kernel_size < 0) { | |
0a094a54 | 151 | error_report("could not load kernel '%s'", kernel_filename); |
d821732a MW |
152 | exit(1); |
153 | } | |
154 | } | |
155 | ||
156 | qemu_register_reset(main_cpu_reset, reset_info); | |
157 | } | |
158 | ||
3ef96221 | 159 | static void lm32_uclinux_init(MachineState *machine) |
d821732a | 160 | { |
3ef96221 MA |
161 | const char *kernel_filename = machine->kernel_filename; |
162 | const char *kernel_cmdline = machine->kernel_cmdline; | |
163 | const char *initrd_filename = machine->initrd_filename; | |
47dc4fa2 | 164 | LM32CPU *cpu; |
93a67402 | 165 | CPULM32State *env; |
d821732a | 166 | DriveInfo *dinfo; |
88fa8031 AK |
167 | MemoryRegion *address_space_mem = get_system_memory(); |
168 | MemoryRegion *phys_ram = g_new(MemoryRegion, 1); | |
d4ef00af | 169 | qemu_irq irq[32]; |
d821732a MW |
170 | HWSetup *hw; |
171 | ResetInfo *reset_info; | |
172 | int i; | |
173 | ||
174 | /* memory map */ | |
a8170e5e | 175 | hwaddr flash_base = 0x04000000; |
fc0187cb PMD |
176 | size_t flash_sector_size = 256 * KiB; |
177 | size_t flash_size = 32 * MiB; | |
a8170e5e | 178 | hwaddr ram_base = 0x08000000; |
fc0187cb | 179 | size_t ram_size = 64 * MiB; |
a8170e5e AK |
180 | hwaddr uart0_base = 0x80000000; |
181 | hwaddr timer0_base = 0x80002000; | |
182 | hwaddr timer1_base = 0x80010000; | |
183 | hwaddr timer2_base = 0x80012000; | |
d821732a MW |
184 | int uart0_irq = 0; |
185 | int timer0_irq = 1; | |
186 | int timer1_irq = 20; | |
187 | int timer2_irq = 21; | |
a8170e5e AK |
188 | hwaddr hwsetup_base = 0x0bffe000; |
189 | hwaddr cmdline_base = 0x0bfff000; | |
190 | hwaddr initrd_base = 0x08400000; | |
d821732a MW |
191 | size_t initrd_max = 0x01000000; |
192 | ||
7267c094 | 193 | reset_info = g_malloc0(sizeof(ResetInfo)); |
d821732a | 194 | |
6e0f9a23 | 195 | cpu = LM32_CPU(cpu_create(machine->cpu_type)); |
f41152bd | 196 | |
47dc4fa2 | 197 | env = &cpu->env; |
b1435596 | 198 | reset_info->cpu = cpu; |
d821732a MW |
199 | |
200 | reset_info->flash_base = flash_base; | |
201 | ||
b7ccb83f DM |
202 | memory_region_allocate_system_memory(phys_ram, NULL, |
203 | "lm32_uclinux.sdram", ram_size); | |
88fa8031 | 204 | memory_region_add_subregion(address_space_mem, ram_base, phys_ram); |
d821732a | 205 | |
d821732a MW |
206 | dinfo = drive_get(IF_PFLASH, 0, 0); |
207 | /* Spansion S29NS128P */ | |
940d5b13 | 208 | pflash_cfi02_register(flash_base, "lm32_uclinux.flash", flash_size, |
4be74634 | 209 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
ce14710f | 210 | flash_sector_size, |
fa1d36df | 211 | 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); |
d821732a MW |
212 | |
213 | /* create irq lines */ | |
d4ef00af | 214 | env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0)); |
d821732a MW |
215 | for (i = 0; i < 32; i++) { |
216 | irq[i] = qdev_get_gpio_in(env->pic_state, i); | |
217 | } | |
218 | ||
9bca0edb | 219 | lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0)); |
d821732a MW |
220 | sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]); |
221 | sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]); | |
222 | sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]); | |
223 | ||
224 | /* make sure juart isn't the first chardev */ | |
9bca0edb | 225 | env->juart_state = lm32_juart_init(serial_hd(1)); |
d821732a MW |
226 | |
227 | reset_info->bootstrap_pc = flash_base; | |
228 | ||
229 | if (kernel_filename) { | |
230 | uint64_t entry; | |
231 | int kernel_size; | |
232 | ||
4366e1db LM |
233 | kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, |
234 | &entry, NULL, NULL, | |
7ef295ea | 235 | 1, EM_LATTICEMICO32, 0, 0); |
d821732a MW |
236 | reset_info->bootstrap_pc = entry; |
237 | ||
238 | if (kernel_size < 0) { | |
239 | kernel_size = load_image_targphys(kernel_filename, ram_base, | |
240 | ram_size); | |
241 | reset_info->bootstrap_pc = ram_base; | |
242 | } | |
243 | ||
244 | if (kernel_size < 0) { | |
0a094a54 | 245 | error_report("could not load kernel '%s'", kernel_filename); |
d821732a MW |
246 | exit(1); |
247 | } | |
248 | } | |
249 | ||
250 | /* generate a rom with the hardware description */ | |
251 | hw = hwsetup_init(); | |
252 | hwsetup_add_cpu(hw, "LM32", 75000000); | |
253 | hwsetup_add_flash(hw, "flash", flash_base, flash_size); | |
254 | hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size); | |
255 | hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq); | |
256 | hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq); | |
257 | hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq); | |
258 | hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq); | |
259 | hwsetup_add_trailer(hw); | |
260 | hwsetup_create_rom(hw, hwsetup_base); | |
261 | hwsetup_free(hw); | |
262 | ||
263 | reset_info->hwsetup_base = hwsetup_base; | |
264 | ||
265 | if (kernel_cmdline && strlen(kernel_cmdline)) { | |
266 | pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, | |
267 | kernel_cmdline); | |
268 | reset_info->cmdline_base = cmdline_base; | |
269 | } | |
270 | ||
271 | if (initrd_filename) { | |
272 | size_t initrd_size; | |
273 | initrd_size = load_image_targphys(initrd_filename, initrd_base, | |
274 | initrd_max); | |
275 | reset_info->initrd_base = initrd_base; | |
276 | reset_info->initrd_size = initrd_size; | |
277 | } | |
278 | ||
279 | qemu_register_reset(main_cpu_reset, reset_info); | |
280 | } | |
281 | ||
8a661aea | 282 | static void lm32_evr_class_init(ObjectClass *oc, void *data) |
d821732a | 283 | { |
8a661aea AF |
284 | MachineClass *mc = MACHINE_CLASS(oc); |
285 | ||
e264d29d EH |
286 | mc->desc = "LatticeMico32 EVR32 eval system"; |
287 | mc->init = lm32_evr_init; | |
288 | mc->is_default = 1; | |
6e0f9a23 | 289 | mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full"); |
d821732a MW |
290 | } |
291 | ||
8a661aea AF |
292 | static const TypeInfo lm32_evr_type = { |
293 | .name = MACHINE_TYPE_NAME("lm32-evr"), | |
294 | .parent = TYPE_MACHINE, | |
295 | .class_init = lm32_evr_class_init, | |
296 | }; | |
e264d29d | 297 | |
8a661aea | 298 | static void lm32_uclinux_class_init(ObjectClass *oc, void *data) |
e264d29d | 299 | { |
8a661aea AF |
300 | MachineClass *mc = MACHINE_CLASS(oc); |
301 | ||
e264d29d EH |
302 | mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems"; |
303 | mc->init = lm32_uclinux_init; | |
304 | mc->is_default = 0; | |
6e0f9a23 | 305 | mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full"); |
e264d29d EH |
306 | } |
307 | ||
8a661aea AF |
308 | static const TypeInfo lm32_uclinux_type = { |
309 | .name = MACHINE_TYPE_NAME("lm32-uclinux"), | |
310 | .parent = TYPE_MACHINE, | |
311 | .class_init = lm32_uclinux_class_init, | |
312 | }; | |
313 | ||
314 | static void lm32_machine_init(void) | |
315 | { | |
316 | type_register_static(&lm32_evr_type); | |
317 | type_register_static(&lm32_uclinux_type); | |
318 | } | |
319 | ||
0e6aac87 | 320 | type_init(lm32_machine_init) |