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ea7924dc MW |
1 | /* |
2 | * QEMU model of the LatticeMico32 timer block. | |
3 | * | |
4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | * | |
20 | * Specification available at: | |
21 | * http://www.latticesemi.com/documents/mico32timer.pdf | |
22 | */ | |
23 | ||
24 | #include "hw.h" | |
25 | #include "sysbus.h" | |
26 | #include "trace.h" | |
27 | #include "qemu-timer.h" | |
28 | #include "qemu-error.h" | |
29 | ||
30 | #define DEFAULT_FREQUENCY (50*1000000) | |
31 | ||
32 | enum { | |
33 | R_SR = 0, | |
34 | R_CR, | |
35 | R_PERIOD, | |
36 | R_SNAPSHOT, | |
37 | R_MAX | |
38 | }; | |
39 | ||
40 | enum { | |
41 | SR_TO = (1 << 0), | |
42 | SR_RUN = (1 << 1), | |
43 | }; | |
44 | ||
45 | enum { | |
46 | CR_ITO = (1 << 0), | |
47 | CR_CONT = (1 << 1), | |
48 | CR_START = (1 << 2), | |
49 | CR_STOP = (1 << 3), | |
50 | }; | |
51 | ||
52 | struct LM32TimerState { | |
53 | SysBusDevice busdev; | |
d09510b2 | 54 | MemoryRegion iomem; |
ea7924dc MW |
55 | |
56 | QEMUBH *bh; | |
57 | ptimer_state *ptimer; | |
58 | ||
59 | qemu_irq irq; | |
60 | uint32_t freq_hz; | |
61 | ||
62 | uint32_t regs[R_MAX]; | |
63 | }; | |
64 | typedef struct LM32TimerState LM32TimerState; | |
65 | ||
66 | static void timer_update_irq(LM32TimerState *s) | |
67 | { | |
68 | int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO); | |
69 | ||
70 | trace_lm32_timer_irq_state(state); | |
71 | qemu_set_irq(s->irq, state); | |
72 | } | |
73 | ||
d09510b2 | 74 | static uint64_t timer_read(void *opaque, target_phys_addr_t addr, unsigned size) |
ea7924dc MW |
75 | { |
76 | LM32TimerState *s = opaque; | |
77 | uint32_t r = 0; | |
78 | ||
79 | addr >>= 2; | |
80 | switch (addr) { | |
81 | case R_SR: | |
82 | case R_CR: | |
83 | case R_PERIOD: | |
84 | r = s->regs[addr]; | |
85 | break; | |
86 | case R_SNAPSHOT: | |
87 | r = (uint32_t)ptimer_get_count(s->ptimer); | |
88 | break; | |
89 | default: | |
dd3d6775 | 90 | error_report("lm32_timer: read access to unknown register 0x" |
ea7924dc MW |
91 | TARGET_FMT_plx, addr << 2); |
92 | break; | |
93 | } | |
94 | ||
95 | trace_lm32_timer_memory_read(addr << 2, r); | |
96 | return r; | |
97 | } | |
98 | ||
d09510b2 AK |
99 | static void timer_write(void *opaque, target_phys_addr_t addr, |
100 | uint64_t value, unsigned size) | |
ea7924dc MW |
101 | { |
102 | LM32TimerState *s = opaque; | |
103 | ||
104 | trace_lm32_timer_memory_write(addr, value); | |
105 | ||
106 | addr >>= 2; | |
107 | switch (addr) { | |
108 | case R_SR: | |
109 | s->regs[R_SR] &= ~SR_TO; | |
110 | break; | |
111 | case R_CR: | |
112 | s->regs[R_CR] = value; | |
113 | if (s->regs[R_CR] & CR_START) { | |
114 | ptimer_run(s->ptimer, 1); | |
115 | } | |
116 | if (s->regs[R_CR] & CR_STOP) { | |
117 | ptimer_stop(s->ptimer); | |
118 | } | |
119 | break; | |
120 | case R_PERIOD: | |
121 | s->regs[R_PERIOD] = value; | |
122 | ptimer_set_count(s->ptimer, value); | |
123 | break; | |
124 | case R_SNAPSHOT: | |
125 | error_report("lm32_timer: write access to read only register 0x" | |
126 | TARGET_FMT_plx, addr << 2); | |
127 | break; | |
128 | default: | |
dd3d6775 | 129 | error_report("lm32_timer: write access to unknown register 0x" |
ea7924dc MW |
130 | TARGET_FMT_plx, addr << 2); |
131 | break; | |
132 | } | |
133 | timer_update_irq(s); | |
134 | } | |
135 | ||
d09510b2 AK |
136 | static const MemoryRegionOps timer_ops = { |
137 | .read = timer_read, | |
138 | .write = timer_write, | |
139 | .endianness = DEVICE_NATIVE_ENDIAN, | |
140 | .valid = { | |
141 | .min_access_size = 4, | |
142 | .max_access_size = 4, | |
143 | }, | |
ea7924dc MW |
144 | }; |
145 | ||
146 | static void timer_hit(void *opaque) | |
147 | { | |
148 | LM32TimerState *s = opaque; | |
149 | ||
150 | trace_lm32_timer_hit(); | |
151 | ||
152 | s->regs[R_SR] |= SR_TO; | |
153 | ||
154 | if (s->regs[R_CR] & CR_CONT) { | |
155 | ptimer_set_count(s->ptimer, s->regs[R_PERIOD]); | |
156 | ptimer_run(s->ptimer, 1); | |
157 | } | |
158 | timer_update_irq(s); | |
159 | } | |
160 | ||
161 | static void timer_reset(DeviceState *d) | |
162 | { | |
163 | LM32TimerState *s = container_of(d, LM32TimerState, busdev.qdev); | |
164 | int i; | |
165 | ||
166 | for (i = 0; i < R_MAX; i++) { | |
167 | s->regs[i] = 0; | |
168 | } | |
169 | ptimer_stop(s->ptimer); | |
170 | } | |
171 | ||
172 | static int lm32_timer_init(SysBusDevice *dev) | |
173 | { | |
174 | LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev); | |
ea7924dc MW |
175 | |
176 | sysbus_init_irq(dev, &s->irq); | |
177 | ||
178 | s->bh = qemu_bh_new(timer_hit, s); | |
179 | s->ptimer = ptimer_init(s->bh); | |
180 | ptimer_set_freq(s->ptimer, s->freq_hz); | |
181 | ||
d09510b2 | 182 | memory_region_init_io(&s->iomem, &timer_ops, s, "timer", R_MAX * 4); |
750ecd44 | 183 | sysbus_init_mmio(dev, &s->iomem); |
ea7924dc MW |
184 | |
185 | return 0; | |
186 | } | |
187 | ||
188 | static const VMStateDescription vmstate_lm32_timer = { | |
189 | .name = "lm32-timer", | |
190 | .version_id = 1, | |
191 | .minimum_version_id = 1, | |
192 | .minimum_version_id_old = 1, | |
193 | .fields = (VMStateField[]) { | |
194 | VMSTATE_PTIMER(ptimer, LM32TimerState), | |
195 | VMSTATE_UINT32(freq_hz, LM32TimerState), | |
196 | VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX), | |
197 | VMSTATE_END_OF_LIST() | |
198 | } | |
199 | }; | |
200 | ||
201 | static SysBusDeviceInfo lm32_timer_info = { | |
202 | .init = lm32_timer_init, | |
203 | .qdev.name = "lm32-timer", | |
204 | .qdev.size = sizeof(LM32TimerState), | |
205 | .qdev.vmsd = &vmstate_lm32_timer, | |
206 | .qdev.reset = timer_reset, | |
207 | .qdev.props = (Property[]) { | |
208 | DEFINE_PROP_UINT32( | |
209 | "frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY | |
210 | ), | |
211 | DEFINE_PROP_END_OF_LIST(), | |
212 | } | |
213 | }; | |
214 | ||
215 | static void lm32_timer_register(void) | |
216 | { | |
217 | sysbus_register_withprop(&lm32_timer_info); | |
218 | } | |
219 | ||
220 | device_init(lm32_timer_register) |