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Commit | Line | Data |
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a8a506c3 XY |
1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* | |
3 | * QEMU loongson 3a5000 develop board emulation | |
4 | * | |
5 | * Copyright (c) 2021 Loongson Technology Corporation Limited | |
6 | */ | |
7 | #include "qemu/osdep.h" | |
8 | #include "qemu/units.h" | |
9 | #include "qemu/datadir.h" | |
10 | #include "qapi/error.h" | |
11 | #include "hw/boards.h" | |
dc93b8df | 12 | #include "hw/char/serial.h" |
a8a506c3 XY |
13 | #include "sysemu/sysemu.h" |
14 | #include "sysemu/qtest.h" | |
15 | #include "sysemu/runstate.h" | |
16 | #include "sysemu/reset.h" | |
17 | #include "sysemu/rtc.h" | |
18 | #include "hw/loongarch/virt.h" | |
19 | #include "exec/address-spaces.h" | |
dc93b8df XY |
20 | #include "hw/irq.h" |
21 | #include "net/net.h" | |
6a6f26f4 XY |
22 | #include "hw/loader.h" |
23 | #include "elf.h" | |
69d9c74f XY |
24 | #include "hw/intc/loongarch_ipi.h" |
25 | #include "hw/intc/loongarch_extioi.h" | |
26 | #include "hw/intc/loongarch_pch_pic.h" | |
27 | #include "hw/intc/loongarch_pch_msi.h" | |
28 | #include "hw/pci-host/ls7a.h" | |
dc93b8df XY |
29 | #include "hw/pci-host/gpex.h" |
30 | #include "hw/misc/unimp.h" | |
27ad7564 | 31 | #include "hw/loongarch/fw_cfg.h" |
a8a506c3 | 32 | #include "target/loongarch/cpu.h" |
3efa6fa1 | 33 | #include "hw/firmware/smbios.h" |
735143f1 XY |
34 | #include "hw/acpi/aml-build.h" |
35 | #include "qapi/qapi-visit-common.h" | |
36 | #include "hw/acpi/generic_event_device.h" | |
37 | #include "hw/mem/nvdimm.h" | |
fda3f15b XY |
38 | #include "sysemu/device_tree.h" |
39 | #include <libfdt.h> | |
a1f7d78e XY |
40 | #include "hw/core/sysbus-fdt.h" |
41 | #include "hw/platform-bus.h" | |
f8ab9aa2 | 42 | #include "hw/display/ramfb.h" |
c3da26f3 | 43 | #include "hw/mem/pc-dimm.h" |
3dfbb6de | 44 | #include "sysemu/tpm.h" |
288431a1 XY |
45 | #include "sysemu/block-backend.h" |
46 | #include "hw/block/flash.h" | |
47 | ||
48 | static void virt_flash_create(LoongArchMachineState *lams) | |
49 | { | |
50 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); | |
51 | ||
52 | qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); | |
53 | qdev_prop_set_uint8(dev, "width", 4); | |
54 | qdev_prop_set_uint8(dev, "device-width", 2); | |
55 | qdev_prop_set_bit(dev, "big-endian", false); | |
56 | qdev_prop_set_uint16(dev, "id0", 0x89); | |
57 | qdev_prop_set_uint16(dev, "id1", 0x18); | |
58 | qdev_prop_set_uint16(dev, "id2", 0x00); | |
59 | qdev_prop_set_uint16(dev, "id3", 0x00); | |
60 | qdev_prop_set_string(dev, "name", "virt.flash"); | |
61 | object_property_add_child(OBJECT(lams), "virt.flash", OBJECT(dev)); | |
62 | object_property_add_alias(OBJECT(lams), "pflash", | |
63 | OBJECT(dev), "drive"); | |
64 | ||
65 | lams->flash = PFLASH_CFI01(dev); | |
66 | } | |
67 | ||
68 | static void virt_flash_map(LoongArchMachineState *lams, | |
69 | MemoryRegion *sysmem) | |
70 | { | |
71 | PFlashCFI01 *flash = lams->flash; | |
72 | DeviceState *dev = DEVICE(flash); | |
73 | hwaddr base = VIRT_FLASH_BASE; | |
74 | hwaddr size = VIRT_FLASH_SIZE; | |
75 | ||
76 | assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); | |
77 | assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); | |
78 | ||
79 | qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); | |
80 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | |
81 | memory_region_add_subregion(sysmem, base, | |
82 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); | |
83 | ||
84 | } | |
85 | ||
86 | static void fdt_add_flash_node(LoongArchMachineState *lams) | |
87 | { | |
88 | MachineState *ms = MACHINE(lams); | |
89 | char *nodename; | |
90 | ||
91 | hwaddr flash_base = VIRT_FLASH_BASE; | |
92 | hwaddr flash_size = VIRT_FLASH_SIZE; | |
93 | ||
94 | nodename = g_strdup_printf("/flash@%" PRIx64, flash_base); | |
95 | qemu_fdt_add_subnode(ms->fdt, nodename); | |
96 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); | |
97 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", | |
98 | 2, flash_base, 2, flash_size); | |
99 | qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); | |
100 | g_free(nodename); | |
101 | } | |
fda3f15b | 102 | |
ca5bf7ad XY |
103 | static void fdt_add_rtc_node(LoongArchMachineState *lams) |
104 | { | |
105 | char *nodename; | |
106 | hwaddr base = VIRT_RTC_REG_BASE; | |
107 | hwaddr size = VIRT_RTC_LEN; | |
108 | MachineState *ms = MACHINE(lams); | |
109 | ||
110 | nodename = g_strdup_printf("/rtc@%" PRIx64, base); | |
111 | qemu_fdt_add_subnode(ms->fdt, nodename); | |
112 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc"); | |
e8c8203e | 113 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); |
ca5bf7ad XY |
114 | g_free(nodename); |
115 | } | |
116 | ||
117 | static void fdt_add_uart_node(LoongArchMachineState *lams) | |
118 | { | |
119 | char *nodename; | |
120 | hwaddr base = VIRT_UART_BASE; | |
121 | hwaddr size = VIRT_UART_SIZE; | |
122 | MachineState *ms = MACHINE(lams); | |
123 | ||
124 | nodename = g_strdup_printf("/serial@%" PRIx64, base); | |
125 | qemu_fdt_add_subnode(ms->fdt, nodename); | |
126 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); | |
127 | qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); | |
128 | qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); | |
0208ba74 | 129 | qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); |
ca5bf7ad XY |
130 | g_free(nodename); |
131 | } | |
132 | ||
fda3f15b XY |
133 | static void create_fdt(LoongArchMachineState *lams) |
134 | { | |
135 | MachineState *ms = MACHINE(lams); | |
136 | ||
137 | ms->fdt = create_device_tree(&lams->fdt_size); | |
138 | if (!ms->fdt) { | |
139 | error_report("create_device_tree() failed"); | |
140 | exit(1); | |
141 | } | |
142 | ||
143 | /* Header */ | |
144 | qemu_fdt_setprop_string(ms->fdt, "/", "compatible", | |
145 | "linux,dummy-loongson3"); | |
146 | qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); | |
147 | qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); | |
0208ba74 | 148 | qemu_fdt_add_subnode(ms->fdt, "/chosen"); |
fda3f15b XY |
149 | } |
150 | ||
151 | static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) | |
152 | { | |
153 | int num; | |
154 | const MachineState *ms = MACHINE(lams); | |
155 | int smp_cpus = ms->smp.cpus; | |
156 | ||
157 | qemu_fdt_add_subnode(ms->fdt, "/cpus"); | |
158 | qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); | |
159 | qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); | |
160 | ||
161 | /* cpu nodes */ | |
162 | for (num = smp_cpus - 1; num >= 0; num--) { | |
163 | char *nodename = g_strdup_printf("/cpus/cpu@%d", num); | |
164 | LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); | |
165 | ||
166 | qemu_fdt_add_subnode(ms->fdt, nodename); | |
167 | qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); | |
168 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", | |
169 | cpu->dtb_compatible); | |
170 | qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); | |
171 | qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", | |
172 | qemu_fdt_alloc_phandle(ms->fdt)); | |
173 | g_free(nodename); | |
174 | } | |
175 | ||
176 | /*cpu map */ | |
177 | qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); | |
178 | ||
179 | for (num = smp_cpus - 1; num >= 0; num--) { | |
180 | char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); | |
181 | char *map_path; | |
182 | ||
183 | if (ms->smp.threads > 1) { | |
184 | map_path = g_strdup_printf( | |
185 | "/cpus/cpu-map/socket%d/core%d/thread%d", | |
186 | num / (ms->smp.cores * ms->smp.threads), | |
187 | (num / ms->smp.threads) % ms->smp.cores, | |
188 | num % ms->smp.threads); | |
189 | } else { | |
190 | map_path = g_strdup_printf( | |
191 | "/cpus/cpu-map/socket%d/core%d", | |
192 | num / ms->smp.cores, | |
193 | num % ms->smp.cores); | |
194 | } | |
195 | qemu_fdt_add_path(ms->fdt, map_path); | |
196 | qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); | |
197 | ||
198 | g_free(map_path); | |
199 | g_free(cpu_path); | |
200 | } | |
201 | } | |
202 | ||
203 | static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) | |
204 | { | |
205 | char *nodename; | |
206 | hwaddr base = VIRT_FWCFG_BASE; | |
207 | const MachineState *ms = MACHINE(lams); | |
208 | ||
209 | nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); | |
210 | qemu_fdt_add_subnode(ms->fdt, nodename); | |
211 | qemu_fdt_setprop_string(ms->fdt, nodename, | |
212 | "compatible", "qemu,fw-cfg-mmio"); | |
213 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", | |
feae45dc | 214 | 2, base, 2, 0x18); |
fda3f15b XY |
215 | qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); |
216 | g_free(nodename); | |
217 | } | |
218 | ||
219 | static void fdt_add_pcie_node(const LoongArchMachineState *lams) | |
220 | { | |
221 | char *nodename; | |
74725231 XY |
222 | hwaddr base_mmio = VIRT_PCI_MEM_BASE; |
223 | hwaddr size_mmio = VIRT_PCI_MEM_SIZE; | |
224 | hwaddr base_pio = VIRT_PCI_IO_BASE; | |
225 | hwaddr size_pio = VIRT_PCI_IO_SIZE; | |
226 | hwaddr base_pcie = VIRT_PCI_CFG_BASE; | |
227 | hwaddr size_pcie = VIRT_PCI_CFG_SIZE; | |
fda3f15b XY |
228 | hwaddr base = base_pcie; |
229 | ||
230 | const MachineState *ms = MACHINE(lams); | |
231 | ||
232 | nodename = g_strdup_printf("/pcie@%" PRIx64, base); | |
233 | qemu_fdt_add_subnode(ms->fdt, nodename); | |
234 | qemu_fdt_setprop_string(ms->fdt, nodename, | |
235 | "compatible", "pci-host-ecam-generic"); | |
236 | qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); | |
237 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); | |
238 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); | |
239 | qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); | |
240 | qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, | |
74725231 | 241 | PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); |
fda3f15b XY |
242 | qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); |
243 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", | |
244 | 2, base_pcie, 2, size_pcie); | |
245 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", | |
74725231 | 246 | 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, |
fda3f15b XY |
247 | 2, base_pio, 2, size_pio, |
248 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
249 | 2, base_mmio, 2, size_mmio); | |
250 | g_free(nodename); | |
fda3f15b XY |
251 | } |
252 | ||
ee413a52 XY |
253 | static void fdt_add_irqchip_node(LoongArchMachineState *lams) |
254 | { | |
255 | MachineState *ms = MACHINE(lams); | |
256 | char *nodename; | |
257 | uint32_t irqchip_phandle; | |
258 | ||
259 | irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); | |
260 | qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); | |
261 | ||
262 | nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); | |
263 | qemu_fdt_add_subnode(ms->fdt, nodename); | |
264 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); | |
265 | qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); | |
266 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); | |
267 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); | |
268 | qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); | |
269 | ||
270 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", | |
271 | "loongarch,ls7a"); | |
272 | ||
273 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", | |
274 | 2, VIRT_IOAPIC_REG_BASE, | |
275 | 2, PCH_PIC_ROUTE_ENTRY_OFFSET); | |
276 | ||
277 | qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); | |
278 | g_free(nodename); | |
279 | } | |
a8a506c3 | 280 | |
9e6602d6 XY |
281 | #define PM_BASE 0x10080000 |
282 | #define PM_SIZE 0x100 | |
283 | #define PM_CTRL 0x10 | |
284 | ||
3efa6fa1 XY |
285 | static void virt_build_smbios(LoongArchMachineState *lams) |
286 | { | |
287 | MachineState *ms = MACHINE(lams); | |
288 | MachineClass *mc = MACHINE_GET_CLASS(lams); | |
289 | uint8_t *smbios_tables, *smbios_anchor; | |
290 | size_t smbios_tables_len, smbios_anchor_len; | |
291 | const char *product = "QEMU Virtual Machine"; | |
292 | ||
293 | if (!lams->fw_cfg) { | |
294 | return; | |
295 | } | |
296 | ||
297 | smbios_set_defaults("QEMU", product, mc->name, false, | |
298 | true, SMBIOS_ENTRY_POINT_TYPE_64); | |
299 | ||
300 | smbios_get_tables(ms, NULL, 0, &smbios_tables, &smbios_tables_len, | |
301 | &smbios_anchor, &smbios_anchor_len, &error_fatal); | |
302 | ||
303 | if (smbios_anchor) { | |
304 | fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", | |
305 | smbios_tables, smbios_tables_len); | |
306 | fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", | |
307 | smbios_anchor, smbios_anchor_len); | |
308 | } | |
309 | } | |
310 | ||
311 | static void virt_machine_done(Notifier *notifier, void *data) | |
312 | { | |
313 | LoongArchMachineState *lams = container_of(notifier, | |
314 | LoongArchMachineState, machine_done); | |
315 | virt_build_smbios(lams); | |
735143f1 | 316 | loongarch_acpi_setup(lams); |
3efa6fa1 XY |
317 | } |
318 | ||
27ad7564 XY |
319 | struct memmap_entry { |
320 | uint64_t address; | |
321 | uint64_t length; | |
322 | uint32_t type; | |
323 | uint32_t reserved; | |
324 | }; | |
325 | ||
326 | static struct memmap_entry *memmap_table; | |
327 | static unsigned memmap_entries; | |
328 | ||
329 | static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) | |
330 | { | |
331 | /* Ensure there are no duplicate entries. */ | |
332 | for (unsigned i = 0; i < memmap_entries; i++) { | |
333 | assert(memmap_table[i].address != address); | |
334 | } | |
335 | ||
336 | memmap_table = g_renew(struct memmap_entry, memmap_table, | |
337 | memmap_entries + 1); | |
338 | memmap_table[memmap_entries].address = cpu_to_le64(address); | |
339 | memmap_table[memmap_entries].length = cpu_to_le64(length); | |
340 | memmap_table[memmap_entries].type = cpu_to_le32(type); | |
341 | memmap_table[memmap_entries].reserved = 0; | |
342 | memmap_entries++; | |
343 | } | |
344 | ||
9e6602d6 XY |
345 | /* |
346 | * This is a placeholder for missing ACPI, | |
347 | * and will eventually be replaced. | |
348 | */ | |
349 | static uint64_t loongarch_virt_pm_read(void *opaque, hwaddr addr, unsigned size) | |
350 | { | |
351 | return 0; | |
352 | } | |
353 | ||
354 | static void loongarch_virt_pm_write(void *opaque, hwaddr addr, | |
355 | uint64_t val, unsigned size) | |
356 | { | |
357 | if (addr != PM_CTRL) { | |
358 | return; | |
359 | } | |
360 | ||
361 | switch (val) { | |
362 | case 0x00: | |
363 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
364 | return; | |
365 | case 0xff: | |
366 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | |
367 | return; | |
368 | default: | |
369 | return; | |
370 | } | |
371 | } | |
372 | ||
373 | static const MemoryRegionOps loongarch_virt_pm_ops = { | |
374 | .read = loongarch_virt_pm_read, | |
375 | .write = loongarch_virt_pm_write, | |
376 | .endianness = DEVICE_NATIVE_ENDIAN, | |
377 | .valid = { | |
378 | .min_access_size = 1, | |
379 | .max_access_size = 1 | |
380 | } | |
381 | }; | |
382 | ||
6a6f26f4 XY |
383 | static struct _loaderparams { |
384 | uint64_t ram_size; | |
385 | const char *kernel_filename; | |
fb1cd3a2 XY |
386 | const char *kernel_cmdline; |
387 | const char *initrd_filename; | |
6a6f26f4 XY |
388 | } loaderparams; |
389 | ||
390 | static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) | |
391 | { | |
392 | return addr & 0x1fffffffll; | |
393 | } | |
394 | ||
395 | static int64_t load_kernel_info(void) | |
396 | { | |
397 | uint64_t kernel_entry, kernel_low, kernel_high; | |
398 | ssize_t kernel_size; | |
399 | ||
400 | kernel_size = load_elf(loaderparams.kernel_filename, NULL, | |
401 | cpu_loongarch_virt_to_phys, NULL, | |
402 | &kernel_entry, &kernel_low, | |
403 | &kernel_high, NULL, 0, | |
404 | EM_LOONGARCH, 1, 0); | |
405 | ||
406 | if (kernel_size < 0) { | |
407 | error_report("could not load kernel '%s': %s", | |
408 | loaderparams.kernel_filename, | |
409 | load_elf_strerror(kernel_size)); | |
410 | exit(1); | |
411 | } | |
412 | return kernel_entry; | |
413 | } | |
414 | ||
735143f1 XY |
415 | static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) |
416 | { | |
417 | DeviceState *dev; | |
418 | MachineState *ms = MACHINE(lams); | |
419 | uint32_t event = ACPI_GED_PWR_DOWN_EVT; | |
420 | ||
421 | if (ms->ram_slots) { | |
422 | event |= ACPI_GED_MEM_HOTPLUG_EVT; | |
423 | } | |
424 | dev = qdev_new(TYPE_ACPI_GED); | |
425 | qdev_prop_set_uint32(dev, "ged-event", event); | |
426 | ||
427 | /* ged event */ | |
428 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); | |
429 | /* memory hotplug */ | |
430 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); | |
431 | /* ged regs used for reset and power down */ | |
432 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); | |
433 | ||
434 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, | |
74725231 | 435 | qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - PCH_PIC_IRQ_OFFSET)); |
735143f1 XY |
436 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
437 | return dev; | |
438 | } | |
439 | ||
a1f7d78e XY |
440 | static DeviceState *create_platform_bus(DeviceState *pch_pic) |
441 | { | |
442 | DeviceState *dev; | |
443 | SysBusDevice *sysbus; | |
444 | int i, irq; | |
445 | MemoryRegion *sysmem = get_system_memory(); | |
446 | ||
447 | dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); | |
448 | dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); | |
449 | qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); | |
450 | qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); | |
451 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | |
452 | ||
453 | sysbus = SYS_BUS_DEVICE(dev); | |
454 | for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { | |
455 | irq = VIRT_PLATFORM_BUS_IRQ - PCH_PIC_IRQ_OFFSET + i; | |
456 | sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); | |
457 | } | |
458 | ||
459 | memory_region_add_subregion(sysmem, | |
460 | VIRT_PLATFORM_BUS_BASEADDRESS, | |
461 | sysbus_mmio_get_region(sysbus, 0)); | |
462 | return dev; | |
463 | } | |
464 | ||
735143f1 | 465 | static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) |
dc93b8df XY |
466 | { |
467 | DeviceState *gpex_dev; | |
468 | SysBusDevice *d; | |
469 | PCIBus *pci_bus; | |
470 | MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; | |
9e6602d6 | 471 | MemoryRegion *mmio_alias, *mmio_reg, *pm_mem; |
dc93b8df XY |
472 | int i; |
473 | ||
474 | gpex_dev = qdev_new(TYPE_GPEX_HOST); | |
475 | d = SYS_BUS_DEVICE(gpex_dev); | |
476 | sysbus_realize_and_unref(d, &error_fatal); | |
477 | pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; | |
1895b967 | 478 | lams->pci_bus = pci_bus; |
dc93b8df XY |
479 | |
480 | /* Map only part size_ecam bytes of ECAM space */ | |
481 | ecam_alias = g_new0(MemoryRegion, 1); | |
482 | ecam_reg = sysbus_mmio_get_region(d, 0); | |
483 | memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", | |
74725231 XY |
484 | ecam_reg, 0, VIRT_PCI_CFG_SIZE); |
485 | memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, | |
dc93b8df XY |
486 | ecam_alias); |
487 | ||
488 | /* Map PCI mem space */ | |
489 | mmio_alias = g_new0(MemoryRegion, 1); | |
490 | mmio_reg = sysbus_mmio_get_region(d, 1); | |
491 | memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", | |
74725231 XY |
492 | mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); |
493 | memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, | |
dc93b8df XY |
494 | mmio_alias); |
495 | ||
496 | /* Map PCI IO port space. */ | |
497 | pio_alias = g_new0(MemoryRegion, 1); | |
498 | pio_reg = sysbus_mmio_get_region(d, 2); | |
499 | memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, | |
74725231 XY |
500 | VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); |
501 | memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, | |
dc93b8df XY |
502 | pio_alias); |
503 | ||
504 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | |
505 | sysbus_connect_irq(d, i, | |
506 | qdev_get_gpio_in(pch_pic, 16 + i)); | |
507 | gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); | |
508 | } | |
509 | ||
74725231 | 510 | serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, |
dc93b8df | 511 | qdev_get_gpio_in(pch_pic, |
74725231 | 512 | VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET), |
dc93b8df | 513 | 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); |
ca5bf7ad | 514 | fdt_add_uart_node(lams); |
dc93b8df XY |
515 | |
516 | /* Network init */ | |
517 | for (i = 0; i < nb_nics; i++) { | |
518 | NICInfo *nd = &nd_table[i]; | |
519 | ||
520 | if (!nd->model) { | |
521 | nd->model = g_strdup("virtio"); | |
522 | } | |
523 | ||
524 | pci_nic_init_nofail(nd, pci_bus, nd->model, NULL); | |
525 | } | |
526 | ||
dc93b8df XY |
527 | /* |
528 | * There are some invalid guest memory access. | |
529 | * Create some unimplemented devices to emulate this. | |
530 | */ | |
531 | create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); | |
74725231 | 532 | sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, |
c117f68a | 533 | qdev_get_gpio_in(pch_pic, |
74725231 | 534 | VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET)); |
ca5bf7ad | 535 | fdt_add_rtc_node(lams); |
9e6602d6 XY |
536 | |
537 | pm_mem = g_new(MemoryRegion, 1); | |
538 | memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops, | |
539 | NULL, "loongarch_virt_pm", PM_SIZE); | |
540 | memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem); | |
735143f1 XY |
541 | /* acpi ged */ |
542 | lams->acpi_ged = create_acpi_ged(pch_pic, lams); | |
a1f7d78e XY |
543 | /* platform bus */ |
544 | lams->platform_bus_dev = create_platform_bus(pch_pic); | |
dc93b8df XY |
545 | } |
546 | ||
69d9c74f XY |
547 | static void loongarch_irq_init(LoongArchMachineState *lams) |
548 | { | |
549 | MachineState *ms = MACHINE(lams); | |
550 | DeviceState *pch_pic, *pch_msi, *cpudev; | |
551 | DeviceState *ipi, *extioi; | |
552 | SysBusDevice *d; | |
553 | LoongArchCPU *lacpu; | |
554 | CPULoongArchState *env; | |
555 | CPUState *cpu_state; | |
556 | int cpu, pin, i; | |
557 | ||
558 | ipi = qdev_new(TYPE_LOONGARCH_IPI); | |
559 | sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); | |
560 | ||
561 | extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); | |
562 | sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); | |
563 | ||
564 | /* | |
565 | * The connection of interrupts: | |
566 | * +-----+ +---------+ +-------+ | |
567 | * | IPI |--> | CPUINTC | <-- | Timer | | |
568 | * +-----+ +---------+ +-------+ | |
569 | * ^ | |
570 | * | | |
571 | * +---------+ | |
572 | * | EIOINTC | | |
573 | * +---------+ | |
574 | * ^ ^ | |
575 | * | | | |
576 | * +---------+ +---------+ | |
577 | * | PCH-PIC | | PCH-MSI | | |
578 | * +---------+ +---------+ | |
579 | * ^ ^ ^ | |
580 | * | | | | |
581 | * +--------+ +---------+ +---------+ | |
582 | * | UARTs | | Devices | | Devices | | |
583 | * +--------+ +---------+ +---------+ | |
584 | */ | |
585 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
586 | cpu_state = qemu_get_cpu(cpu); | |
587 | cpudev = DEVICE(cpu_state); | |
588 | lacpu = LOONGARCH_CPU(cpu_state); | |
589 | env = &(lacpu->env); | |
590 | ||
591 | /* connect ipi irq to cpu irq */ | |
592 | qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); | |
593 | /* IPI iocsr memory region */ | |
594 | memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX, | |
595 | sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), | |
ddf93261 XY |
596 | cpu * 2)); |
597 | memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR, | |
598 | sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), | |
599 | cpu * 2 + 1)); | |
69d9c74f XY |
600 | /* extioi iocsr memory region */ |
601 | memory_region_add_subregion(&env->system_iocsr, APIC_BASE, | |
602 | sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), | |
603 | cpu)); | |
604 | } | |
605 | ||
606 | /* | |
607 | * connect ext irq to the cpu irq | |
608 | * cpu_pin[9:2] <= intc_pin[7:0] | |
609 | */ | |
610 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
611 | cpudev = DEVICE(qemu_get_cpu(cpu)); | |
612 | for (pin = 0; pin < LS3A_INTC_IP; pin++) { | |
613 | qdev_connect_gpio_out(extioi, (cpu * 8 + pin), | |
614 | qdev_get_gpio_in(cpudev, pin + 2)); | |
615 | } | |
616 | } | |
617 | ||
618 | pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); | |
619 | d = SYS_BUS_DEVICE(pch_pic); | |
620 | sysbus_realize_and_unref(d, &error_fatal); | |
74725231 | 621 | memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, |
69d9c74f XY |
622 | sysbus_mmio_get_region(d, 0)); |
623 | memory_region_add_subregion(get_system_memory(), | |
74725231 | 624 | VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, |
69d9c74f XY |
625 | sysbus_mmio_get_region(d, 1)); |
626 | memory_region_add_subregion(get_system_memory(), | |
74725231 | 627 | VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, |
69d9c74f XY |
628 | sysbus_mmio_get_region(d, 2)); |
629 | ||
630 | /* Connect 64 pch_pic irqs to extioi */ | |
631 | for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) { | |
632 | qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); | |
633 | } | |
634 | ||
635 | pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); | |
490c03ab | 636 | qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START); |
69d9c74f XY |
637 | d = SYS_BUS_DEVICE(pch_msi); |
638 | sysbus_realize_and_unref(d, &error_fatal); | |
74725231 | 639 | sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); |
69d9c74f XY |
640 | for (i = 0; i < PCH_MSI_IRQ_NUM; i++) { |
641 | /* Connect 192 pch_msi irqs to extioi */ | |
642 | qdev_connect_gpio_out(DEVICE(d), i, | |
643 | qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START)); | |
644 | } | |
dc93b8df | 645 | |
735143f1 | 646 | loongarch_devices_init(pch_pic, lams); |
69d9c74f XY |
647 | } |
648 | ||
98afb0d4 XY |
649 | static void loongarch_firmware_init(LoongArchMachineState *lams) |
650 | { | |
651 | char *filename = MACHINE(lams)->firmware; | |
652 | char *bios_name = NULL; | |
653 | int bios_size; | |
654 | ||
655 | lams->bios_loaded = false; | |
288431a1 XY |
656 | |
657 | virt_flash_map(lams, get_system_memory()); | |
658 | ||
98afb0d4 XY |
659 | if (filename) { |
660 | bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); | |
661 | if (!bios_name) { | |
662 | error_report("Could not find ROM image '%s'", filename); | |
663 | exit(1); | |
664 | } | |
665 | ||
666 | bios_size = load_image_targphys(bios_name, VIRT_BIOS_BASE, VIRT_BIOS_SIZE); | |
667 | if (bios_size < 0) { | |
668 | error_report("Could not load ROM image '%s'", bios_name); | |
669 | exit(1); | |
670 | } | |
671 | ||
672 | g_free(bios_name); | |
673 | ||
674 | memory_region_init_ram(&lams->bios, NULL, "loongarch.bios", | |
675 | VIRT_BIOS_SIZE, &error_fatal); | |
676 | memory_region_set_readonly(&lams->bios, true); | |
677 | memory_region_add_subregion(get_system_memory(), VIRT_BIOS_BASE, &lams->bios); | |
678 | lams->bios_loaded = true; | |
679 | } | |
680 | ||
681 | } | |
682 | ||
6a6f26f4 XY |
683 | static void reset_load_elf(void *opaque) |
684 | { | |
685 | LoongArchCPU *cpu = opaque; | |
686 | CPULoongArchState *env = &cpu->env; | |
687 | ||
688 | cpu_reset(CPU(cpu)); | |
689 | if (env->load_elf) { | |
690 | cpu_set_pc(CPU(cpu), env->elf_address); | |
691 | } | |
692 | } | |
693 | ||
fb1cd3a2 XY |
694 | static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg) |
695 | { | |
696 | /* | |
697 | * Expose the kernel, the command line, and the initrd in fw_cfg. | |
698 | * We don't process them here at all, it's all left to the | |
699 | * firmware. | |
700 | */ | |
701 | load_image_to_fw_cfg(fw_cfg, | |
702 | FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, | |
703 | loaderparams.kernel_filename, | |
704 | false); | |
705 | ||
706 | if (loaderparams.initrd_filename) { | |
707 | load_image_to_fw_cfg(fw_cfg, | |
708 | FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, | |
709 | loaderparams.initrd_filename, false); | |
710 | } | |
711 | ||
712 | if (loaderparams.kernel_cmdline) { | |
713 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | |
714 | strlen(loaderparams.kernel_cmdline) + 1); | |
715 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, | |
716 | loaderparams.kernel_cmdline); | |
717 | } | |
718 | } | |
719 | ||
720 | static void loongarch_firmware_boot(LoongArchMachineState *lams) | |
721 | { | |
722 | fw_cfg_add_kernel_info(lams->fw_cfg); | |
723 | } | |
724 | ||
725 | static void loongarch_direct_kernel_boot(LoongArchMachineState *lams) | |
726 | { | |
727 | MachineState *machine = MACHINE(lams); | |
728 | int64_t kernel_addr = 0; | |
729 | LoongArchCPU *lacpu; | |
730 | int i; | |
731 | ||
732 | kernel_addr = load_kernel_info(); | |
733 | if (!machine->firmware) { | |
734 | for (i = 0; i < machine->smp.cpus; i++) { | |
735 | lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); | |
736 | lacpu->env.load_elf = true; | |
737 | lacpu->env.elf_address = kernel_addr; | |
738 | } | |
739 | } | |
740 | } | |
741 | ||
a8a506c3 XY |
742 | static void loongarch_init(MachineState *machine) |
743 | { | |
fb1cd3a2 | 744 | LoongArchCPU *lacpu; |
a8a506c3 XY |
745 | const char *cpu_model = machine->cpu_type; |
746 | ram_addr_t offset = 0; | |
747 | ram_addr_t ram_size = machine->ram_size; | |
748 | uint64_t highram_size = 0; | |
749 | MemoryRegion *address_space_mem = get_system_memory(); | |
750 | LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); | |
751 | int i; | |
02183693 | 752 | hwaddr fdt_base; |
a8a506c3 XY |
753 | |
754 | if (!cpu_model) { | |
755 | cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); | |
756 | } | |
757 | ||
758 | if (!strstr(cpu_model, "la464")) { | |
759 | error_report("LoongArch/TCG needs cpu type la464"); | |
760 | exit(1); | |
761 | } | |
762 | ||
763 | if (ram_size < 1 * GiB) { | |
764 | error_report("ram_size must be greater than 1G."); | |
765 | exit(1); | |
766 | } | |
fda3f15b | 767 | create_fdt(lams); |
a8a506c3 XY |
768 | /* Init CPUs */ |
769 | for (i = 0; i < machine->smp.cpus; i++) { | |
770 | cpu_create(machine->cpu_type); | |
771 | } | |
fda3f15b | 772 | fdt_add_cpu_nodes(lams); |
a8a506c3 XY |
773 | /* Add memory region */ |
774 | memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram", | |
775 | machine->ram, 0, 256 * MiB); | |
776 | memory_region_add_subregion(address_space_mem, offset, &lams->lowmem); | |
777 | offset += 256 * MiB; | |
27ad7564 | 778 | memmap_add_entry(0, 256 * MiB, 1); |
a8a506c3 XY |
779 | highram_size = ram_size - 256 * MiB; |
780 | memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem", | |
781 | machine->ram, offset, highram_size); | |
782 | memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem); | |
27ad7564 | 783 | memmap_add_entry(0x90000000, highram_size, 1); |
c3da26f3 XY |
784 | |
785 | /* initialize device memory address space */ | |
786 | if (machine->ram_size < machine->maxram_size) { | |
787 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); | |
788 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; | |
789 | ||
790 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { | |
791 | error_report("unsupported amount of memory slots: %"PRIu64, | |
792 | machine->ram_slots); | |
793 | exit(EXIT_FAILURE); | |
794 | } | |
795 | ||
796 | if (QEMU_ALIGN_UP(machine->maxram_size, | |
797 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
798 | error_report("maximum memory size must by aligned to multiple of " | |
799 | "%d bytes", TARGET_PAGE_SIZE); | |
800 | exit(EXIT_FAILURE); | |
801 | } | |
802 | /* device memory base is the top of high memory address. */ | |
803 | machine->device_memory->base = 0x90000000 + highram_size; | |
804 | machine->device_memory->base = | |
805 | ROUND_UP(machine->device_memory->base, 1 * GiB); | |
806 | ||
807 | memory_region_init(&machine->device_memory->mr, OBJECT(lams), | |
808 | "device-memory", device_mem_size); | |
809 | memory_region_add_subregion(address_space_mem, machine->device_memory->base, | |
810 | &machine->device_memory->mr); | |
811 | } | |
812 | ||
a8a506c3 XY |
813 | /* Add isa io region */ |
814 | memory_region_init_alias(&lams->isa_io, NULL, "isa-io", | |
74725231 XY |
815 | get_system_io(), 0, VIRT_ISA_IO_SIZE); |
816 | memory_region_add_subregion(address_space_mem, VIRT_ISA_IO_BASE, | |
a8a506c3 | 817 | &lams->isa_io); |
98afb0d4 XY |
818 | /* load the BIOS image. */ |
819 | loongarch_firmware_init(lams); | |
820 | ||
27ad7564 XY |
821 | /* fw_cfg init */ |
822 | lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); | |
823 | rom_set_fw(lams->fw_cfg); | |
27ad7564 XY |
824 | if (lams->fw_cfg != NULL) { |
825 | fw_cfg_add_file(lams->fw_cfg, "etc/memmap", | |
826 | memmap_table, | |
827 | sizeof(struct memmap_entry) * (memmap_entries)); | |
828 | } | |
fda3f15b | 829 | fdt_add_fw_cfg_node(lams); |
fb1cd3a2 XY |
830 | loaderparams.ram_size = ram_size; |
831 | loaderparams.kernel_filename = machine->kernel_filename; | |
832 | loaderparams.kernel_cmdline = machine->kernel_cmdline; | |
833 | loaderparams.initrd_filename = machine->initrd_filename; | |
834 | /* load the kernel. */ | |
835 | if (loaderparams.kernel_filename) { | |
836 | if (lams->bios_loaded) { | |
837 | loongarch_firmware_boot(lams); | |
838 | } else { | |
839 | loongarch_direct_kernel_boot(lams); | |
6a6f26f4 XY |
840 | } |
841 | } | |
288431a1 | 842 | fdt_add_flash_node(lams); |
fb1cd3a2 XY |
843 | /* register reset function */ |
844 | for (i = 0; i < machine->smp.cpus; i++) { | |
845 | lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); | |
846 | qemu_register_reset(reset_load_elf, lacpu); | |
847 | } | |
69d9c74f XY |
848 | /* Initialize the IO interrupt subsystem */ |
849 | loongarch_irq_init(lams); | |
ee413a52 | 850 | fdt_add_irqchip_node(lams); |
a1f7d78e XY |
851 | platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", |
852 | VIRT_PLATFORM_BUS_BASEADDRESS, | |
853 | VIRT_PLATFORM_BUS_SIZE, | |
854 | VIRT_PLATFORM_BUS_IRQ); | |
3efa6fa1 XY |
855 | lams->machine_done.notify = virt_machine_done; |
856 | qemu_add_machine_init_done_notifier(&lams->machine_done); | |
fda3f15b | 857 | fdt_add_pcie_node(lams); |
02183693 | 858 | /* |
46b21de2 SG |
859 | * Since lowmem region starts from 0 and Linux kernel legacy start address |
860 | * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer | |
861 | * access. FDT size limit with 1 MiB. | |
02183693 XY |
862 | * Put the FDT into the memory map as a ROM image: this will ensure |
863 | * the FDT is copied again upon reset, even if addr points into RAM. | |
864 | */ | |
46b21de2 | 865 | fdt_base = 1 * MiB; |
02183693 XY |
866 | qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); |
867 | rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base); | |
a8a506c3 XY |
868 | } |
869 | ||
735143f1 XY |
870 | bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) |
871 | { | |
872 | if (lams->acpi == ON_OFF_AUTO_OFF) { | |
873 | return false; | |
874 | } | |
875 | return true; | |
876 | } | |
877 | ||
878 | static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, | |
879 | void *opaque, Error **errp) | |
880 | { | |
881 | LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); | |
882 | OnOffAuto acpi = lams->acpi; | |
883 | ||
884 | visit_type_OnOffAuto(v, name, &acpi, errp); | |
885 | } | |
886 | ||
887 | static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, | |
888 | void *opaque, Error **errp) | |
889 | { | |
890 | LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); | |
891 | ||
892 | visit_type_OnOffAuto(v, name, &lams->acpi, errp); | |
893 | } | |
894 | ||
895 | static void loongarch_machine_initfn(Object *obj) | |
896 | { | |
897 | LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); | |
898 | ||
899 | lams->acpi = ON_OFF_AUTO_AUTO; | |
900 | lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); | |
901 | lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); | |
288431a1 | 902 | virt_flash_create(lams); |
735143f1 XY |
903 | } |
904 | ||
c3da26f3 XY |
905 | static bool memhp_type_supported(DeviceState *dev) |
906 | { | |
907 | /* we only support pc dimm now */ | |
908 | return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && | |
909 | !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); | |
910 | } | |
911 | ||
912 | static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
913 | Error **errp) | |
914 | { | |
915 | pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); | |
916 | } | |
917 | ||
918 | static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, | |
919 | DeviceState *dev, Error **errp) | |
920 | { | |
921 | if (memhp_type_supported(dev)) { | |
922 | virt_mem_pre_plug(hotplug_dev, dev, errp); | |
923 | } | |
924 | } | |
925 | ||
926 | static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, | |
927 | DeviceState *dev, Error **errp) | |
928 | { | |
929 | LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); | |
930 | ||
931 | /* the acpi ged is always exist */ | |
932 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, | |
933 | errp); | |
934 | } | |
935 | ||
936 | static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, | |
937 | DeviceState *dev, Error **errp) | |
938 | { | |
939 | if (memhp_type_supported(dev)) { | |
940 | virt_mem_unplug_request(hotplug_dev, dev, errp); | |
941 | } | |
942 | } | |
943 | ||
944 | static void virt_mem_unplug(HotplugHandler *hotplug_dev, | |
945 | DeviceState *dev, Error **errp) | |
946 | { | |
947 | LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); | |
948 | ||
949 | hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); | |
950 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); | |
951 | qdev_unrealize(dev); | |
952 | } | |
953 | ||
954 | static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, | |
955 | DeviceState *dev, Error **errp) | |
956 | { | |
957 | if (memhp_type_supported(dev)) { | |
958 | virt_mem_unplug(hotplug_dev, dev, errp); | |
959 | } | |
960 | } | |
961 | ||
962 | static void virt_mem_plug(HotplugHandler *hotplug_dev, | |
963 | DeviceState *dev, Error **errp) | |
964 | { | |
965 | LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); | |
966 | ||
967 | pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); | |
968 | hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), | |
969 | dev, &error_abort); | |
970 | } | |
971 | ||
e27e5357 XY |
972 | static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
973 | DeviceState *dev, Error **errp) | |
974 | { | |
975 | LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); | |
976 | MachineClass *mc = MACHINE_GET_CLASS(lams); | |
977 | ||
978 | if (device_is_dynamic_sysbus(mc, dev)) { | |
979 | if (lams->platform_bus_dev) { | |
980 | platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), | |
981 | SYS_BUS_DEVICE(dev)); | |
982 | } | |
c3da26f3 XY |
983 | } else if (memhp_type_supported(dev)) { |
984 | virt_mem_plug(hotplug_dev, dev, errp); | |
e27e5357 XY |
985 | } |
986 | } | |
987 | ||
988 | static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, | |
989 | DeviceState *dev) | |
990 | { | |
991 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
992 | ||
c3da26f3 XY |
993 | if (device_is_dynamic_sysbus(mc, dev) || |
994 | memhp_type_supported(dev)) { | |
e27e5357 XY |
995 | return HOTPLUG_HANDLER(machine); |
996 | } | |
997 | return NULL; | |
998 | } | |
999 | ||
a8a506c3 XY |
1000 | static void loongarch_class_init(ObjectClass *oc, void *data) |
1001 | { | |
1002 | MachineClass *mc = MACHINE_CLASS(oc); | |
e27e5357 | 1003 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
a8a506c3 XY |
1004 | |
1005 | mc->desc = "Loongson-3A5000 LS7A1000 machine"; | |
1006 | mc->init = loongarch_init; | |
1007 | mc->default_ram_size = 1 * GiB; | |
1008 | mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); | |
1009 | mc->default_ram_id = "loongarch.ram"; | |
1010 | mc->max_cpus = LOONGARCH_MAX_VCPUS; | |
1011 | mc->is_default = 1; | |
1012 | mc->default_kernel_irqchip_split = false; | |
1013 | mc->block_default_type = IF_VIRTIO; | |
1014 | mc->default_boot_order = "c"; | |
1015 | mc->no_cdrom = 1; | |
e27e5357 XY |
1016 | mc->get_hotplug_handler = virt_machine_get_hotplug_handler; |
1017 | hc->plug = loongarch_machine_device_plug_cb; | |
c3da26f3 XY |
1018 | hc->pre_plug = virt_machine_device_pre_plug; |
1019 | hc->unplug_request = virt_machine_device_unplug_request; | |
1020 | hc->unplug = virt_machine_device_unplug; | |
735143f1 XY |
1021 | |
1022 | object_class_property_add(oc, "acpi", "OnOffAuto", | |
1023 | loongarch_get_acpi, loongarch_set_acpi, | |
1024 | NULL, NULL); | |
1025 | object_class_property_set_description(oc, "acpi", | |
1026 | "Enable ACPI"); | |
f8ab9aa2 | 1027 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); |
3dfbb6de XY |
1028 | #ifdef CONFIG_TPM |
1029 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); | |
1030 | #endif | |
a8a506c3 XY |
1031 | } |
1032 | ||
1033 | static const TypeInfo loongarch_machine_types[] = { | |
1034 | { | |
1035 | .name = TYPE_LOONGARCH_MACHINE, | |
1036 | .parent = TYPE_MACHINE, | |
1037 | .instance_size = sizeof(LoongArchMachineState), | |
1038 | .class_init = loongarch_class_init, | |
735143f1 | 1039 | .instance_init = loongarch_machine_initfn, |
e27e5357 XY |
1040 | .interfaces = (InterfaceInfo[]) { |
1041 | { TYPE_HOTPLUG_HANDLER }, | |
1042 | { } | |
1043 | }, | |
a8a506c3 XY |
1044 | } |
1045 | }; | |
1046 | ||
1047 | DEFINE_TYPES(loongarch_machine_types) |