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a8a506c3 XY |
1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* | |
3 | * QEMU loongson 3a5000 develop board emulation | |
4 | * | |
5 | * Copyright (c) 2021 Loongson Technology Corporation Limited | |
6 | */ | |
7 | #include "qemu/osdep.h" | |
8 | #include "qemu/units.h" | |
9 | #include "qemu/datadir.h" | |
10 | #include "qapi/error.h" | |
11 | #include "hw/boards.h" | |
dc93b8df | 12 | #include "hw/char/serial.h" |
a8a506c3 XY |
13 | #include "sysemu/sysemu.h" |
14 | #include "sysemu/qtest.h" | |
15 | #include "sysemu/runstate.h" | |
16 | #include "sysemu/reset.h" | |
17 | #include "sysemu/rtc.h" | |
18 | #include "hw/loongarch/virt.h" | |
19 | #include "exec/address-spaces.h" | |
dc93b8df XY |
20 | #include "hw/irq.h" |
21 | #include "net/net.h" | |
6a6f26f4 XY |
22 | #include "hw/loader.h" |
23 | #include "elf.h" | |
69d9c74f XY |
24 | #include "hw/intc/loongarch_ipi.h" |
25 | #include "hw/intc/loongarch_extioi.h" | |
26 | #include "hw/intc/loongarch_pch_pic.h" | |
27 | #include "hw/intc/loongarch_pch_msi.h" | |
28 | #include "hw/pci-host/ls7a.h" | |
dc93b8df XY |
29 | #include "hw/pci-host/gpex.h" |
30 | #include "hw/misc/unimp.h" | |
27ad7564 | 31 | #include "hw/loongarch/fw_cfg.h" |
a8a506c3 | 32 | #include "target/loongarch/cpu.h" |
3efa6fa1 | 33 | #include "hw/firmware/smbios.h" |
735143f1 XY |
34 | #include "hw/acpi/aml-build.h" |
35 | #include "qapi/qapi-visit-common.h" | |
36 | #include "hw/acpi/generic_event_device.h" | |
37 | #include "hw/mem/nvdimm.h" | |
fda3f15b XY |
38 | #include "sysemu/device_tree.h" |
39 | #include <libfdt.h> | |
40 | ||
41 | static void create_fdt(LoongArchMachineState *lams) | |
42 | { | |
43 | MachineState *ms = MACHINE(lams); | |
44 | ||
45 | ms->fdt = create_device_tree(&lams->fdt_size); | |
46 | if (!ms->fdt) { | |
47 | error_report("create_device_tree() failed"); | |
48 | exit(1); | |
49 | } | |
50 | ||
51 | /* Header */ | |
52 | qemu_fdt_setprop_string(ms->fdt, "/", "compatible", | |
53 | "linux,dummy-loongson3"); | |
54 | qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); | |
55 | qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); | |
56 | } | |
57 | ||
58 | static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) | |
59 | { | |
60 | int num; | |
61 | const MachineState *ms = MACHINE(lams); | |
62 | int smp_cpus = ms->smp.cpus; | |
63 | ||
64 | qemu_fdt_add_subnode(ms->fdt, "/cpus"); | |
65 | qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); | |
66 | qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); | |
67 | ||
68 | /* cpu nodes */ | |
69 | for (num = smp_cpus - 1; num >= 0; num--) { | |
70 | char *nodename = g_strdup_printf("/cpus/cpu@%d", num); | |
71 | LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); | |
72 | ||
73 | qemu_fdt_add_subnode(ms->fdt, nodename); | |
74 | qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); | |
75 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", | |
76 | cpu->dtb_compatible); | |
77 | qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); | |
78 | qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", | |
79 | qemu_fdt_alloc_phandle(ms->fdt)); | |
80 | g_free(nodename); | |
81 | } | |
82 | ||
83 | /*cpu map */ | |
84 | qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); | |
85 | ||
86 | for (num = smp_cpus - 1; num >= 0; num--) { | |
87 | char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); | |
88 | char *map_path; | |
89 | ||
90 | if (ms->smp.threads > 1) { | |
91 | map_path = g_strdup_printf( | |
92 | "/cpus/cpu-map/socket%d/core%d/thread%d", | |
93 | num / (ms->smp.cores * ms->smp.threads), | |
94 | (num / ms->smp.threads) % ms->smp.cores, | |
95 | num % ms->smp.threads); | |
96 | } else { | |
97 | map_path = g_strdup_printf( | |
98 | "/cpus/cpu-map/socket%d/core%d", | |
99 | num / ms->smp.cores, | |
100 | num % ms->smp.cores); | |
101 | } | |
102 | qemu_fdt_add_path(ms->fdt, map_path); | |
103 | qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); | |
104 | ||
105 | g_free(map_path); | |
106 | g_free(cpu_path); | |
107 | } | |
108 | } | |
109 | ||
110 | static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) | |
111 | { | |
112 | char *nodename; | |
113 | hwaddr base = VIRT_FWCFG_BASE; | |
114 | const MachineState *ms = MACHINE(lams); | |
115 | ||
116 | nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); | |
117 | qemu_fdt_add_subnode(ms->fdt, nodename); | |
118 | qemu_fdt_setprop_string(ms->fdt, nodename, | |
119 | "compatible", "qemu,fw-cfg-mmio"); | |
120 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", | |
121 | 2, base, 2, 0x8); | |
122 | qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); | |
123 | g_free(nodename); | |
124 | } | |
125 | ||
126 | static void fdt_add_pcie_node(const LoongArchMachineState *lams) | |
127 | { | |
128 | char *nodename; | |
74725231 XY |
129 | hwaddr base_mmio = VIRT_PCI_MEM_BASE; |
130 | hwaddr size_mmio = VIRT_PCI_MEM_SIZE; | |
131 | hwaddr base_pio = VIRT_PCI_IO_BASE; | |
132 | hwaddr size_pio = VIRT_PCI_IO_SIZE; | |
133 | hwaddr base_pcie = VIRT_PCI_CFG_BASE; | |
134 | hwaddr size_pcie = VIRT_PCI_CFG_SIZE; | |
fda3f15b XY |
135 | hwaddr base = base_pcie; |
136 | ||
137 | const MachineState *ms = MACHINE(lams); | |
138 | ||
139 | nodename = g_strdup_printf("/pcie@%" PRIx64, base); | |
140 | qemu_fdt_add_subnode(ms->fdt, nodename); | |
141 | qemu_fdt_setprop_string(ms->fdt, nodename, | |
142 | "compatible", "pci-host-ecam-generic"); | |
143 | qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); | |
144 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); | |
145 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); | |
146 | qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); | |
147 | qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, | |
74725231 | 148 | PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); |
fda3f15b XY |
149 | qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); |
150 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", | |
151 | 2, base_pcie, 2, size_pcie); | |
152 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", | |
74725231 | 153 | 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, |
fda3f15b XY |
154 | 2, base_pio, 2, size_pio, |
155 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
156 | 2, base_mmio, 2, size_mmio); | |
157 | g_free(nodename); | |
158 | qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size); | |
159 | } | |
160 | ||
a8a506c3 | 161 | |
9e6602d6 XY |
162 | #define PM_BASE 0x10080000 |
163 | #define PM_SIZE 0x100 | |
164 | #define PM_CTRL 0x10 | |
165 | ||
3efa6fa1 XY |
166 | static void virt_build_smbios(LoongArchMachineState *lams) |
167 | { | |
168 | MachineState *ms = MACHINE(lams); | |
169 | MachineClass *mc = MACHINE_GET_CLASS(lams); | |
170 | uint8_t *smbios_tables, *smbios_anchor; | |
171 | size_t smbios_tables_len, smbios_anchor_len; | |
172 | const char *product = "QEMU Virtual Machine"; | |
173 | ||
174 | if (!lams->fw_cfg) { | |
175 | return; | |
176 | } | |
177 | ||
178 | smbios_set_defaults("QEMU", product, mc->name, false, | |
179 | true, SMBIOS_ENTRY_POINT_TYPE_64); | |
180 | ||
181 | smbios_get_tables(ms, NULL, 0, &smbios_tables, &smbios_tables_len, | |
182 | &smbios_anchor, &smbios_anchor_len, &error_fatal); | |
183 | ||
184 | if (smbios_anchor) { | |
185 | fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", | |
186 | smbios_tables, smbios_tables_len); | |
187 | fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", | |
188 | smbios_anchor, smbios_anchor_len); | |
189 | } | |
190 | } | |
191 | ||
192 | static void virt_machine_done(Notifier *notifier, void *data) | |
193 | { | |
194 | LoongArchMachineState *lams = container_of(notifier, | |
195 | LoongArchMachineState, machine_done); | |
196 | virt_build_smbios(lams); | |
735143f1 | 197 | loongarch_acpi_setup(lams); |
3efa6fa1 XY |
198 | } |
199 | ||
27ad7564 XY |
200 | struct memmap_entry { |
201 | uint64_t address; | |
202 | uint64_t length; | |
203 | uint32_t type; | |
204 | uint32_t reserved; | |
205 | }; | |
206 | ||
207 | static struct memmap_entry *memmap_table; | |
208 | static unsigned memmap_entries; | |
209 | ||
210 | static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) | |
211 | { | |
212 | /* Ensure there are no duplicate entries. */ | |
213 | for (unsigned i = 0; i < memmap_entries; i++) { | |
214 | assert(memmap_table[i].address != address); | |
215 | } | |
216 | ||
217 | memmap_table = g_renew(struct memmap_entry, memmap_table, | |
218 | memmap_entries + 1); | |
219 | memmap_table[memmap_entries].address = cpu_to_le64(address); | |
220 | memmap_table[memmap_entries].length = cpu_to_le64(length); | |
221 | memmap_table[memmap_entries].type = cpu_to_le32(type); | |
222 | memmap_table[memmap_entries].reserved = 0; | |
223 | memmap_entries++; | |
224 | } | |
225 | ||
9e6602d6 XY |
226 | /* |
227 | * This is a placeholder for missing ACPI, | |
228 | * and will eventually be replaced. | |
229 | */ | |
230 | static uint64_t loongarch_virt_pm_read(void *opaque, hwaddr addr, unsigned size) | |
231 | { | |
232 | return 0; | |
233 | } | |
234 | ||
235 | static void loongarch_virt_pm_write(void *opaque, hwaddr addr, | |
236 | uint64_t val, unsigned size) | |
237 | { | |
238 | if (addr != PM_CTRL) { | |
239 | return; | |
240 | } | |
241 | ||
242 | switch (val) { | |
243 | case 0x00: | |
244 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
245 | return; | |
246 | case 0xff: | |
247 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | |
248 | return; | |
249 | default: | |
250 | return; | |
251 | } | |
252 | } | |
253 | ||
254 | static const MemoryRegionOps loongarch_virt_pm_ops = { | |
255 | .read = loongarch_virt_pm_read, | |
256 | .write = loongarch_virt_pm_write, | |
257 | .endianness = DEVICE_NATIVE_ENDIAN, | |
258 | .valid = { | |
259 | .min_access_size = 1, | |
260 | .max_access_size = 1 | |
261 | } | |
262 | }; | |
263 | ||
6a6f26f4 XY |
264 | static struct _loaderparams { |
265 | uint64_t ram_size; | |
266 | const char *kernel_filename; | |
fb1cd3a2 XY |
267 | const char *kernel_cmdline; |
268 | const char *initrd_filename; | |
6a6f26f4 XY |
269 | } loaderparams; |
270 | ||
271 | static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) | |
272 | { | |
273 | return addr & 0x1fffffffll; | |
274 | } | |
275 | ||
276 | static int64_t load_kernel_info(void) | |
277 | { | |
278 | uint64_t kernel_entry, kernel_low, kernel_high; | |
279 | ssize_t kernel_size; | |
280 | ||
281 | kernel_size = load_elf(loaderparams.kernel_filename, NULL, | |
282 | cpu_loongarch_virt_to_phys, NULL, | |
283 | &kernel_entry, &kernel_low, | |
284 | &kernel_high, NULL, 0, | |
285 | EM_LOONGARCH, 1, 0); | |
286 | ||
287 | if (kernel_size < 0) { | |
288 | error_report("could not load kernel '%s': %s", | |
289 | loaderparams.kernel_filename, | |
290 | load_elf_strerror(kernel_size)); | |
291 | exit(1); | |
292 | } | |
293 | return kernel_entry; | |
294 | } | |
295 | ||
735143f1 XY |
296 | static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) |
297 | { | |
298 | DeviceState *dev; | |
299 | MachineState *ms = MACHINE(lams); | |
300 | uint32_t event = ACPI_GED_PWR_DOWN_EVT; | |
301 | ||
302 | if (ms->ram_slots) { | |
303 | event |= ACPI_GED_MEM_HOTPLUG_EVT; | |
304 | } | |
305 | dev = qdev_new(TYPE_ACPI_GED); | |
306 | qdev_prop_set_uint32(dev, "ged-event", event); | |
307 | ||
308 | /* ged event */ | |
309 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); | |
310 | /* memory hotplug */ | |
311 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); | |
312 | /* ged regs used for reset and power down */ | |
313 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); | |
314 | ||
315 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, | |
74725231 | 316 | qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - PCH_PIC_IRQ_OFFSET)); |
735143f1 XY |
317 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
318 | return dev; | |
319 | } | |
320 | ||
321 | static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) | |
dc93b8df XY |
322 | { |
323 | DeviceState *gpex_dev; | |
324 | SysBusDevice *d; | |
325 | PCIBus *pci_bus; | |
326 | MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; | |
9e6602d6 | 327 | MemoryRegion *mmio_alias, *mmio_reg, *pm_mem; |
dc93b8df XY |
328 | int i; |
329 | ||
330 | gpex_dev = qdev_new(TYPE_GPEX_HOST); | |
331 | d = SYS_BUS_DEVICE(gpex_dev); | |
332 | sysbus_realize_and_unref(d, &error_fatal); | |
333 | pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; | |
334 | ||
335 | /* Map only part size_ecam bytes of ECAM space */ | |
336 | ecam_alias = g_new0(MemoryRegion, 1); | |
337 | ecam_reg = sysbus_mmio_get_region(d, 0); | |
338 | memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", | |
74725231 XY |
339 | ecam_reg, 0, VIRT_PCI_CFG_SIZE); |
340 | memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, | |
dc93b8df XY |
341 | ecam_alias); |
342 | ||
343 | /* Map PCI mem space */ | |
344 | mmio_alias = g_new0(MemoryRegion, 1); | |
345 | mmio_reg = sysbus_mmio_get_region(d, 1); | |
346 | memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", | |
74725231 XY |
347 | mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); |
348 | memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, | |
dc93b8df XY |
349 | mmio_alias); |
350 | ||
351 | /* Map PCI IO port space. */ | |
352 | pio_alias = g_new0(MemoryRegion, 1); | |
353 | pio_reg = sysbus_mmio_get_region(d, 2); | |
354 | memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, | |
74725231 XY |
355 | VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); |
356 | memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, | |
dc93b8df XY |
357 | pio_alias); |
358 | ||
359 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | |
360 | sysbus_connect_irq(d, i, | |
361 | qdev_get_gpio_in(pch_pic, 16 + i)); | |
362 | gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); | |
363 | } | |
364 | ||
74725231 | 365 | serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, |
dc93b8df | 366 | qdev_get_gpio_in(pch_pic, |
74725231 | 367 | VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET), |
dc93b8df XY |
368 | 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); |
369 | ||
370 | /* Network init */ | |
371 | for (i = 0; i < nb_nics; i++) { | |
372 | NICInfo *nd = &nd_table[i]; | |
373 | ||
374 | if (!nd->model) { | |
375 | nd->model = g_strdup("virtio"); | |
376 | } | |
377 | ||
378 | pci_nic_init_nofail(nd, pci_bus, nd->model, NULL); | |
379 | } | |
380 | ||
dc93b8df XY |
381 | /* |
382 | * There are some invalid guest memory access. | |
383 | * Create some unimplemented devices to emulate this. | |
384 | */ | |
385 | create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); | |
74725231 | 386 | sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, |
c117f68a | 387 | qdev_get_gpio_in(pch_pic, |
74725231 | 388 | VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET)); |
9e6602d6 XY |
389 | |
390 | pm_mem = g_new(MemoryRegion, 1); | |
391 | memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops, | |
392 | NULL, "loongarch_virt_pm", PM_SIZE); | |
393 | memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem); | |
735143f1 XY |
394 | /* acpi ged */ |
395 | lams->acpi_ged = create_acpi_ged(pch_pic, lams); | |
dc93b8df XY |
396 | } |
397 | ||
69d9c74f XY |
398 | static void loongarch_irq_init(LoongArchMachineState *lams) |
399 | { | |
400 | MachineState *ms = MACHINE(lams); | |
401 | DeviceState *pch_pic, *pch_msi, *cpudev; | |
402 | DeviceState *ipi, *extioi; | |
403 | SysBusDevice *d; | |
404 | LoongArchCPU *lacpu; | |
405 | CPULoongArchState *env; | |
406 | CPUState *cpu_state; | |
407 | int cpu, pin, i; | |
408 | ||
409 | ipi = qdev_new(TYPE_LOONGARCH_IPI); | |
410 | sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); | |
411 | ||
412 | extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); | |
413 | sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); | |
414 | ||
415 | /* | |
416 | * The connection of interrupts: | |
417 | * +-----+ +---------+ +-------+ | |
418 | * | IPI |--> | CPUINTC | <-- | Timer | | |
419 | * +-----+ +---------+ +-------+ | |
420 | * ^ | |
421 | * | | |
422 | * +---------+ | |
423 | * | EIOINTC | | |
424 | * +---------+ | |
425 | * ^ ^ | |
426 | * | | | |
427 | * +---------+ +---------+ | |
428 | * | PCH-PIC | | PCH-MSI | | |
429 | * +---------+ +---------+ | |
430 | * ^ ^ ^ | |
431 | * | | | | |
432 | * +--------+ +---------+ +---------+ | |
433 | * | UARTs | | Devices | | Devices | | |
434 | * +--------+ +---------+ +---------+ | |
435 | */ | |
436 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
437 | cpu_state = qemu_get_cpu(cpu); | |
438 | cpudev = DEVICE(cpu_state); | |
439 | lacpu = LOONGARCH_CPU(cpu_state); | |
440 | env = &(lacpu->env); | |
441 | ||
442 | /* connect ipi irq to cpu irq */ | |
443 | qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); | |
444 | /* IPI iocsr memory region */ | |
445 | memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX, | |
446 | sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), | |
ddf93261 XY |
447 | cpu * 2)); |
448 | memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR, | |
449 | sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), | |
450 | cpu * 2 + 1)); | |
69d9c74f XY |
451 | /* extioi iocsr memory region */ |
452 | memory_region_add_subregion(&env->system_iocsr, APIC_BASE, | |
453 | sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), | |
454 | cpu)); | |
455 | } | |
456 | ||
457 | /* | |
458 | * connect ext irq to the cpu irq | |
459 | * cpu_pin[9:2] <= intc_pin[7:0] | |
460 | */ | |
461 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
462 | cpudev = DEVICE(qemu_get_cpu(cpu)); | |
463 | for (pin = 0; pin < LS3A_INTC_IP; pin++) { | |
464 | qdev_connect_gpio_out(extioi, (cpu * 8 + pin), | |
465 | qdev_get_gpio_in(cpudev, pin + 2)); | |
466 | } | |
467 | } | |
468 | ||
469 | pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); | |
470 | d = SYS_BUS_DEVICE(pch_pic); | |
471 | sysbus_realize_and_unref(d, &error_fatal); | |
74725231 | 472 | memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, |
69d9c74f XY |
473 | sysbus_mmio_get_region(d, 0)); |
474 | memory_region_add_subregion(get_system_memory(), | |
74725231 | 475 | VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, |
69d9c74f XY |
476 | sysbus_mmio_get_region(d, 1)); |
477 | memory_region_add_subregion(get_system_memory(), | |
74725231 | 478 | VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, |
69d9c74f XY |
479 | sysbus_mmio_get_region(d, 2)); |
480 | ||
481 | /* Connect 64 pch_pic irqs to extioi */ | |
482 | for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) { | |
483 | qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); | |
484 | } | |
485 | ||
486 | pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); | |
490c03ab | 487 | qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START); |
69d9c74f XY |
488 | d = SYS_BUS_DEVICE(pch_msi); |
489 | sysbus_realize_and_unref(d, &error_fatal); | |
74725231 | 490 | sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); |
69d9c74f XY |
491 | for (i = 0; i < PCH_MSI_IRQ_NUM; i++) { |
492 | /* Connect 192 pch_msi irqs to extioi */ | |
493 | qdev_connect_gpio_out(DEVICE(d), i, | |
494 | qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START)); | |
495 | } | |
dc93b8df | 496 | |
735143f1 | 497 | loongarch_devices_init(pch_pic, lams); |
69d9c74f XY |
498 | } |
499 | ||
98afb0d4 XY |
500 | static void loongarch_firmware_init(LoongArchMachineState *lams) |
501 | { | |
502 | char *filename = MACHINE(lams)->firmware; | |
503 | char *bios_name = NULL; | |
504 | int bios_size; | |
505 | ||
506 | lams->bios_loaded = false; | |
507 | if (filename) { | |
508 | bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); | |
509 | if (!bios_name) { | |
510 | error_report("Could not find ROM image '%s'", filename); | |
511 | exit(1); | |
512 | } | |
513 | ||
514 | bios_size = load_image_targphys(bios_name, VIRT_BIOS_BASE, VIRT_BIOS_SIZE); | |
515 | if (bios_size < 0) { | |
516 | error_report("Could not load ROM image '%s'", bios_name); | |
517 | exit(1); | |
518 | } | |
519 | ||
520 | g_free(bios_name); | |
521 | ||
522 | memory_region_init_ram(&lams->bios, NULL, "loongarch.bios", | |
523 | VIRT_BIOS_SIZE, &error_fatal); | |
524 | memory_region_set_readonly(&lams->bios, true); | |
525 | memory_region_add_subregion(get_system_memory(), VIRT_BIOS_BASE, &lams->bios); | |
526 | lams->bios_loaded = true; | |
527 | } | |
528 | ||
529 | } | |
530 | ||
6a6f26f4 XY |
531 | static void reset_load_elf(void *opaque) |
532 | { | |
533 | LoongArchCPU *cpu = opaque; | |
534 | CPULoongArchState *env = &cpu->env; | |
535 | ||
536 | cpu_reset(CPU(cpu)); | |
537 | if (env->load_elf) { | |
538 | cpu_set_pc(CPU(cpu), env->elf_address); | |
539 | } | |
540 | } | |
541 | ||
fb1cd3a2 XY |
542 | /* Load an image file into an fw_cfg entry identified by key. */ |
543 | static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, | |
544 | uint16_t data_key, const char *image_name, | |
545 | bool try_decompress) | |
546 | { | |
547 | size_t size = -1; | |
548 | uint8_t *data; | |
549 | ||
550 | if (image_name == NULL) { | |
551 | return; | |
552 | } | |
553 | ||
554 | if (try_decompress) { | |
555 | size = load_image_gzipped_buffer(image_name, | |
556 | LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); | |
557 | } | |
558 | ||
559 | if (size == (size_t)-1) { | |
560 | gchar *contents; | |
561 | gsize length; | |
562 | ||
563 | if (!g_file_get_contents(image_name, &contents, &length, NULL)) { | |
564 | error_report("failed to load \"%s\"", image_name); | |
565 | exit(1); | |
566 | } | |
567 | size = length; | |
568 | data = (uint8_t *)contents; | |
569 | } | |
570 | ||
571 | fw_cfg_add_i32(fw_cfg, size_key, size); | |
572 | fw_cfg_add_bytes(fw_cfg, data_key, data, size); | |
573 | } | |
574 | ||
575 | static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg) | |
576 | { | |
577 | /* | |
578 | * Expose the kernel, the command line, and the initrd in fw_cfg. | |
579 | * We don't process them here at all, it's all left to the | |
580 | * firmware. | |
581 | */ | |
582 | load_image_to_fw_cfg(fw_cfg, | |
583 | FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, | |
584 | loaderparams.kernel_filename, | |
585 | false); | |
586 | ||
587 | if (loaderparams.initrd_filename) { | |
588 | load_image_to_fw_cfg(fw_cfg, | |
589 | FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, | |
590 | loaderparams.initrd_filename, false); | |
591 | } | |
592 | ||
593 | if (loaderparams.kernel_cmdline) { | |
594 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | |
595 | strlen(loaderparams.kernel_cmdline) + 1); | |
596 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, | |
597 | loaderparams.kernel_cmdline); | |
598 | } | |
599 | } | |
600 | ||
601 | static void loongarch_firmware_boot(LoongArchMachineState *lams) | |
602 | { | |
603 | fw_cfg_add_kernel_info(lams->fw_cfg); | |
604 | } | |
605 | ||
606 | static void loongarch_direct_kernel_boot(LoongArchMachineState *lams) | |
607 | { | |
608 | MachineState *machine = MACHINE(lams); | |
609 | int64_t kernel_addr = 0; | |
610 | LoongArchCPU *lacpu; | |
611 | int i; | |
612 | ||
613 | kernel_addr = load_kernel_info(); | |
614 | if (!machine->firmware) { | |
615 | for (i = 0; i < machine->smp.cpus; i++) { | |
616 | lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); | |
617 | lacpu->env.load_elf = true; | |
618 | lacpu->env.elf_address = kernel_addr; | |
619 | } | |
620 | } | |
621 | } | |
622 | ||
a8a506c3 XY |
623 | static void loongarch_init(MachineState *machine) |
624 | { | |
fb1cd3a2 | 625 | LoongArchCPU *lacpu; |
a8a506c3 XY |
626 | const char *cpu_model = machine->cpu_type; |
627 | ram_addr_t offset = 0; | |
628 | ram_addr_t ram_size = machine->ram_size; | |
629 | uint64_t highram_size = 0; | |
630 | MemoryRegion *address_space_mem = get_system_memory(); | |
631 | LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); | |
632 | int i; | |
633 | ||
634 | if (!cpu_model) { | |
635 | cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); | |
636 | } | |
637 | ||
638 | if (!strstr(cpu_model, "la464")) { | |
639 | error_report("LoongArch/TCG needs cpu type la464"); | |
640 | exit(1); | |
641 | } | |
642 | ||
643 | if (ram_size < 1 * GiB) { | |
644 | error_report("ram_size must be greater than 1G."); | |
645 | exit(1); | |
646 | } | |
fda3f15b | 647 | create_fdt(lams); |
a8a506c3 XY |
648 | /* Init CPUs */ |
649 | for (i = 0; i < machine->smp.cpus; i++) { | |
650 | cpu_create(machine->cpu_type); | |
651 | } | |
fda3f15b | 652 | fdt_add_cpu_nodes(lams); |
a8a506c3 XY |
653 | /* Add memory region */ |
654 | memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram", | |
655 | machine->ram, 0, 256 * MiB); | |
656 | memory_region_add_subregion(address_space_mem, offset, &lams->lowmem); | |
657 | offset += 256 * MiB; | |
27ad7564 | 658 | memmap_add_entry(0, 256 * MiB, 1); |
a8a506c3 XY |
659 | highram_size = ram_size - 256 * MiB; |
660 | memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem", | |
661 | machine->ram, offset, highram_size); | |
662 | memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem); | |
27ad7564 | 663 | memmap_add_entry(0x90000000, highram_size, 1); |
a8a506c3 XY |
664 | /* Add isa io region */ |
665 | memory_region_init_alias(&lams->isa_io, NULL, "isa-io", | |
74725231 XY |
666 | get_system_io(), 0, VIRT_ISA_IO_SIZE); |
667 | memory_region_add_subregion(address_space_mem, VIRT_ISA_IO_BASE, | |
a8a506c3 | 668 | &lams->isa_io); |
98afb0d4 XY |
669 | /* load the BIOS image. */ |
670 | loongarch_firmware_init(lams); | |
671 | ||
27ad7564 XY |
672 | /* fw_cfg init */ |
673 | lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); | |
674 | rom_set_fw(lams->fw_cfg); | |
27ad7564 XY |
675 | if (lams->fw_cfg != NULL) { |
676 | fw_cfg_add_file(lams->fw_cfg, "etc/memmap", | |
677 | memmap_table, | |
678 | sizeof(struct memmap_entry) * (memmap_entries)); | |
679 | } | |
fda3f15b | 680 | fdt_add_fw_cfg_node(lams); |
fb1cd3a2 XY |
681 | loaderparams.ram_size = ram_size; |
682 | loaderparams.kernel_filename = machine->kernel_filename; | |
683 | loaderparams.kernel_cmdline = machine->kernel_cmdline; | |
684 | loaderparams.initrd_filename = machine->initrd_filename; | |
685 | /* load the kernel. */ | |
686 | if (loaderparams.kernel_filename) { | |
687 | if (lams->bios_loaded) { | |
688 | loongarch_firmware_boot(lams); | |
689 | } else { | |
690 | loongarch_direct_kernel_boot(lams); | |
6a6f26f4 XY |
691 | } |
692 | } | |
fb1cd3a2 XY |
693 | /* register reset function */ |
694 | for (i = 0; i < machine->smp.cpus; i++) { | |
695 | lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); | |
696 | qemu_register_reset(reset_load_elf, lacpu); | |
697 | } | |
69d9c74f XY |
698 | /* Initialize the IO interrupt subsystem */ |
699 | loongarch_irq_init(lams); | |
3efa6fa1 XY |
700 | lams->machine_done.notify = virt_machine_done; |
701 | qemu_add_machine_init_done_notifier(&lams->machine_done); | |
fda3f15b XY |
702 | fdt_add_pcie_node(lams); |
703 | ||
704 | /* load fdt */ | |
705 | MemoryRegion *fdt_rom = g_new(MemoryRegion, 1); | |
74725231 XY |
706 | memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal); |
707 | memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom); | |
708 | rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE); | |
a8a506c3 XY |
709 | } |
710 | ||
735143f1 XY |
711 | bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) |
712 | { | |
713 | if (lams->acpi == ON_OFF_AUTO_OFF) { | |
714 | return false; | |
715 | } | |
716 | return true; | |
717 | } | |
718 | ||
719 | static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, | |
720 | void *opaque, Error **errp) | |
721 | { | |
722 | LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); | |
723 | OnOffAuto acpi = lams->acpi; | |
724 | ||
725 | visit_type_OnOffAuto(v, name, &acpi, errp); | |
726 | } | |
727 | ||
728 | static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, | |
729 | void *opaque, Error **errp) | |
730 | { | |
731 | LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); | |
732 | ||
733 | visit_type_OnOffAuto(v, name, &lams->acpi, errp); | |
734 | } | |
735 | ||
736 | static void loongarch_machine_initfn(Object *obj) | |
737 | { | |
738 | LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); | |
739 | ||
740 | lams->acpi = ON_OFF_AUTO_AUTO; | |
741 | lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); | |
742 | lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); | |
743 | } | |
744 | ||
a8a506c3 XY |
745 | static void loongarch_class_init(ObjectClass *oc, void *data) |
746 | { | |
747 | MachineClass *mc = MACHINE_CLASS(oc); | |
748 | ||
749 | mc->desc = "Loongson-3A5000 LS7A1000 machine"; | |
750 | mc->init = loongarch_init; | |
751 | mc->default_ram_size = 1 * GiB; | |
752 | mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); | |
753 | mc->default_ram_id = "loongarch.ram"; | |
754 | mc->max_cpus = LOONGARCH_MAX_VCPUS; | |
755 | mc->is_default = 1; | |
756 | mc->default_kernel_irqchip_split = false; | |
757 | mc->block_default_type = IF_VIRTIO; | |
758 | mc->default_boot_order = "c"; | |
759 | mc->no_cdrom = 1; | |
735143f1 XY |
760 | |
761 | object_class_property_add(oc, "acpi", "OnOffAuto", | |
762 | loongarch_get_acpi, loongarch_set_acpi, | |
763 | NULL, NULL); | |
764 | object_class_property_set_description(oc, "acpi", | |
765 | "Enable ACPI"); | |
a8a506c3 XY |
766 | } |
767 | ||
768 | static const TypeInfo loongarch_machine_types[] = { | |
769 | { | |
770 | .name = TYPE_LOONGARCH_MACHINE, | |
771 | .parent = TYPE_MACHINE, | |
772 | .instance_size = sizeof(LoongArchMachineState), | |
773 | .class_init = loongarch_class_init, | |
735143f1 | 774 | .instance_init = loongarch_machine_initfn, |
a8a506c3 XY |
775 | } |
776 | }; | |
777 | ||
778 | DEFINE_TYPES(loongarch_machine_types) |