]>
Commit | Line | Data |
---|---|---|
4d00636e JB |
1 | /* |
2 | * Copyright (c) 2006 Fabrice Bellard | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
5 | * of this software and associated documentation files (the "Software"), to deal | |
6 | * in the Software without restriction, including without limitation the rights | |
7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
8 | * copies of the Software, and to permit persons to whom the Software is | |
9 | * furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
20 | * THE SOFTWARE. | |
21 | */ | |
22 | /* | |
23 | * QEMU ICH9 Emulation | |
24 | * | |
25 | * Copyright (c) 2009, 2010, 2011 | |
26 | * Isaku Yamahata <yamahata at valinux co jp> | |
27 | * VA Linux Systems Japan K.K. | |
28 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> | |
29 | * | |
30 | * This is based on piix_pci.c, but heavily modified. | |
31 | * | |
32 | * This library is free software; you can redistribute it and/or | |
33 | * modify it under the terms of the GNU Lesser General Public | |
34 | * License as published by the Free Software Foundation; either | |
35 | * version 2 of the License, or (at your option) any later version. | |
36 | * | |
37 | * This library is distributed in the hope that it will be useful, | |
38 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
39 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
40 | * Lesser General Public License for more details. | |
41 | * | |
42 | * You should have received a copy of the GNU Lesser General Public | |
43 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
44 | */ | |
45 | ||
46 | #include "qemu-common.h" | |
47 | #include "hw.h" | |
48 | #include "range.h" | |
49 | #include "isa.h" | |
50 | #include "sysbus.h" | |
51 | #include "pc.h" | |
52 | #include "apm.h" | |
53 | #include "ioapic.h" | |
54 | #include "pci.h" | |
55 | #include "pcie_host.h" | |
56 | #include "pci_bridge.h" | |
57 | #include "ich9.h" | |
58 | #include "acpi.h" | |
59 | #include "acpi_ich9.h" | |
60 | #include "pam.h" | |
61 | #include "pci_internals.h" | |
62 | #include "exec-memory.h" | |
3f5bc9e8 | 63 | #include "sysemu.h" |
4d00636e JB |
64 | |
65 | static int ich9_lpc_sci_irq(ICH9LPCState *lpc); | |
66 | ||
67 | /*****************************************************************************/ | |
68 | /* ICH9 LPC PCI to ISA bridge */ | |
69 | ||
70 | static void ich9_lpc_reset(DeviceState *qdev); | |
71 | ||
72 | /* chipset configuration register | |
73 | * to access chipset configuration registers, pci_[sg]et_{byte, word, long} | |
74 | * are used. | |
75 | * Although it's not pci configuration space, it's little endian as Intel. | |
76 | */ | |
77 | ||
78 | static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) | |
79 | { | |
80 | int intx; | |
81 | for (intx = 0; intx < PCI_NUM_PINS; intx++) { | |
82 | irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; | |
83 | } | |
84 | } | |
85 | ||
86 | static void ich9_cc_update(ICH9LPCState *lpc) | |
87 | { | |
88 | int slot; | |
89 | int pci_intx; | |
90 | ||
91 | const int reg_offsets[] = { | |
92 | ICH9_CC_D25IR, | |
93 | ICH9_CC_D26IR, | |
94 | ICH9_CC_D27IR, | |
95 | ICH9_CC_D28IR, | |
96 | ICH9_CC_D29IR, | |
97 | ICH9_CC_D30IR, | |
98 | ICH9_CC_D31IR, | |
99 | }; | |
100 | const int *offset; | |
101 | ||
102 | /* D{25 - 31}IR, but D30IR is read only to 0. */ | |
103 | for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { | |
104 | if (slot == 30) { | |
105 | continue; | |
106 | } | |
107 | ich9_cc_update_ir(lpc->irr[slot], | |
108 | pci_get_word(lpc->chip_config + *offset)); | |
109 | } | |
110 | ||
111 | /* | |
112 | * D30: DMI2PCI bridge | |
113 | * It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge | |
114 | * are connected to pirq lines. Our choice is PIRQ[E-H]. | |
115 | * INT[A-D] are connected to PIRQ[E-H] | |
116 | */ | |
117 | for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { | |
118 | lpc->irr[30][pci_intx] = pci_intx + 4; | |
119 | } | |
120 | } | |
121 | ||
122 | static void ich9_cc_init(ICH9LPCState *lpc) | |
123 | { | |
124 | int slot; | |
125 | int intx; | |
126 | ||
127 | /* the default irq routing is arbitrary as long as it matches with | |
128 | * acpi irq routing table. | |
129 | * The one that is incompatible with piix_pci(= bochs) one is | |
130 | * intentionally chosen to let the users know that the different | |
131 | * board is used. | |
132 | * | |
133 | * int[A-D] -> pirq[E-F] | |
134 | * avoid pirq A-D because they are used for pci express port | |
135 | */ | |
136 | for (slot = 0; slot < PCI_SLOT_MAX; slot++) { | |
137 | for (intx = 0; intx < PCI_NUM_PINS; intx++) { | |
138 | lpc->irr[slot][intx] = (slot + intx) % 4 + 4; | |
139 | } | |
140 | } | |
141 | ich9_cc_update(lpc); | |
142 | } | |
143 | ||
144 | static void ich9_cc_reset(ICH9LPCState *lpc) | |
145 | { | |
146 | uint8_t *c = lpc->chip_config; | |
147 | ||
148 | memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); | |
149 | ||
150 | pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); | |
151 | pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); | |
152 | pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); | |
153 | pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); | |
154 | pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); | |
155 | pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); | |
156 | pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); | |
157 | ||
158 | ich9_cc_update(lpc); | |
159 | } | |
160 | ||
161 | static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) | |
162 | { | |
163 | *addr &= ICH9_CC_ADDR_MASK; | |
164 | if (*addr + *len >= ICH9_CC_SIZE) { | |
165 | *len = ICH9_CC_SIZE - *addr; | |
166 | } | |
167 | } | |
168 | ||
169 | /* val: little endian */ | |
170 | static void ich9_cc_write(void *opaque, hwaddr addr, | |
171 | uint64_t val, unsigned len) | |
172 | { | |
173 | ICH9LPCState *lpc = (ICH9LPCState *)opaque; | |
174 | ||
175 | ich9_cc_addr_len(&addr, &len); | |
176 | memcpy(lpc->chip_config + addr, &val, len); | |
177 | ich9_cc_update(lpc); | |
178 | } | |
179 | ||
180 | /* return value: little endian */ | |
181 | static uint64_t ich9_cc_read(void *opaque, hwaddr addr, | |
182 | unsigned len) | |
183 | { | |
184 | ICH9LPCState *lpc = (ICH9LPCState *)opaque; | |
185 | ||
186 | uint32_t val = 0; | |
187 | ich9_cc_addr_len(&addr, &len); | |
188 | memcpy(&val, lpc->chip_config + addr, len); | |
189 | return val; | |
190 | } | |
191 | ||
192 | /* IRQ routing */ | |
193 | /* */ | |
194 | static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) | |
195 | { | |
196 | *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; | |
197 | *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; | |
198 | } | |
199 | ||
200 | static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, | |
201 | int *pic_irq, int *pic_dis) | |
202 | { | |
203 | switch (pirq_num) { | |
204 | case 0 ... 3: /* A-D */ | |
205 | ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], | |
206 | pic_irq, pic_dis); | |
207 | return; | |
208 | case 4 ... 7: /* E-H */ | |
209 | ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], | |
210 | pic_irq, pic_dis); | |
211 | return; | |
212 | default: | |
213 | break; | |
214 | } | |
215 | abort(); | |
216 | } | |
217 | ||
218 | /* pic_irq: i8254 irq 0-15 */ | |
219 | static void ich9_lpc_update_pic(ICH9LPCState *lpc, int pic_irq) | |
220 | { | |
221 | int i, pic_level; | |
222 | ||
223 | /* The pic level is the logical OR of all the PCI irqs mapped to it */ | |
224 | pic_level = 0; | |
225 | for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { | |
226 | int tmp_irq; | |
227 | int tmp_dis; | |
228 | ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); | |
229 | if (!tmp_dis && pic_irq == tmp_irq) { | |
230 | pic_level |= pci_bus_get_irq_level(lpc->d.bus, i); | |
231 | } | |
232 | } | |
233 | if (pic_irq == ich9_lpc_sci_irq(lpc)) { | |
234 | pic_level |= lpc->sci_level; | |
235 | } | |
236 | ||
237 | qemu_set_irq(lpc->pic[pic_irq], pic_level); | |
238 | } | |
239 | ||
240 | /* pirq: pirq[A-H] 0-7*/ | |
241 | static void ich9_lpc_update_by_pirq(ICH9LPCState *lpc, int pirq) | |
242 | { | |
243 | int pic_irq; | |
244 | int pic_dis; | |
245 | ||
246 | ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); | |
247 | assert(pic_irq < ICH9_LPC_PIC_NUM_PINS); | |
248 | if (pic_dis) { | |
249 | return; | |
250 | } | |
251 | ||
252 | ich9_lpc_update_pic(lpc, pic_irq); | |
253 | } | |
254 | ||
255 | /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ | |
256 | static int ich9_pirq_to_gsi(int pirq) | |
257 | { | |
258 | return pirq + ICH9_LPC_PIC_NUM_PINS; | |
259 | } | |
260 | ||
261 | static int ich9_gsi_to_pirq(int gsi) | |
262 | { | |
263 | return gsi - ICH9_LPC_PIC_NUM_PINS; | |
264 | } | |
265 | ||
266 | static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) | |
267 | { | |
243b9511 | 268 | int level = 0; |
4d00636e | 269 | |
243b9511 JK |
270 | if (gsi >= ICH9_LPC_PIC_NUM_PINS) { |
271 | level |= pci_bus_get_irq_level(lpc->d.bus, ich9_gsi_to_pirq(gsi)); | |
272 | } | |
4d00636e JB |
273 | if (gsi == ich9_lpc_sci_irq(lpc)) { |
274 | level |= lpc->sci_level; | |
275 | } | |
276 | ||
277 | qemu_set_irq(lpc->ioapic[gsi], level); | |
278 | } | |
279 | ||
280 | void ich9_lpc_set_irq(void *opaque, int pirq, int level) | |
281 | { | |
282 | ICH9LPCState *lpc = opaque; | |
283 | ||
284 | assert(0 <= pirq); | |
285 | assert(pirq < ICH9_LPC_NB_PIRQS); | |
286 | ||
287 | ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); | |
288 | ich9_lpc_update_by_pirq(lpc, pirq); | |
289 | } | |
290 | ||
291 | /* return the pirq number (PIRQ[A-H]:0-7) corresponding to | |
292 | * a given device irq pin. | |
293 | */ | |
294 | int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) | |
295 | { | |
296 | BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); | |
297 | PCIBus *pci_bus = PCI_BUS(bus); | |
298 | PCIDevice *lpc_pdev = | |
299 | pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; | |
300 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); | |
301 | ||
302 | return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; | |
303 | } | |
304 | ||
305 | static int ich9_lpc_sci_irq(ICH9LPCState *lpc) | |
306 | { | |
307 | switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] & | |
308 | ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) { | |
309 | case ICH9_LPC_ACPI_CTRL_9: | |
310 | return 9; | |
311 | case ICH9_LPC_ACPI_CTRL_10: | |
312 | return 10; | |
313 | case ICH9_LPC_ACPI_CTRL_11: | |
314 | return 11; | |
315 | case ICH9_LPC_ACPI_CTRL_20: | |
316 | return 20; | |
317 | case ICH9_LPC_ACPI_CTRL_21: | |
318 | return 21; | |
319 | default: | |
320 | /* reserved */ | |
321 | break; | |
322 | } | |
323 | return -1; | |
324 | } | |
325 | ||
326 | static void ich9_set_sci(void *opaque, int irq_num, int level) | |
327 | { | |
328 | ICH9LPCState *lpc = opaque; | |
329 | int irq; | |
330 | ||
331 | assert(irq_num == 0); | |
332 | level = !!level; | |
333 | if (level == lpc->sci_level) { | |
334 | return; | |
335 | } | |
336 | lpc->sci_level = level; | |
337 | ||
338 | irq = ich9_lpc_sci_irq(lpc); | |
339 | if (irq < 0) { | |
340 | return; | |
341 | } | |
342 | ||
343 | ich9_lpc_update_apic(lpc, irq); | |
344 | if (irq < ICH9_LPC_PIC_NUM_PINS) { | |
345 | ich9_lpc_update_pic(lpc, irq); | |
346 | } | |
347 | } | |
348 | ||
349 | void ich9_lpc_pm_init(PCIDevice *lpc_pci, qemu_irq cmos_s3) | |
350 | { | |
351 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); | |
352 | qemu_irq *sci_irq; | |
353 | ||
354 | sci_irq = qemu_allocate_irqs(ich9_set_sci, lpc, 1); | |
355 | ich9_pm_init(&lpc->pm, sci_irq[0], cmos_s3); | |
356 | ||
357 | ich9_lpc_reset(&lpc->d.qdev); | |
358 | } | |
359 | ||
360 | /* APM */ | |
361 | ||
362 | static void ich9_apm_ctrl_changed(uint32_t val, void *arg) | |
363 | { | |
364 | ICH9LPCState *lpc = arg; | |
365 | ||
366 | /* ACPI specs 3.0, 4.7.2.5 */ | |
367 | acpi_pm1_cnt_update(&lpc->pm.acpi_regs, | |
368 | val == ICH9_APM_ACPI_ENABLE, | |
369 | val == ICH9_APM_ACPI_DISABLE); | |
370 | ||
371 | /* SMI_EN = PMBASE + 30. SMI control and enable register */ | |
372 | if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { | |
373 | cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); | |
374 | } | |
375 | } | |
376 | ||
377 | /* config:PMBASE */ | |
378 | static void | |
379 | ich9_lpc_pmbase_update(ICH9LPCState *lpc) | |
380 | { | |
381 | uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); | |
382 | pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; | |
383 | ||
384 | ich9_pm_iospace_update(&lpc->pm, pm_io_base); | |
385 | } | |
386 | ||
387 | /* config:RBCA */ | |
388 | static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rbca_old) | |
389 | { | |
390 | uint32_t rbca = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); | |
391 | ||
392 | if (rbca_old & ICH9_LPC_RCBA_EN) { | |
393 | memory_region_del_subregion(get_system_memory(), &lpc->rbca_mem); | |
394 | } | |
395 | if (rbca & ICH9_LPC_RCBA_EN) { | |
396 | memory_region_add_subregion_overlap(get_system_memory(), | |
397 | rbca & ICH9_LPC_RCBA_BA_MASK, | |
398 | &lpc->rbca_mem, 1); | |
399 | } | |
400 | } | |
401 | ||
402 | static int ich9_lpc_post_load(void *opaque, int version_id) | |
403 | { | |
404 | ICH9LPCState *lpc = opaque; | |
405 | ||
406 | ich9_lpc_pmbase_update(lpc); | |
407 | ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RBCA_EN */); | |
408 | return 0; | |
409 | } | |
410 | ||
411 | static void ich9_lpc_config_write(PCIDevice *d, | |
412 | uint32_t addr, uint32_t val, int len) | |
413 | { | |
414 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); | |
415 | uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA); | |
416 | ||
417 | pci_default_write_config(d, addr, val, len); | |
418 | if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4)) { | |
419 | ich9_lpc_pmbase_update(lpc); | |
420 | } | |
421 | if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { | |
422 | ich9_lpc_rcba_update(lpc, rbca_old); | |
423 | } | |
424 | } | |
425 | ||
426 | static void ich9_lpc_reset(DeviceState *qdev) | |
427 | { | |
428 | PCIDevice *d = PCI_DEVICE(qdev); | |
429 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); | |
430 | uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA); | |
431 | int i; | |
432 | ||
433 | for (i = 0; i < 4; i++) { | |
434 | pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, | |
435 | ICH9_LPC_PIRQ_ROUT_DEFAULT); | |
436 | } | |
437 | for (i = 0; i < 4; i++) { | |
438 | pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, | |
439 | ICH9_LPC_PIRQ_ROUT_DEFAULT); | |
440 | } | |
441 | pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); | |
442 | ||
443 | pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); | |
444 | pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); | |
445 | ||
446 | ich9_cc_reset(lpc); | |
447 | ||
448 | ich9_lpc_pmbase_update(lpc); | |
449 | ich9_lpc_rcba_update(lpc, rbca_old); | |
450 | ||
451 | lpc->sci_level = 0; | |
452 | } | |
453 | ||
454 | static const MemoryRegionOps rbca_mmio_ops = { | |
455 | .read = ich9_cc_read, | |
456 | .write = ich9_cc_write, | |
457 | .endianness = DEVICE_LITTLE_ENDIAN, | |
458 | }; | |
459 | ||
3f5bc9e8 GH |
460 | static void ich9_lpc_machine_ready(Notifier *n, void *opaque) |
461 | { | |
462 | ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); | |
463 | uint8_t *pci_conf; | |
464 | ||
465 | pci_conf = s->d.config; | |
466 | if (isa_is_ioport_assigned(0x3f8)) { | |
467 | /* com1 */ | |
468 | pci_conf[0x82] |= 0x01; | |
469 | } | |
470 | if (isa_is_ioport_assigned(0x2f8)) { | |
471 | /* com2 */ | |
472 | pci_conf[0x82] |= 0x02; | |
473 | } | |
474 | if (isa_is_ioport_assigned(0x378)) { | |
475 | /* lpt */ | |
476 | pci_conf[0x82] |= 0x04; | |
477 | } | |
478 | if (isa_is_ioport_assigned(0x3f0)) { | |
479 | /* floppy */ | |
480 | pci_conf[0x82] |= 0x08; | |
481 | } | |
482 | } | |
483 | ||
4d00636e JB |
484 | static int ich9_lpc_initfn(PCIDevice *d) |
485 | { | |
486 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); | |
487 | ISABus *isa_bus; | |
488 | ||
489 | isa_bus = isa_bus_new(&d->qdev, get_system_io()); | |
490 | ||
491 | pci_set_long(d->wmask + ICH9_LPC_PMBASE, | |
492 | ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); | |
493 | ||
494 | memory_region_init_io(&lpc->rbca_mem, &rbca_mmio_ops, lpc, | |
495 | "lpc-rbca-mmio", ICH9_CC_SIZE); | |
496 | ||
497 | lpc->isa_bus = isa_bus; | |
498 | ||
499 | ich9_cc_init(lpc); | |
42d8a3cf | 500 | apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); |
3f5bc9e8 GH |
501 | |
502 | lpc->machine_ready.notify = ich9_lpc_machine_ready; | |
503 | qemu_add_machine_init_done_notifier(&lpc->machine_ready); | |
504 | ||
4d00636e JB |
505 | return 0; |
506 | } | |
507 | ||
508 | static const VMStateDescription vmstate_ich9_lpc = { | |
509 | .name = "ICH9LPC", | |
510 | .version_id = 1, | |
511 | .minimum_version_id = 1, | |
512 | .minimum_version_id_old = 1, | |
513 | .post_load = ich9_lpc_post_load, | |
514 | .fields = (VMStateField[]) { | |
515 | VMSTATE_PCI_DEVICE(d, ICH9LPCState), | |
516 | VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), | |
517 | VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), | |
518 | VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), | |
519 | VMSTATE_UINT32(sci_level, ICH9LPCState), | |
520 | VMSTATE_END_OF_LIST() | |
521 | } | |
522 | }; | |
523 | ||
524 | static void ich9_lpc_class_init(ObjectClass *klass, void *data) | |
525 | { | |
526 | DeviceClass *dc = DEVICE_CLASS(klass); | |
527 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
528 | ||
529 | dc->reset = ich9_lpc_reset; | |
530 | k->init = ich9_lpc_initfn; | |
531 | dc->vmsd = &vmstate_ich9_lpc; | |
532 | dc->no_user = 1; | |
533 | k->config_write = ich9_lpc_config_write; | |
534 | dc->desc = "ICH9 LPC bridge"; | |
535 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
536 | k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; | |
537 | k->revision = ICH9_A2_LPC_REVISION; | |
538 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
539 | ||
540 | } | |
541 | ||
542 | static const TypeInfo ich9_lpc_info = { | |
543 | .name = TYPE_ICH9_LPC_DEVICE, | |
544 | .parent = TYPE_PCI_DEVICE, | |
545 | .instance_size = sizeof(struct ICH9LPCState), | |
546 | .class_init = ich9_lpc_class_init, | |
547 | }; | |
548 | ||
549 | static void ich9_lpc_register(void) | |
550 | { | |
551 | type_register_static(&ich9_lpc_info); | |
552 | } | |
553 | ||
554 | type_init(ich9_lpc_register); |