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4d00636e JB |
1 | /* |
2 | * Copyright (c) 2006 Fabrice Bellard | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
5 | * of this software and associated documentation files (the "Software"), to deal | |
6 | * in the Software without restriction, including without limitation the rights | |
7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
8 | * copies of the Software, and to permit persons to whom the Software is | |
9 | * furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
20 | * THE SOFTWARE. | |
21 | */ | |
22 | /* | |
23 | * QEMU ICH9 Emulation | |
24 | * | |
25 | * Copyright (c) 2009, 2010, 2011 | |
26 | * Isaku Yamahata <yamahata at valinux co jp> | |
27 | * VA Linux Systems Japan K.K. | |
28 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> | |
29 | * | |
30 | * This is based on piix_pci.c, but heavily modified. | |
31 | * | |
32 | * This library is free software; you can redistribute it and/or | |
33 | * modify it under the terms of the GNU Lesser General Public | |
34 | * License as published by the Free Software Foundation; either | |
35 | * version 2 of the License, or (at your option) any later version. | |
36 | * | |
37 | * This library is distributed in the hope that it will be useful, | |
38 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
39 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
40 | * Lesser General Public License for more details. | |
41 | * | |
42 | * You should have received a copy of the GNU Lesser General Public | |
43 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
44 | */ | |
45 | ||
46 | #include "qemu-common.h" | |
47 | #include "hw.h" | |
48 | #include "range.h" | |
49 | #include "isa.h" | |
50 | #include "sysbus.h" | |
51 | #include "pc.h" | |
52 | #include "apm.h" | |
53 | #include "ioapic.h" | |
54 | #include "pci.h" | |
55 | #include "pcie_host.h" | |
56 | #include "pci_bridge.h" | |
57 | #include "ich9.h" | |
58 | #include "acpi.h" | |
59 | #include "acpi_ich9.h" | |
60 | #include "pam.h" | |
61 | #include "pci_internals.h" | |
62 | #include "exec-memory.h" | |
63 | ||
64 | static int ich9_lpc_sci_irq(ICH9LPCState *lpc); | |
65 | ||
66 | /*****************************************************************************/ | |
67 | /* ICH9 LPC PCI to ISA bridge */ | |
68 | ||
69 | static void ich9_lpc_reset(DeviceState *qdev); | |
70 | ||
71 | /* chipset configuration register | |
72 | * to access chipset configuration registers, pci_[sg]et_{byte, word, long} | |
73 | * are used. | |
74 | * Although it's not pci configuration space, it's little endian as Intel. | |
75 | */ | |
76 | ||
77 | static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) | |
78 | { | |
79 | int intx; | |
80 | for (intx = 0; intx < PCI_NUM_PINS; intx++) { | |
81 | irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; | |
82 | } | |
83 | } | |
84 | ||
85 | static void ich9_cc_update(ICH9LPCState *lpc) | |
86 | { | |
87 | int slot; | |
88 | int pci_intx; | |
89 | ||
90 | const int reg_offsets[] = { | |
91 | ICH9_CC_D25IR, | |
92 | ICH9_CC_D26IR, | |
93 | ICH9_CC_D27IR, | |
94 | ICH9_CC_D28IR, | |
95 | ICH9_CC_D29IR, | |
96 | ICH9_CC_D30IR, | |
97 | ICH9_CC_D31IR, | |
98 | }; | |
99 | const int *offset; | |
100 | ||
101 | /* D{25 - 31}IR, but D30IR is read only to 0. */ | |
102 | for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { | |
103 | if (slot == 30) { | |
104 | continue; | |
105 | } | |
106 | ich9_cc_update_ir(lpc->irr[slot], | |
107 | pci_get_word(lpc->chip_config + *offset)); | |
108 | } | |
109 | ||
110 | /* | |
111 | * D30: DMI2PCI bridge | |
112 | * It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge | |
113 | * are connected to pirq lines. Our choice is PIRQ[E-H]. | |
114 | * INT[A-D] are connected to PIRQ[E-H] | |
115 | */ | |
116 | for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { | |
117 | lpc->irr[30][pci_intx] = pci_intx + 4; | |
118 | } | |
119 | } | |
120 | ||
121 | static void ich9_cc_init(ICH9LPCState *lpc) | |
122 | { | |
123 | int slot; | |
124 | int intx; | |
125 | ||
126 | /* the default irq routing is arbitrary as long as it matches with | |
127 | * acpi irq routing table. | |
128 | * The one that is incompatible with piix_pci(= bochs) one is | |
129 | * intentionally chosen to let the users know that the different | |
130 | * board is used. | |
131 | * | |
132 | * int[A-D] -> pirq[E-F] | |
133 | * avoid pirq A-D because they are used for pci express port | |
134 | */ | |
135 | for (slot = 0; slot < PCI_SLOT_MAX; slot++) { | |
136 | for (intx = 0; intx < PCI_NUM_PINS; intx++) { | |
137 | lpc->irr[slot][intx] = (slot + intx) % 4 + 4; | |
138 | } | |
139 | } | |
140 | ich9_cc_update(lpc); | |
141 | } | |
142 | ||
143 | static void ich9_cc_reset(ICH9LPCState *lpc) | |
144 | { | |
145 | uint8_t *c = lpc->chip_config; | |
146 | ||
147 | memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); | |
148 | ||
149 | pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); | |
150 | pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); | |
151 | pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); | |
152 | pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); | |
153 | pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); | |
154 | pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); | |
155 | pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); | |
156 | ||
157 | ich9_cc_update(lpc); | |
158 | } | |
159 | ||
160 | static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) | |
161 | { | |
162 | *addr &= ICH9_CC_ADDR_MASK; | |
163 | if (*addr + *len >= ICH9_CC_SIZE) { | |
164 | *len = ICH9_CC_SIZE - *addr; | |
165 | } | |
166 | } | |
167 | ||
168 | /* val: little endian */ | |
169 | static void ich9_cc_write(void *opaque, hwaddr addr, | |
170 | uint64_t val, unsigned len) | |
171 | { | |
172 | ICH9LPCState *lpc = (ICH9LPCState *)opaque; | |
173 | ||
174 | ich9_cc_addr_len(&addr, &len); | |
175 | memcpy(lpc->chip_config + addr, &val, len); | |
176 | ich9_cc_update(lpc); | |
177 | } | |
178 | ||
179 | /* return value: little endian */ | |
180 | static uint64_t ich9_cc_read(void *opaque, hwaddr addr, | |
181 | unsigned len) | |
182 | { | |
183 | ICH9LPCState *lpc = (ICH9LPCState *)opaque; | |
184 | ||
185 | uint32_t val = 0; | |
186 | ich9_cc_addr_len(&addr, &len); | |
187 | memcpy(&val, lpc->chip_config + addr, len); | |
188 | return val; | |
189 | } | |
190 | ||
191 | /* IRQ routing */ | |
192 | /* */ | |
193 | static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) | |
194 | { | |
195 | *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; | |
196 | *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; | |
197 | } | |
198 | ||
199 | static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, | |
200 | int *pic_irq, int *pic_dis) | |
201 | { | |
202 | switch (pirq_num) { | |
203 | case 0 ... 3: /* A-D */ | |
204 | ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], | |
205 | pic_irq, pic_dis); | |
206 | return; | |
207 | case 4 ... 7: /* E-H */ | |
208 | ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], | |
209 | pic_irq, pic_dis); | |
210 | return; | |
211 | default: | |
212 | break; | |
213 | } | |
214 | abort(); | |
215 | } | |
216 | ||
217 | /* pic_irq: i8254 irq 0-15 */ | |
218 | static void ich9_lpc_update_pic(ICH9LPCState *lpc, int pic_irq) | |
219 | { | |
220 | int i, pic_level; | |
221 | ||
222 | /* The pic level is the logical OR of all the PCI irqs mapped to it */ | |
223 | pic_level = 0; | |
224 | for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { | |
225 | int tmp_irq; | |
226 | int tmp_dis; | |
227 | ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); | |
228 | if (!tmp_dis && pic_irq == tmp_irq) { | |
229 | pic_level |= pci_bus_get_irq_level(lpc->d.bus, i); | |
230 | } | |
231 | } | |
232 | if (pic_irq == ich9_lpc_sci_irq(lpc)) { | |
233 | pic_level |= lpc->sci_level; | |
234 | } | |
235 | ||
236 | qemu_set_irq(lpc->pic[pic_irq], pic_level); | |
237 | } | |
238 | ||
239 | /* pirq: pirq[A-H] 0-7*/ | |
240 | static void ich9_lpc_update_by_pirq(ICH9LPCState *lpc, int pirq) | |
241 | { | |
242 | int pic_irq; | |
243 | int pic_dis; | |
244 | ||
245 | ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); | |
246 | assert(pic_irq < ICH9_LPC_PIC_NUM_PINS); | |
247 | if (pic_dis) { | |
248 | return; | |
249 | } | |
250 | ||
251 | ich9_lpc_update_pic(lpc, pic_irq); | |
252 | } | |
253 | ||
254 | /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ | |
255 | static int ich9_pirq_to_gsi(int pirq) | |
256 | { | |
257 | return pirq + ICH9_LPC_PIC_NUM_PINS; | |
258 | } | |
259 | ||
260 | static int ich9_gsi_to_pirq(int gsi) | |
261 | { | |
262 | return gsi - ICH9_LPC_PIC_NUM_PINS; | |
263 | } | |
264 | ||
265 | static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) | |
266 | { | |
243b9511 | 267 | int level = 0; |
4d00636e | 268 | |
243b9511 JK |
269 | if (gsi >= ICH9_LPC_PIC_NUM_PINS) { |
270 | level |= pci_bus_get_irq_level(lpc->d.bus, ich9_gsi_to_pirq(gsi)); | |
271 | } | |
4d00636e JB |
272 | if (gsi == ich9_lpc_sci_irq(lpc)) { |
273 | level |= lpc->sci_level; | |
274 | } | |
275 | ||
276 | qemu_set_irq(lpc->ioapic[gsi], level); | |
277 | } | |
278 | ||
279 | void ich9_lpc_set_irq(void *opaque, int pirq, int level) | |
280 | { | |
281 | ICH9LPCState *lpc = opaque; | |
282 | ||
283 | assert(0 <= pirq); | |
284 | assert(pirq < ICH9_LPC_NB_PIRQS); | |
285 | ||
286 | ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); | |
287 | ich9_lpc_update_by_pirq(lpc, pirq); | |
288 | } | |
289 | ||
290 | /* return the pirq number (PIRQ[A-H]:0-7) corresponding to | |
291 | * a given device irq pin. | |
292 | */ | |
293 | int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) | |
294 | { | |
295 | BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); | |
296 | PCIBus *pci_bus = PCI_BUS(bus); | |
297 | PCIDevice *lpc_pdev = | |
298 | pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; | |
299 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); | |
300 | ||
301 | return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; | |
302 | } | |
303 | ||
304 | static int ich9_lpc_sci_irq(ICH9LPCState *lpc) | |
305 | { | |
306 | switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] & | |
307 | ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) { | |
308 | case ICH9_LPC_ACPI_CTRL_9: | |
309 | return 9; | |
310 | case ICH9_LPC_ACPI_CTRL_10: | |
311 | return 10; | |
312 | case ICH9_LPC_ACPI_CTRL_11: | |
313 | return 11; | |
314 | case ICH9_LPC_ACPI_CTRL_20: | |
315 | return 20; | |
316 | case ICH9_LPC_ACPI_CTRL_21: | |
317 | return 21; | |
318 | default: | |
319 | /* reserved */ | |
320 | break; | |
321 | } | |
322 | return -1; | |
323 | } | |
324 | ||
325 | static void ich9_set_sci(void *opaque, int irq_num, int level) | |
326 | { | |
327 | ICH9LPCState *lpc = opaque; | |
328 | int irq; | |
329 | ||
330 | assert(irq_num == 0); | |
331 | level = !!level; | |
332 | if (level == lpc->sci_level) { | |
333 | return; | |
334 | } | |
335 | lpc->sci_level = level; | |
336 | ||
337 | irq = ich9_lpc_sci_irq(lpc); | |
338 | if (irq < 0) { | |
339 | return; | |
340 | } | |
341 | ||
342 | ich9_lpc_update_apic(lpc, irq); | |
343 | if (irq < ICH9_LPC_PIC_NUM_PINS) { | |
344 | ich9_lpc_update_pic(lpc, irq); | |
345 | } | |
346 | } | |
347 | ||
348 | void ich9_lpc_pm_init(PCIDevice *lpc_pci, qemu_irq cmos_s3) | |
349 | { | |
350 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); | |
351 | qemu_irq *sci_irq; | |
352 | ||
353 | sci_irq = qemu_allocate_irqs(ich9_set_sci, lpc, 1); | |
354 | ich9_pm_init(&lpc->pm, sci_irq[0], cmos_s3); | |
355 | ||
356 | ich9_lpc_reset(&lpc->d.qdev); | |
357 | } | |
358 | ||
359 | /* APM */ | |
360 | ||
361 | static void ich9_apm_ctrl_changed(uint32_t val, void *arg) | |
362 | { | |
363 | ICH9LPCState *lpc = arg; | |
364 | ||
365 | /* ACPI specs 3.0, 4.7.2.5 */ | |
366 | acpi_pm1_cnt_update(&lpc->pm.acpi_regs, | |
367 | val == ICH9_APM_ACPI_ENABLE, | |
368 | val == ICH9_APM_ACPI_DISABLE); | |
369 | ||
370 | /* SMI_EN = PMBASE + 30. SMI control and enable register */ | |
371 | if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { | |
372 | cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); | |
373 | } | |
374 | } | |
375 | ||
376 | /* config:PMBASE */ | |
377 | static void | |
378 | ich9_lpc_pmbase_update(ICH9LPCState *lpc) | |
379 | { | |
380 | uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); | |
381 | pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; | |
382 | ||
383 | ich9_pm_iospace_update(&lpc->pm, pm_io_base); | |
384 | } | |
385 | ||
386 | /* config:RBCA */ | |
387 | static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rbca_old) | |
388 | { | |
389 | uint32_t rbca = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); | |
390 | ||
391 | if (rbca_old & ICH9_LPC_RCBA_EN) { | |
392 | memory_region_del_subregion(get_system_memory(), &lpc->rbca_mem); | |
393 | } | |
394 | if (rbca & ICH9_LPC_RCBA_EN) { | |
395 | memory_region_add_subregion_overlap(get_system_memory(), | |
396 | rbca & ICH9_LPC_RCBA_BA_MASK, | |
397 | &lpc->rbca_mem, 1); | |
398 | } | |
399 | } | |
400 | ||
401 | static int ich9_lpc_post_load(void *opaque, int version_id) | |
402 | { | |
403 | ICH9LPCState *lpc = opaque; | |
404 | ||
405 | ich9_lpc_pmbase_update(lpc); | |
406 | ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RBCA_EN */); | |
407 | return 0; | |
408 | } | |
409 | ||
410 | static void ich9_lpc_config_write(PCIDevice *d, | |
411 | uint32_t addr, uint32_t val, int len) | |
412 | { | |
413 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); | |
414 | uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA); | |
415 | ||
416 | pci_default_write_config(d, addr, val, len); | |
417 | if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4)) { | |
418 | ich9_lpc_pmbase_update(lpc); | |
419 | } | |
420 | if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { | |
421 | ich9_lpc_rcba_update(lpc, rbca_old); | |
422 | } | |
423 | } | |
424 | ||
425 | static void ich9_lpc_reset(DeviceState *qdev) | |
426 | { | |
427 | PCIDevice *d = PCI_DEVICE(qdev); | |
428 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); | |
429 | uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA); | |
430 | int i; | |
431 | ||
432 | for (i = 0; i < 4; i++) { | |
433 | pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, | |
434 | ICH9_LPC_PIRQ_ROUT_DEFAULT); | |
435 | } | |
436 | for (i = 0; i < 4; i++) { | |
437 | pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, | |
438 | ICH9_LPC_PIRQ_ROUT_DEFAULT); | |
439 | } | |
440 | pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); | |
441 | ||
442 | pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); | |
443 | pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); | |
444 | ||
445 | ich9_cc_reset(lpc); | |
446 | ||
447 | ich9_lpc_pmbase_update(lpc); | |
448 | ich9_lpc_rcba_update(lpc, rbca_old); | |
449 | ||
450 | lpc->sci_level = 0; | |
451 | } | |
452 | ||
453 | static const MemoryRegionOps rbca_mmio_ops = { | |
454 | .read = ich9_cc_read, | |
455 | .write = ich9_cc_write, | |
456 | .endianness = DEVICE_LITTLE_ENDIAN, | |
457 | }; | |
458 | ||
459 | static int ich9_lpc_initfn(PCIDevice *d) | |
460 | { | |
461 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); | |
462 | ISABus *isa_bus; | |
463 | ||
464 | isa_bus = isa_bus_new(&d->qdev, get_system_io()); | |
465 | ||
466 | pci_set_long(d->wmask + ICH9_LPC_PMBASE, | |
467 | ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); | |
468 | ||
469 | memory_region_init_io(&lpc->rbca_mem, &rbca_mmio_ops, lpc, | |
470 | "lpc-rbca-mmio", ICH9_CC_SIZE); | |
471 | ||
472 | lpc->isa_bus = isa_bus; | |
473 | ||
474 | ich9_cc_init(lpc); | |
42d8a3cf | 475 | apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); |
4d00636e JB |
476 | return 0; |
477 | } | |
478 | ||
479 | static const VMStateDescription vmstate_ich9_lpc = { | |
480 | .name = "ICH9LPC", | |
481 | .version_id = 1, | |
482 | .minimum_version_id = 1, | |
483 | .minimum_version_id_old = 1, | |
484 | .post_load = ich9_lpc_post_load, | |
485 | .fields = (VMStateField[]) { | |
486 | VMSTATE_PCI_DEVICE(d, ICH9LPCState), | |
487 | VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), | |
488 | VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), | |
489 | VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), | |
490 | VMSTATE_UINT32(sci_level, ICH9LPCState), | |
491 | VMSTATE_END_OF_LIST() | |
492 | } | |
493 | }; | |
494 | ||
495 | static void ich9_lpc_class_init(ObjectClass *klass, void *data) | |
496 | { | |
497 | DeviceClass *dc = DEVICE_CLASS(klass); | |
498 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
499 | ||
500 | dc->reset = ich9_lpc_reset; | |
501 | k->init = ich9_lpc_initfn; | |
502 | dc->vmsd = &vmstate_ich9_lpc; | |
503 | dc->no_user = 1; | |
504 | k->config_write = ich9_lpc_config_write; | |
505 | dc->desc = "ICH9 LPC bridge"; | |
506 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
507 | k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; | |
508 | k->revision = ICH9_A2_LPC_REVISION; | |
509 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
510 | ||
511 | } | |
512 | ||
513 | static const TypeInfo ich9_lpc_info = { | |
514 | .name = TYPE_ICH9_LPC_DEVICE, | |
515 | .parent = TYPE_PCI_DEVICE, | |
516 | .instance_size = sizeof(struct ICH9LPCState), | |
517 | .class_init = ich9_lpc_class_init, | |
518 | }; | |
519 | ||
520 | static void ich9_lpc_register(void) | |
521 | { | |
522 | type_register_static(&ich9_lpc_info); | |
523 | } | |
524 | ||
525 | type_init(ich9_lpc_register); |