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Commit | Line | Data |
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a541f297 | 1 | /* |
819385c5 | 2 | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms |
5fafdf24 | 3 | * |
3ccacc4a | 4 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "nvram.h" | |
87ecb68b PB |
26 | #include "qemu-timer.h" |
27 | #include "sysemu.h" | |
d27cf0ae | 28 | #include "sysbus.h" |
f80237d4 | 29 | #include "isa.h" |
a541f297 | 30 | |
13ab5daa | 31 | //#define DEBUG_NVRAM |
a541f297 | 32 | |
13ab5daa | 33 | #if defined(DEBUG_NVRAM) |
001faf32 | 34 | #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
a541f297 | 35 | #else |
001faf32 | 36 | #define NVRAM_PRINTF(fmt, ...) do { } while (0) |
a541f297 FB |
37 | #endif |
38 | ||
819385c5 | 39 | /* |
4aed2c33 | 40 | * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has |
819385c5 FB |
41 | * alarm and a watchdog timer and related control registers. In the |
42 | * PPC platform there is also a nvram lock function. | |
43 | */ | |
930f3fe1 BS |
44 | |
45 | /* | |
46 | * Chipset docs: | |
47 | * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf | |
48 | * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf | |
49 | * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf | |
50 | */ | |
51 | ||
43a34704 | 52 | struct M48t59State { |
a541f297 | 53 | /* Hardware parameters */ |
d537cf6c | 54 | qemu_irq IRQ; |
a541f297 | 55 | uint32_t io_base; |
ee6847d1 | 56 | uint32_t size; |
a541f297 FB |
57 | /* RTC management */ |
58 | time_t time_offset; | |
59 | time_t stop_time; | |
60 | /* Alarm & watchdog */ | |
f6503059 | 61 | struct tm alarm; |
a541f297 FB |
62 | struct QEMUTimer *alrm_timer; |
63 | struct QEMUTimer *wd_timer; | |
64 | /* NVRAM storage */ | |
a541f297 | 65 | uint8_t *buffer; |
42c812b9 BS |
66 | /* Model parameters */ |
67 | uint32_t type; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */ | |
68 | /* NVRAM storage */ | |
69 | uint16_t addr; | |
70 | uint8_t lock; | |
c5df018e | 71 | }; |
a541f297 | 72 | |
f80237d4 BS |
73 | typedef struct M48t59ISAState { |
74 | ISADevice busdev; | |
43a34704 | 75 | M48t59State state; |
9936d6e4 | 76 | MemoryRegion io; |
f80237d4 BS |
77 | } M48t59ISAState; |
78 | ||
79 | typedef struct M48t59SysBusState { | |
80 | SysBusDevice busdev; | |
43a34704 | 81 | M48t59State state; |
f80237d4 BS |
82 | } M48t59SysBusState; |
83 | ||
a541f297 | 84 | /* Fake timer functions */ |
a541f297 | 85 | |
a541f297 FB |
86 | /* Alarm management */ |
87 | static void alarm_cb (void *opaque) | |
88 | { | |
f6503059 | 89 | struct tm tm; |
a541f297 | 90 | uint64_t next_time; |
43a34704 | 91 | M48t59State *NVRAM = opaque; |
a541f297 | 92 | |
d537cf6c | 93 | qemu_set_irq(NVRAM->IRQ, 1); |
5fafdf24 | 94 | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
a541f297 FB |
95 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
96 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
97 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
98 | /* Repeat once a month */ |
99 | qemu_get_timedate(&tm, NVRAM->time_offset); | |
100 | tm.tm_mon++; | |
101 | if (tm.tm_mon == 13) { | |
102 | tm.tm_mon = 1; | |
103 | tm.tm_year++; | |
104 | } | |
105 | next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; | |
a541f297 FB |
106 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
107 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && | |
108 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
109 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
110 | /* Repeat once a day */ |
111 | next_time = 24 * 60 * 60; | |
a541f297 FB |
112 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
113 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && | |
114 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
115 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
116 | /* Repeat once an hour */ |
117 | next_time = 60 * 60; | |
a541f297 FB |
118 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
119 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && | |
120 | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && | |
121 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
122 | /* Repeat once a minute */ |
123 | next_time = 60; | |
a541f297 | 124 | } else { |
f6503059 AZ |
125 | /* Repeat once a second */ |
126 | next_time = 1; | |
a541f297 | 127 | } |
74475455 | 128 | qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(vm_clock) + |
f6503059 | 129 | next_time * 1000); |
d537cf6c | 130 | qemu_set_irq(NVRAM->IRQ, 0); |
a541f297 FB |
131 | } |
132 | ||
43a34704 | 133 | static void set_alarm(M48t59State *NVRAM) |
f6503059 AZ |
134 | { |
135 | int diff; | |
136 | if (NVRAM->alrm_timer != NULL) { | |
137 | qemu_del_timer(NVRAM->alrm_timer); | |
138 | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; | |
139 | if (diff > 0) | |
140 | qemu_mod_timer(NVRAM->alrm_timer, diff * 1000); | |
141 | } | |
142 | } | |
a541f297 | 143 | |
f6503059 | 144 | /* RTC management helpers */ |
43a34704 | 145 | static inline void get_time(M48t59State *NVRAM, struct tm *tm) |
a541f297 | 146 | { |
f6503059 | 147 | qemu_get_timedate(tm, NVRAM->time_offset); |
a541f297 FB |
148 | } |
149 | ||
43a34704 | 150 | static void set_time(M48t59State *NVRAM, struct tm *tm) |
a541f297 | 151 | { |
f6503059 AZ |
152 | NVRAM->time_offset = qemu_timedate_diff(tm); |
153 | set_alarm(NVRAM); | |
a541f297 FB |
154 | } |
155 | ||
156 | /* Watchdog management */ | |
157 | static void watchdog_cb (void *opaque) | |
158 | { | |
43a34704 | 159 | M48t59State *NVRAM = opaque; |
a541f297 FB |
160 | |
161 | NVRAM->buffer[0x1FF0] |= 0x80; | |
162 | if (NVRAM->buffer[0x1FF7] & 0x80) { | |
163 | NVRAM->buffer[0x1FF7] = 0x00; | |
164 | NVRAM->buffer[0x1FFC] &= ~0x40; | |
13ab5daa | 165 | /* May it be a hw CPU Reset instead ? */ |
d7d02e3c | 166 | qemu_system_reset_request(); |
a541f297 | 167 | } else { |
d537cf6c PB |
168 | qemu_set_irq(NVRAM->IRQ, 1); |
169 | qemu_set_irq(NVRAM->IRQ, 0); | |
a541f297 FB |
170 | } |
171 | } | |
172 | ||
43a34704 | 173 | static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) |
a541f297 FB |
174 | { |
175 | uint64_t interval; /* in 1/16 seconds */ | |
176 | ||
868d585a | 177 | NVRAM->buffer[0x1FF0] &= ~0x80; |
a541f297 FB |
178 | if (NVRAM->wd_timer != NULL) { |
179 | qemu_del_timer(NVRAM->wd_timer); | |
868d585a JM |
180 | if (value != 0) { |
181 | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); | |
182 | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + | |
183 | ((interval * 1000) >> 4)); | |
184 | } | |
a541f297 FB |
185 | } |
186 | } | |
187 | ||
188 | /* Direct access to NVRAM */ | |
897b4c6c | 189 | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
a541f297 | 190 | { |
43a34704 | 191 | M48t59State *NVRAM = opaque; |
a541f297 FB |
192 | struct tm tm; |
193 | int tmp; | |
194 | ||
819385c5 FB |
195 | if (addr > 0x1FF8 && addr < 0x2000) |
196 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); | |
4aed2c33 BS |
197 | |
198 | /* check for NVRAM access */ | |
199 | if ((NVRAM->type == 2 && addr < 0x7f8) || | |
200 | (NVRAM->type == 8 && addr < 0x1ff8) || | |
201 | (NVRAM->type == 59 && addr < 0x1ff0)) | |
819385c5 | 202 | goto do_write; |
4aed2c33 BS |
203 | |
204 | /* TOD access */ | |
819385c5 | 205 | switch (addr) { |
a541f297 FB |
206 | case 0x1FF0: |
207 | /* flags register : read-only */ | |
208 | break; | |
209 | case 0x1FF1: | |
210 | /* unused */ | |
211 | break; | |
212 | case 0x1FF2: | |
213 | /* alarm seconds */ | |
abd0c6bd | 214 | tmp = from_bcd(val & 0x7F); |
819385c5 | 215 | if (tmp >= 0 && tmp <= 59) { |
f6503059 | 216 | NVRAM->alarm.tm_sec = tmp; |
819385c5 | 217 | NVRAM->buffer[0x1FF2] = val; |
f6503059 | 218 | set_alarm(NVRAM); |
819385c5 | 219 | } |
a541f297 FB |
220 | break; |
221 | case 0x1FF3: | |
222 | /* alarm minutes */ | |
abd0c6bd | 223 | tmp = from_bcd(val & 0x7F); |
819385c5 | 224 | if (tmp >= 0 && tmp <= 59) { |
f6503059 | 225 | NVRAM->alarm.tm_min = tmp; |
819385c5 | 226 | NVRAM->buffer[0x1FF3] = val; |
f6503059 | 227 | set_alarm(NVRAM); |
819385c5 | 228 | } |
a541f297 FB |
229 | break; |
230 | case 0x1FF4: | |
231 | /* alarm hours */ | |
abd0c6bd | 232 | tmp = from_bcd(val & 0x3F); |
819385c5 | 233 | if (tmp >= 0 && tmp <= 23) { |
f6503059 | 234 | NVRAM->alarm.tm_hour = tmp; |
819385c5 | 235 | NVRAM->buffer[0x1FF4] = val; |
f6503059 | 236 | set_alarm(NVRAM); |
819385c5 | 237 | } |
a541f297 FB |
238 | break; |
239 | case 0x1FF5: | |
240 | /* alarm date */ | |
abd0c6bd | 241 | tmp = from_bcd(val & 0x1F); |
819385c5 | 242 | if (tmp != 0) { |
f6503059 | 243 | NVRAM->alarm.tm_mday = tmp; |
819385c5 | 244 | NVRAM->buffer[0x1FF5] = val; |
f6503059 | 245 | set_alarm(NVRAM); |
819385c5 | 246 | } |
a541f297 FB |
247 | break; |
248 | case 0x1FF6: | |
249 | /* interrupts */ | |
819385c5 | 250 | NVRAM->buffer[0x1FF6] = val; |
a541f297 FB |
251 | break; |
252 | case 0x1FF7: | |
253 | /* watchdog */ | |
819385c5 FB |
254 | NVRAM->buffer[0x1FF7] = val; |
255 | set_up_watchdog(NVRAM, val); | |
a541f297 FB |
256 | break; |
257 | case 0x1FF8: | |
4aed2c33 | 258 | case 0x07F8: |
a541f297 | 259 | /* control */ |
4aed2c33 | 260 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
a541f297 FB |
261 | break; |
262 | case 0x1FF9: | |
4aed2c33 | 263 | case 0x07F9: |
a541f297 | 264 | /* seconds (BCD) */ |
abd0c6bd | 265 | tmp = from_bcd(val & 0x7F); |
a541f297 FB |
266 | if (tmp >= 0 && tmp <= 59) { |
267 | get_time(NVRAM, &tm); | |
268 | tm.tm_sec = tmp; | |
269 | set_time(NVRAM, &tm); | |
270 | } | |
f6503059 | 271 | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
a541f297 FB |
272 | if (val & 0x80) { |
273 | NVRAM->stop_time = time(NULL); | |
274 | } else { | |
275 | NVRAM->time_offset += NVRAM->stop_time - time(NULL); | |
276 | NVRAM->stop_time = 0; | |
277 | } | |
278 | } | |
f6503059 | 279 | NVRAM->buffer[addr] = val & 0x80; |
a541f297 FB |
280 | break; |
281 | case 0x1FFA: | |
4aed2c33 | 282 | case 0x07FA: |
a541f297 | 283 | /* minutes (BCD) */ |
abd0c6bd | 284 | tmp = from_bcd(val & 0x7F); |
a541f297 FB |
285 | if (tmp >= 0 && tmp <= 59) { |
286 | get_time(NVRAM, &tm); | |
287 | tm.tm_min = tmp; | |
288 | set_time(NVRAM, &tm); | |
289 | } | |
290 | break; | |
291 | case 0x1FFB: | |
4aed2c33 | 292 | case 0x07FB: |
a541f297 | 293 | /* hours (BCD) */ |
abd0c6bd | 294 | tmp = from_bcd(val & 0x3F); |
a541f297 FB |
295 | if (tmp >= 0 && tmp <= 23) { |
296 | get_time(NVRAM, &tm); | |
297 | tm.tm_hour = tmp; | |
298 | set_time(NVRAM, &tm); | |
299 | } | |
300 | break; | |
301 | case 0x1FFC: | |
4aed2c33 | 302 | case 0x07FC: |
a541f297 | 303 | /* day of the week / century */ |
abd0c6bd | 304 | tmp = from_bcd(val & 0x07); |
a541f297 FB |
305 | get_time(NVRAM, &tm); |
306 | tm.tm_wday = tmp; | |
307 | set_time(NVRAM, &tm); | |
4aed2c33 | 308 | NVRAM->buffer[addr] = val & 0x40; |
a541f297 FB |
309 | break; |
310 | case 0x1FFD: | |
4aed2c33 | 311 | case 0x07FD: |
a541f297 | 312 | /* date */ |
abd0c6bd | 313 | tmp = from_bcd(val & 0x1F); |
a541f297 FB |
314 | if (tmp != 0) { |
315 | get_time(NVRAM, &tm); | |
316 | tm.tm_mday = tmp; | |
317 | set_time(NVRAM, &tm); | |
318 | } | |
319 | break; | |
320 | case 0x1FFE: | |
4aed2c33 | 321 | case 0x07FE: |
a541f297 | 322 | /* month */ |
abd0c6bd | 323 | tmp = from_bcd(val & 0x1F); |
a541f297 FB |
324 | if (tmp >= 1 && tmp <= 12) { |
325 | get_time(NVRAM, &tm); | |
326 | tm.tm_mon = tmp - 1; | |
327 | set_time(NVRAM, &tm); | |
328 | } | |
329 | break; | |
330 | case 0x1FFF: | |
4aed2c33 | 331 | case 0x07FF: |
a541f297 | 332 | /* year */ |
abd0c6bd | 333 | tmp = from_bcd(val); |
a541f297 FB |
334 | if (tmp >= 0 && tmp <= 99) { |
335 | get_time(NVRAM, &tm); | |
180b700d | 336 | if (NVRAM->type == 8) |
abd0c6bd | 337 | tm.tm_year = from_bcd(val) + 68; // Base year is 1968 |
180b700d | 338 | else |
abd0c6bd | 339 | tm.tm_year = from_bcd(val); |
a541f297 FB |
340 | set_time(NVRAM, &tm); |
341 | } | |
342 | break; | |
343 | default: | |
13ab5daa | 344 | /* Check lock registers state */ |
819385c5 | 345 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
13ab5daa | 346 | break; |
819385c5 | 347 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
13ab5daa | 348 | break; |
819385c5 FB |
349 | do_write: |
350 | if (addr < NVRAM->size) { | |
351 | NVRAM->buffer[addr] = val & 0xFF; | |
a541f297 FB |
352 | } |
353 | break; | |
354 | } | |
355 | } | |
356 | ||
897b4c6c | 357 | uint32_t m48t59_read (void *opaque, uint32_t addr) |
a541f297 | 358 | { |
43a34704 | 359 | M48t59State *NVRAM = opaque; |
a541f297 FB |
360 | struct tm tm; |
361 | uint32_t retval = 0xFF; | |
362 | ||
4aed2c33 BS |
363 | /* check for NVRAM access */ |
364 | if ((NVRAM->type == 2 && addr < 0x078f) || | |
365 | (NVRAM->type == 8 && addr < 0x1ff8) || | |
366 | (NVRAM->type == 59 && addr < 0x1ff0)) | |
819385c5 | 367 | goto do_read; |
4aed2c33 BS |
368 | |
369 | /* TOD access */ | |
819385c5 | 370 | switch (addr) { |
a541f297 FB |
371 | case 0x1FF0: |
372 | /* flags register */ | |
373 | goto do_read; | |
374 | case 0x1FF1: | |
375 | /* unused */ | |
376 | retval = 0; | |
377 | break; | |
378 | case 0x1FF2: | |
379 | /* alarm seconds */ | |
380 | goto do_read; | |
381 | case 0x1FF3: | |
382 | /* alarm minutes */ | |
383 | goto do_read; | |
384 | case 0x1FF4: | |
385 | /* alarm hours */ | |
386 | goto do_read; | |
387 | case 0x1FF5: | |
388 | /* alarm date */ | |
389 | goto do_read; | |
390 | case 0x1FF6: | |
391 | /* interrupts */ | |
392 | goto do_read; | |
393 | case 0x1FF7: | |
394 | /* A read resets the watchdog */ | |
395 | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]); | |
396 | goto do_read; | |
397 | case 0x1FF8: | |
4aed2c33 | 398 | case 0x07F8: |
a541f297 FB |
399 | /* control */ |
400 | goto do_read; | |
401 | case 0x1FF9: | |
4aed2c33 | 402 | case 0x07F9: |
a541f297 FB |
403 | /* seconds (BCD) */ |
404 | get_time(NVRAM, &tm); | |
abd0c6bd | 405 | retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec); |
a541f297 FB |
406 | break; |
407 | case 0x1FFA: | |
4aed2c33 | 408 | case 0x07FA: |
a541f297 FB |
409 | /* minutes (BCD) */ |
410 | get_time(NVRAM, &tm); | |
abd0c6bd | 411 | retval = to_bcd(tm.tm_min); |
a541f297 FB |
412 | break; |
413 | case 0x1FFB: | |
4aed2c33 | 414 | case 0x07FB: |
a541f297 FB |
415 | /* hours (BCD) */ |
416 | get_time(NVRAM, &tm); | |
abd0c6bd | 417 | retval = to_bcd(tm.tm_hour); |
a541f297 FB |
418 | break; |
419 | case 0x1FFC: | |
4aed2c33 | 420 | case 0x07FC: |
a541f297 FB |
421 | /* day of the week / century */ |
422 | get_time(NVRAM, &tm); | |
4aed2c33 | 423 | retval = NVRAM->buffer[addr] | tm.tm_wday; |
a541f297 FB |
424 | break; |
425 | case 0x1FFD: | |
4aed2c33 | 426 | case 0x07FD: |
a541f297 FB |
427 | /* date */ |
428 | get_time(NVRAM, &tm); | |
abd0c6bd | 429 | retval = to_bcd(tm.tm_mday); |
a541f297 FB |
430 | break; |
431 | case 0x1FFE: | |
4aed2c33 | 432 | case 0x07FE: |
a541f297 FB |
433 | /* month */ |
434 | get_time(NVRAM, &tm); | |
abd0c6bd | 435 | retval = to_bcd(tm.tm_mon + 1); |
a541f297 FB |
436 | break; |
437 | case 0x1FFF: | |
4aed2c33 | 438 | case 0x07FF: |
a541f297 FB |
439 | /* year */ |
440 | get_time(NVRAM, &tm); | |
5fafdf24 | 441 | if (NVRAM->type == 8) |
abd0c6bd | 442 | retval = to_bcd(tm.tm_year - 68); // Base year is 1968 |
180b700d | 443 | else |
abd0c6bd | 444 | retval = to_bcd(tm.tm_year); |
a541f297 FB |
445 | break; |
446 | default: | |
13ab5daa | 447 | /* Check lock registers state */ |
819385c5 | 448 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
13ab5daa | 449 | break; |
819385c5 | 450 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
13ab5daa | 451 | break; |
819385c5 FB |
452 | do_read: |
453 | if (addr < NVRAM->size) { | |
454 | retval = NVRAM->buffer[addr]; | |
a541f297 FB |
455 | } |
456 | break; | |
457 | } | |
819385c5 | 458 | if (addr > 0x1FF9 && addr < 0x2000) |
9ed1e667 | 459 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); |
a541f297 FB |
460 | |
461 | return retval; | |
462 | } | |
463 | ||
897b4c6c | 464 | void m48t59_set_addr (void *opaque, uint32_t addr) |
a541f297 | 465 | { |
43a34704 | 466 | M48t59State *NVRAM = opaque; |
897b4c6c | 467 | |
a541f297 FB |
468 | NVRAM->addr = addr; |
469 | } | |
470 | ||
897b4c6c | 471 | void m48t59_toggle_lock (void *opaque, int lock) |
13ab5daa | 472 | { |
43a34704 | 473 | M48t59State *NVRAM = opaque; |
897b4c6c | 474 | |
13ab5daa FB |
475 | NVRAM->lock ^= 1 << lock; |
476 | } | |
477 | ||
a541f297 FB |
478 | /* IO access to NVRAM */ |
479 | static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) | |
480 | { | |
43a34704 | 481 | M48t59State *NVRAM = opaque; |
a541f297 | 482 | |
9ed1e667 | 483 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); |
a541f297 FB |
484 | switch (addr) { |
485 | case 0: | |
486 | NVRAM->addr &= ~0x00FF; | |
487 | NVRAM->addr |= val; | |
488 | break; | |
489 | case 1: | |
490 | NVRAM->addr &= ~0xFF00; | |
491 | NVRAM->addr |= val << 8; | |
492 | break; | |
493 | case 3: | |
819385c5 | 494 | m48t59_write(NVRAM, val, NVRAM->addr); |
a541f297 FB |
495 | NVRAM->addr = 0x0000; |
496 | break; | |
497 | default: | |
498 | break; | |
499 | } | |
500 | } | |
501 | ||
502 | static uint32_t NVRAM_readb (void *opaque, uint32_t addr) | |
503 | { | |
43a34704 | 504 | M48t59State *NVRAM = opaque; |
13ab5daa | 505 | uint32_t retval; |
a541f297 | 506 | |
13ab5daa FB |
507 | switch (addr) { |
508 | case 3: | |
819385c5 | 509 | retval = m48t59_read(NVRAM, NVRAM->addr); |
13ab5daa FB |
510 | break; |
511 | default: | |
512 | retval = -1; | |
513 | break; | |
514 | } | |
9ed1e667 | 515 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); |
a541f297 | 516 | |
13ab5daa | 517 | return retval; |
a541f297 FB |
518 | } |
519 | ||
c227f099 | 520 | static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
e1bb04f7 | 521 | { |
43a34704 | 522 | M48t59State *NVRAM = opaque; |
3b46e624 | 523 | |
819385c5 | 524 | m48t59_write(NVRAM, addr, value & 0xff); |
e1bb04f7 FB |
525 | } |
526 | ||
c227f099 | 527 | static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
e1bb04f7 | 528 | { |
43a34704 | 529 | M48t59State *NVRAM = opaque; |
3b46e624 | 530 | |
819385c5 FB |
531 | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
532 | m48t59_write(NVRAM, addr + 1, value & 0xff); | |
e1bb04f7 FB |
533 | } |
534 | ||
c227f099 | 535 | static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
e1bb04f7 | 536 | { |
43a34704 | 537 | M48t59State *NVRAM = opaque; |
3b46e624 | 538 | |
819385c5 FB |
539 | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
540 | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); | |
541 | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); | |
542 | m48t59_write(NVRAM, addr + 3, value & 0xff); | |
e1bb04f7 FB |
543 | } |
544 | ||
c227f099 | 545 | static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
e1bb04f7 | 546 | { |
43a34704 | 547 | M48t59State *NVRAM = opaque; |
819385c5 | 548 | uint32_t retval; |
3b46e624 | 549 | |
819385c5 | 550 | retval = m48t59_read(NVRAM, addr); |
e1bb04f7 FB |
551 | return retval; |
552 | } | |
553 | ||
c227f099 | 554 | static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
e1bb04f7 | 555 | { |
43a34704 | 556 | M48t59State *NVRAM = opaque; |
819385c5 | 557 | uint32_t retval; |
3b46e624 | 558 | |
819385c5 FB |
559 | retval = m48t59_read(NVRAM, addr) << 8; |
560 | retval |= m48t59_read(NVRAM, addr + 1); | |
e1bb04f7 FB |
561 | return retval; |
562 | } | |
563 | ||
c227f099 | 564 | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
e1bb04f7 | 565 | { |
43a34704 | 566 | M48t59State *NVRAM = opaque; |
819385c5 | 567 | uint32_t retval; |
e1bb04f7 | 568 | |
819385c5 FB |
569 | retval = m48t59_read(NVRAM, addr) << 24; |
570 | retval |= m48t59_read(NVRAM, addr + 1) << 16; | |
571 | retval |= m48t59_read(NVRAM, addr + 2) << 8; | |
572 | retval |= m48t59_read(NVRAM, addr + 3); | |
e1bb04f7 FB |
573 | return retval; |
574 | } | |
575 | ||
d60efc6b | 576 | static CPUWriteMemoryFunc * const nvram_write[] = { |
e1bb04f7 FB |
577 | &nvram_writeb, |
578 | &nvram_writew, | |
579 | &nvram_writel, | |
580 | }; | |
581 | ||
d60efc6b | 582 | static CPUReadMemoryFunc * const nvram_read[] = { |
e1bb04f7 FB |
583 | &nvram_readb, |
584 | &nvram_readw, | |
585 | &nvram_readl, | |
586 | }; | |
819385c5 | 587 | |
fd484ae4 JQ |
588 | static const VMStateDescription vmstate_m48t59 = { |
589 | .name = "m48t59", | |
590 | .version_id = 1, | |
591 | .minimum_version_id = 1, | |
592 | .minimum_version_id_old = 1, | |
593 | .fields = (VMStateField[]) { | |
594 | VMSTATE_UINT8(lock, M48t59State), | |
595 | VMSTATE_UINT16(addr, M48t59State), | |
596 | VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size), | |
597 | VMSTATE_END_OF_LIST() | |
598 | } | |
599 | }; | |
3ccacc4a | 600 | |
43a34704 | 601 | static void m48t59_reset_common(M48t59State *NVRAM) |
3ccacc4a | 602 | { |
6e6b7363 BS |
603 | NVRAM->addr = 0; |
604 | NVRAM->lock = 0; | |
3ccacc4a BS |
605 | if (NVRAM->alrm_timer != NULL) |
606 | qemu_del_timer(NVRAM->alrm_timer); | |
607 | ||
608 | if (NVRAM->wd_timer != NULL) | |
609 | qemu_del_timer(NVRAM->wd_timer); | |
610 | } | |
611 | ||
285e468d BS |
612 | static void m48t59_reset_isa(DeviceState *d) |
613 | { | |
614 | M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev); | |
43a34704 | 615 | M48t59State *NVRAM = &isa->state; |
285e468d BS |
616 | |
617 | m48t59_reset_common(NVRAM); | |
618 | } | |
619 | ||
620 | static void m48t59_reset_sysbus(DeviceState *d) | |
621 | { | |
622 | M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); | |
43a34704 | 623 | M48t59State *NVRAM = &sys->state; |
285e468d BS |
624 | |
625 | m48t59_reset_common(NVRAM); | |
626 | } | |
627 | ||
9936d6e4 RH |
628 | static const MemoryRegionPortio m48t59_portio[] = { |
629 | {0, 4, 1, .read = NVRAM_readb, .write = NVRAM_writeb }, | |
630 | PORTIO_END_OF_LIST(), | |
631 | }; | |
632 | ||
633 | static const MemoryRegionOps m48t59_io_ops = { | |
634 | .old_portio = m48t59_portio, | |
635 | }; | |
636 | ||
a541f297 | 637 | /* Initialisation routine */ |
43a34704 BS |
638 | M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base, |
639 | uint32_t io_base, uint16_t size, int type) | |
a541f297 | 640 | { |
d27cf0ae BS |
641 | DeviceState *dev; |
642 | SysBusDevice *s; | |
f80237d4 | 643 | M48t59SysBusState *d; |
51f9b84e | 644 | M48t59State *state; |
d27cf0ae BS |
645 | |
646 | dev = qdev_create(NULL, "m48t59"); | |
ee6847d1 GH |
647 | qdev_prop_set_uint32(dev, "type", type); |
648 | qdev_prop_set_uint32(dev, "size", size); | |
649 | qdev_prop_set_uint32(dev, "io_base", io_base); | |
e23a1b33 | 650 | qdev_init_nofail(dev); |
d27cf0ae | 651 | s = sysbus_from_qdev(dev); |
51f9b84e HP |
652 | d = FROM_SYSBUS(M48t59SysBusState, s); |
653 | state = &d->state; | |
d27cf0ae | 654 | sysbus_connect_irq(s, 0, IRQ); |
819385c5 | 655 | if (io_base != 0) { |
51f9b84e HP |
656 | register_ioport_read(io_base, 0x04, 1, NVRAM_readb, state); |
657 | register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, state); | |
819385c5 | 658 | } |
e1bb04f7 | 659 | if (mem_base != 0) { |
d27cf0ae | 660 | sysbus_mmio_map(s, 0, mem_base); |
e1bb04f7 | 661 | } |
d27cf0ae | 662 | |
51f9b84e | 663 | return state; |
d27cf0ae BS |
664 | } |
665 | ||
43a34704 | 666 | M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type) |
d27cf0ae | 667 | { |
f80237d4 BS |
668 | M48t59ISAState *d; |
669 | ISADevice *dev; | |
43a34704 | 670 | M48t59State *s; |
f80237d4 BS |
671 | |
672 | dev = isa_create("m48t59_isa"); | |
673 | qdev_prop_set_uint32(&dev->qdev, "type", type); | |
674 | qdev_prop_set_uint32(&dev->qdev, "size", size); | |
675 | qdev_prop_set_uint32(&dev->qdev, "io_base", io_base); | |
e23a1b33 | 676 | qdev_init_nofail(&dev->qdev); |
f80237d4 BS |
677 | d = DO_UPCAST(M48t59ISAState, busdev, dev); |
678 | s = &d->state; | |
d27cf0ae | 679 | |
9936d6e4 | 680 | memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); |
f80237d4 | 681 | if (io_base != 0) { |
9936d6e4 | 682 | isa_register_ioport(dev, &d->io, io_base); |
f80237d4 | 683 | } |
d27cf0ae | 684 | |
f80237d4 BS |
685 | return s; |
686 | } | |
d27cf0ae | 687 | |
43a34704 | 688 | static void m48t59_init_common(M48t59State *s) |
f80237d4 | 689 | { |
7267c094 | 690 | s->buffer = g_malloc0(s->size); |
d27cf0ae | 691 | if (s->type == 59) { |
74475455 PB |
692 | s->alrm_timer = qemu_new_timer_ns(vm_clock, &alarm_cb, s); |
693 | s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s); | |
819385c5 | 694 | } |
f6503059 | 695 | qemu_get_timedate(&s->alarm, 0); |
13ab5daa | 696 | |
fd484ae4 | 697 | vmstate_register(NULL, -1, &vmstate_m48t59, s); |
f80237d4 BS |
698 | } |
699 | ||
700 | static int m48t59_init_isa1(ISADevice *dev) | |
701 | { | |
702 | M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); | |
43a34704 | 703 | M48t59State *s = &d->state; |
f80237d4 BS |
704 | |
705 | isa_init_irq(dev, &s->IRQ, 8); | |
706 | m48t59_init_common(s); | |
707 | ||
81a322d4 | 708 | return 0; |
d27cf0ae | 709 | } |
3ccacc4a | 710 | |
f80237d4 BS |
711 | static int m48t59_init1(SysBusDevice *dev) |
712 | { | |
713 | M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); | |
43a34704 | 714 | M48t59State *s = &d->state; |
f80237d4 BS |
715 | int mem_index; |
716 | ||
717 | sysbus_init_irq(dev, &s->IRQ); | |
718 | ||
2507c12a AG |
719 | mem_index = cpu_register_io_memory(nvram_read, nvram_write, s, |
720 | DEVICE_NATIVE_ENDIAN); | |
f80237d4 BS |
721 | sysbus_init_mmio(dev, s->size, mem_index); |
722 | m48t59_init_common(s); | |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
727 | static ISADeviceInfo m48t59_isa_info = { | |
728 | .init = m48t59_init_isa1, | |
729 | .qdev.name = "m48t59_isa", | |
730 | .qdev.size = sizeof(M48t59ISAState), | |
285e468d | 731 | .qdev.reset = m48t59_reset_isa, |
f80237d4 BS |
732 | .qdev.no_user = 1, |
733 | .qdev.props = (Property[]) { | |
734 | DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), | |
735 | DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1), | |
736 | DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), | |
737 | DEFINE_PROP_END_OF_LIST(), | |
738 | } | |
739 | }; | |
740 | ||
ee6847d1 GH |
741 | static SysBusDeviceInfo m48t59_info = { |
742 | .init = m48t59_init1, | |
743 | .qdev.name = "m48t59", | |
f80237d4 | 744 | .qdev.size = sizeof(M48t59SysBusState), |
285e468d | 745 | .qdev.reset = m48t59_reset_sysbus, |
ee6847d1 | 746 | .qdev.props = (Property[]) { |
f80237d4 BS |
747 | DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), |
748 | DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1), | |
749 | DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), | |
01274424 | 750 | DEFINE_PROP_END_OF_LIST(), |
ee6847d1 GH |
751 | } |
752 | }; | |
753 | ||
d27cf0ae BS |
754 | static void m48t59_register_devices(void) |
755 | { | |
ee6847d1 | 756 | sysbus_register_withprop(&m48t59_info); |
f80237d4 | 757 | isa_qdev_register(&m48t59_isa_info); |
a541f297 | 758 | } |
d27cf0ae BS |
759 | |
760 | device_init(m48t59_register_devices) |