[mirror_qemu.git] / hw / m48t59.c

/*
 * QEMU M48T59 NVRAM emulation for PPC PREP platform
 * 
 * Copyright (c) 2003-2004 Jocelyn Mayer
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
#include "m48t59.h"

//#define DEBUG_NVRAM

#if defined(DEBUG_NVRAM)
#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
#else
#define NVRAM_PRINTF(fmt, args...) do { } while (0)
#endif

struct m48t59_t {
    /* Hardware parameters */
    int      IRQ;
    uint32_t io_base;
    uint16_t size;
    /* RTC management */
    time_t   time_offset;
    time_t   stop_time;
    /* Alarm & watchdog */
    time_t   alarm;
    struct QEMUTimer *alrm_timer;
    struct QEMUTimer *wd_timer;
    /* NVRAM storage */
    uint8_t  lock;
    uint16_t addr;
    uint8_t *buffer;
};

/* Fake timer functions */
/* Generic helpers for BCD */
static inline uint8_t toBCD (uint8_t value)
{
    return (((value / 10) % 10) << 4) | (value % 10);
}

static inline uint8_t fromBCD (uint8_t BCD)
{
    return ((BCD >> 4) * 10) + (BCD & 0x0F);
}

/* RTC management helpers */
static void get_time (m48t59_t *NVRAM, struct tm *tm)
{
    time_t t;

    t = time(NULL) + NVRAM->time_offset;
#ifdef _WIN32
    memcpy(tm,localtime(&t),sizeof(*tm));
#else
    localtime_r (&t, tm) ;
#endif
}

static void set_time (m48t59_t *NVRAM, struct tm *tm)
{
    time_t now, new_time;
    
    new_time = mktime(tm);
    now = time(NULL);
    NVRAM->time_offset = new_time - now;
}

/* Alarm management */
static void alarm_cb (void *opaque)
{
    struct tm tm, tm_now;
    uint64_t next_time;
    m48t59_t *NVRAM = opaque;

    pic_set_irq(NVRAM->IRQ, 1);
    if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && 
	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	/* Repeat once a month */
	get_time(NVRAM, &tm_now);
	memcpy(&tm, &tm_now, sizeof(struct tm));
	tm.tm_mon++;
	if (tm.tm_mon == 13) {
	    tm.tm_mon = 1;
	    tm.tm_year++;
	}
	next_time = mktime(&tm);
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	       (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	/* Repeat once a day */
	next_time = 24 * 60 * 60 + mktime(&tm_now);
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	/* Repeat once an hour */
	next_time = 60 * 60 + mktime(&tm_now);
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	/* Repeat once a minute */
	next_time = 60 + mktime(&tm_now);
    } else {
	/* Repeat once a second */
	next_time = 1 + mktime(&tm_now);
    }
    qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
    pic_set_irq(NVRAM->IRQ, 0);
}


static void get_alarm (m48t59_t *NVRAM, struct tm *tm)
{
#ifdef _WIN32
    memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
#else
    localtime_r (&NVRAM->alarm, tm);
#endif
}

static void set_alarm (m48t59_t *NVRAM, struct tm *tm)
{
    NVRAM->alarm = mktime(tm);
    if (NVRAM->alrm_timer != NULL) {
        qemu_del_timer(NVRAM->alrm_timer);
	NVRAM->alrm_timer = NULL;
    }
    if (NVRAM->alarm - time(NULL) > 0)
	qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
}

/* Watchdog management */
static void watchdog_cb (void *opaque)
{
    m48t59_t *NVRAM = opaque;

    NVRAM->buffer[0x1FF0] |= 0x80;
    if (NVRAM->buffer[0x1FF7] & 0x80) {
	NVRAM->buffer[0x1FF7] = 0x00;
	NVRAM->buffer[0x1FFC] &= ~0x40;
        /* May it be a hw CPU Reset instead ? */
        qemu_system_reset_request();
    } else {
	pic_set_irq(NVRAM->IRQ, 1);
	pic_set_irq(NVRAM->IRQ, 0);
    }
}

static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
{
    uint64_t interval; /* in 1/16 seconds */

    if (NVRAM->wd_timer != NULL) {
        qemu_del_timer(NVRAM->wd_timer);
	NVRAM->wd_timer = NULL;
    }
    NVRAM->buffer[0x1FF0] &= ~0x80;
    if (value != 0) {
	interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
	qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
		       ((interval * 1000) >> 4));
    }
}

/* Direct access to NVRAM */
void m48t59_write (m48t59_t *NVRAM, uint32_t val)
{
    struct tm tm;
    int tmp;

    if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000)
	NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
    switch (NVRAM->addr) {
    case 0x1FF0:
        /* flags register : read-only */
        break;
    case 0x1FF1:
        /* unused */
        break;
    case 0x1FF2:
        /* alarm seconds */
	tmp = fromBCD(val & 0x7F);
	if (tmp >= 0 && tmp <= 59) {
	    get_alarm(NVRAM, &tm);
	    tm.tm_sec = tmp;
	    NVRAM->buffer[0x1FF2] = val;
	    set_alarm(NVRAM, &tm);
	}
        break;
    case 0x1FF3:
        /* alarm minutes */
	tmp = fromBCD(val & 0x7F);
	if (tmp >= 0 && tmp <= 59) {
	    get_alarm(NVRAM, &tm);
	    tm.tm_min = tmp;
	    NVRAM->buffer[0x1FF3] = val;
	    set_alarm(NVRAM, &tm);
	}
        break;
    case 0x1FF4:
        /* alarm hours */
	tmp = fromBCD(val & 0x3F);
	if (tmp >= 0 && tmp <= 23) {
	    get_alarm(NVRAM, &tm);
	    tm.tm_hour = tmp;
	    NVRAM->buffer[0x1FF4] = val;
	    set_alarm(NVRAM, &tm);
	}
        break;
    case 0x1FF5:
        /* alarm date */
	tmp = fromBCD(val & 0x1F);
	if (tmp != 0) {
	    get_alarm(NVRAM, &tm);
	    tm.tm_mday = tmp;
	    NVRAM->buffer[0x1FF5] = val;
	    set_alarm(NVRAM, &tm);
	}
        break;
    case 0x1FF6:
        /* interrupts */
	NVRAM->buffer[0x1FF6] = val;
        break;
    case 0x1FF7:
        /* watchdog */
	NVRAM->buffer[0x1FF7] = val;
	set_up_watchdog(NVRAM, val);
        break;
    case 0x1FF8:
        /* control */
	NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90;
        break;
    case 0x1FF9:
        /* seconds (BCD) */
	tmp = fromBCD(val & 0x7F);
	if (tmp >= 0 && tmp <= 59) {
	    get_time(NVRAM, &tm);
	    tm.tm_sec = tmp;
	    set_time(NVRAM, &tm);
	}
	if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
	    if (val & 0x80) {
		NVRAM->stop_time = time(NULL);
	    } else {
		NVRAM->time_offset += NVRAM->stop_time - time(NULL);
		NVRAM->stop_time = 0;
	    }
	}
	NVRAM->buffer[0x1FF9] = val & 0x80;
        break;
    case 0x1FFA:
        /* minutes (BCD) */
	tmp = fromBCD(val & 0x7F);
	if (tmp >= 0 && tmp <= 59) {
	    get_time(NVRAM, &tm);
	    tm.tm_min = tmp;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFB:
        /* hours (BCD) */
	tmp = fromBCD(val & 0x3F);
	if (tmp >= 0 && tmp <= 23) {
	    get_time(NVRAM, &tm);
	    tm.tm_hour = tmp;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFC:
        /* day of the week / century */
	tmp = fromBCD(val & 0x07);
	get_time(NVRAM, &tm);
	tm.tm_wday = tmp;
	set_time(NVRAM, &tm);
        NVRAM->buffer[0x1FFC] = val & 0x40;
        break;
    case 0x1FFD:
        /* date */
	tmp = fromBCD(val & 0x1F);
	if (tmp != 0) {
	    get_time(NVRAM, &tm);
	    tm.tm_mday = tmp;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFE:
        /* month */
	tmp = fromBCD(val & 0x1F);
	if (tmp >= 1 && tmp <= 12) {
	    get_time(NVRAM, &tm);
	    tm.tm_mon = tmp - 1;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFF:
        /* year */
	tmp = fromBCD(val);
	if (tmp >= 0 && tmp <= 99) {
	    get_time(NVRAM, &tm);
	    tm.tm_year = fromBCD(val);
	    set_time(NVRAM, &tm);
	}
        break;
    default:
        /* Check lock registers state */
        if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
            break;
        if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
            break;
        if (NVRAM->addr < 0x1FF0 ||
	    (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
            NVRAM->buffer[NVRAM->addr] = val & 0xFF;
	}
        break;
    }
}

uint32_t m48t59_read (m48t59_t *NVRAM)
{
    struct tm tm;
    uint32_t retval = 0xFF;

    switch (NVRAM->addr) {
    case 0x1FF0:
        /* flags register */
	goto do_read;
    case 0x1FF1:
        /* unused */
	retval = 0;
        break;
    case 0x1FF2:
        /* alarm seconds */
	goto do_read;
    case 0x1FF3:
        /* alarm minutes */
	goto do_read;
    case 0x1FF4:
        /* alarm hours */
	goto do_read;
    case 0x1FF5:
        /* alarm date */
	goto do_read;
    case 0x1FF6:
        /* interrupts */
	goto do_read;
    case 0x1FF7:
	/* A read resets the watchdog */
	set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
	goto do_read;
    case 0x1FF8:
        /* control */
	goto do_read;
    case 0x1FF9:
        /* seconds (BCD) */
        get_time(NVRAM, &tm);
        retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec);
        break;
    case 0x1FFA:
        /* minutes (BCD) */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_min);
        break;
    case 0x1FFB:
        /* hours (BCD) */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_hour);
        break;
    case 0x1FFC:
        /* day of the week / century */
        get_time(NVRAM, &tm);
        retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
        break;
    case 0x1FFD:
        /* date */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_mday);
        break;
    case 0x1FFE:
        /* month */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_mon + 1);
        break;
    case 0x1FFF:
        /* year */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_year);
        break;
    default:
        /* Check lock registers state */
        if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
            break;
        if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
            break;
        if (NVRAM->addr < 0x1FF0 ||
	    (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
	do_read:
            retval = NVRAM->buffer[NVRAM->addr];
	}
        break;
    }
    if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000)
	NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);

    return retval;
}

void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr)
{
    NVRAM->addr = addr;
}

void m48t59_toggle_lock (m48t59_t *NVRAM, int lock)
{
    NVRAM->lock ^= 1 << lock;
}

/* IO access to NVRAM */
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
{
    m48t59_t *NVRAM = opaque;

    addr -= NVRAM->io_base;
    NVRAM_PRINTF("0x%08x => 0x%08x\n", addr, val);
    switch (addr) {
    case 0:
        NVRAM->addr &= ~0x00FF;
        NVRAM->addr |= val;
        break;
    case 1:
        NVRAM->addr &= ~0xFF00;
        NVRAM->addr |= val << 8;
        break;
    case 3:
        m48t59_write(NVRAM, val);
        NVRAM->addr = 0x0000;
        break;
    default:
        break;
    }
}

static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    addr -= NVRAM->io_base;
    switch (addr) {
    case 3:
        retval = m48t59_read(NVRAM);
        break;
    default:
        retval = -1;
        break;
    }
    NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);

    return retval;
}

/* Initialisation routine */
m48t59_t *m48t59_init (int IRQ, uint32_t io_base, uint16_t size)
{
    m48t59_t *s;

    s = qemu_mallocz(sizeof(m48t59_t));
    if (!s)
	return NULL;
    s->buffer = qemu_mallocz(size);
    if (!s->buffer) {
        qemu_free(s);
        return NULL;
    }
    s->IRQ = IRQ;
    s->size = size;
    s->io_base = io_base;
    s->addr = 0;
    register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
    register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
    s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
    s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
    s->lock = 0;

    return s;
}
Commit	Line	Data
a541f297 FB	1	/*
	2	* QEMU M48T59 NVRAM emulation for PPC PREP platform
	3	*
	4	* Copyright (c) 2003-2004 Jocelyn Mayer
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
a541f297	24	#include "vl.h"
c5df018e	25	#include "m48t59.h"
a541f297	26
13ab5daa	27	//#define DEBUG_NVRAM
a541f297	28
13ab5daa	29	#if defined(DEBUG_NVRAM)
a541f297 FB	30	#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
	31	#else
	32	#define NVRAM_PRINTF(fmt, args...) do { } while (0)
	33	#endif
	34
c5df018e	35	struct m48t59_t {
a541f297 FB	36	/* Hardware parameters */
	37	int IRQ;
	38	uint32_t io_base;
	39	uint16_t size;
	40	/* RTC management */
	41	time_t time_offset;
	42	time_t stop_time;
	43	/* Alarm & watchdog */
	44	time_t alarm;
	45	struct QEMUTimer *alrm_timer;
	46	struct QEMUTimer *wd_timer;
	47	/* NVRAM storage */
13ab5daa	48	uint8_t lock;
a541f297 FB	49	uint16_t addr;
a541f297 FB	50	uint8_t *buffer;
c5df018e	51	};
a541f297 FB	52
	53	/* Fake timer functions */
	54	/* Generic helpers for BCD */
	55	static inline uint8_t toBCD (uint8_t value)
	56	{
	57	return (((value / 10) % 10) << 4) \| (value % 10);
	58	}
	59
	60	static inline uint8_t fromBCD (uint8_t BCD)
	61	{
	62	return ((BCD >> 4) * 10) + (BCD & 0x0F);
	63	}
	64
	65	/* RTC management helpers */
	66	static void get_time (m48t59_t NVRAM, struct tm tm)
	67	{
	68	time_t t;
	69
	70	t = time(NULL) + NVRAM->time_offset;
d157e205 FB	71	#ifdef _WIN32
	72	memcpy(tm,localtime(&t),sizeof(*tm));
	73	#else
	74	localtime_r (&t, tm) ;
	75	#endif
a541f297 FB	76	}
	77
	78	static void set_time (m48t59_t NVRAM, struct tm tm)
	79	{
	80	time_t now, new_time;
	81
	82	new_time = mktime(tm);
	83	now = time(NULL);
	84	NVRAM->time_offset = new_time - now;
	85	}
	86
	87	/* Alarm management */
	88	static void alarm_cb (void *opaque)
	89	{
	90	struct tm tm, tm_now;
	91	uint64_t next_time;
	92	m48t59_t *NVRAM = opaque;
	93
	94	pic_set_irq(NVRAM->IRQ, 1);
	95	if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
	96	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	97	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	98	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	99	/* Repeat once a month */
	100	get_time(NVRAM, &tm_now);
	101	memcpy(&tm, &tm_now, sizeof(struct tm));
	102	tm.tm_mon++;
	103	if (tm.tm_mon == 13) {
	104	tm.tm_mon = 1;
	105	tm.tm_year++;
	106	}
	107	next_time = mktime(&tm);
	108	} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	109	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	110	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	111	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	112	/* Repeat once a day */
	113	next_time = 24 * 60 * 60 + mktime(&tm_now);
	114	} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	115	(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	116	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	117	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	118	/* Repeat once an hour */
	119	next_time = 60 * 60 + mktime(&tm_now);
	120	} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	121	(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	122	(NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
	123	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	124	/* Repeat once a minute */
	125	next_time = 60 + mktime(&tm_now);
	126	} else {
	127	/* Repeat once a second */
	128	next_time = 1 + mktime(&tm_now);
	129	}
	130	qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
	131	pic_set_irq(NVRAM->IRQ, 0);
	132	}
	133
	134
	135	static void get_alarm (m48t59_t NVRAM, struct tm tm)
	136	{
d157e205 FB	137	#ifdef _WIN32
	138	memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
	139	#else
	140	localtime_r (&NVRAM->alarm, tm);
	141	#endif
a541f297 FB	142	}
	143
	144	static void set_alarm (m48t59_t NVRAM, struct tm tm)
	145	{
	146	NVRAM->alarm = mktime(tm);
	147	if (NVRAM->alrm_timer != NULL) {
	148	qemu_del_timer(NVRAM->alrm_timer);
	149	NVRAM->alrm_timer = NULL;
	150	}
	151	if (NVRAM->alarm - time(NULL) > 0)
	152	qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
	153	}
	154
	155	/* Watchdog management */
	156	static void watchdog_cb (void *opaque)
	157	{
	158	m48t59_t *NVRAM = opaque;
	159
	160	NVRAM->buffer[0x1FF0] \|= 0x80;
	161	if (NVRAM->buffer[0x1FF7] & 0x80) {
	162	NVRAM->buffer[0x1FF7] = 0x00;
	163	NVRAM->buffer[0x1FFC] &= ~0x40;
13ab5daa	164	/* May it be a hw CPU Reset instead ? */
d7d02e3c	165	qemu_system_reset_request();
a541f297 FB	166	} else {
	167	pic_set_irq(NVRAM->IRQ, 1);
	168	pic_set_irq(NVRAM->IRQ, 0);
	169	}
	170	}
	171
	172	static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
	173	{
	174	uint64_t interval; /* in 1/16 seconds */
	175
	176	if (NVRAM->wd_timer != NULL) {
	177	qemu_del_timer(NVRAM->wd_timer);
	178	NVRAM->wd_timer = NULL;
	179	}
	180	NVRAM->buffer[0x1FF0] &= ~0x80;
	181	if (value != 0) {
	182	interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
	183	qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
	184	((interval * 1000) >> 4));
	185	}
	186	}
	187
	188	/* Direct access to NVRAM */
c5df018e	189	void m48t59_write (m48t59_t *NVRAM, uint32_t val)
a541f297	190	{
a541f297 FB	191	struct tm tm;
	192	int tmp;
	193
	194	if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000)
	195	NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
	196	switch (NVRAM->addr) {
	197	case 0x1FF0:
	198	/* flags register : read-only */
	199	break;
	200	case 0x1FF1:
	201	/* unused */
	202	break;
	203	case 0x1FF2:
	204	/* alarm seconds */
	205	tmp = fromBCD(val & 0x7F);
	206	if (tmp >= 0 && tmp <= 59) {
	207	get_alarm(NVRAM, &tm);
	208	tm.tm_sec = tmp;
	209	NVRAM->buffer[0x1FF2] = val;
	210	set_alarm(NVRAM, &tm);
	211	}
	212	break;
	213	case 0x1FF3:
	214	/* alarm minutes */
	215	tmp = fromBCD(val & 0x7F);
	216	if (tmp >= 0 && tmp <= 59) {
	217	get_alarm(NVRAM, &tm);
	218	tm.tm_min = tmp;
	219	NVRAM->buffer[0x1FF3] = val;
	220	set_alarm(NVRAM, &tm);
	221	}
	222	break;
	223	case 0x1FF4:
	224	/* alarm hours */
	225	tmp = fromBCD(val & 0x3F);
	226	if (tmp >= 0 && tmp <= 23) {
	227	get_alarm(NVRAM, &tm);
	228	tm.tm_hour = tmp;
	229	NVRAM->buffer[0x1FF4] = val;
	230	set_alarm(NVRAM, &tm);
	231	}
	232	break;
	233	case 0x1FF5:
	234	/* alarm date */
	235	tmp = fromBCD(val & 0x1F);
	236	if (tmp != 0) {
	237	get_alarm(NVRAM, &tm);
	238	tm.tm_mday = tmp;
	239	NVRAM->buffer[0x1FF5] = val;
	240	set_alarm(NVRAM, &tm);
	241	}
	242	break;
	243	case 0x1FF6:
	244	/* interrupts */
	245	NVRAM->buffer[0x1FF6] = val;
	246	break;
	247	case 0x1FF7:
	248	/* watchdog */
	249	NVRAM->buffer[0x1FF7] = val;
	250	set_up_watchdog(NVRAM, val);
	251	break;
	252	case 0x1FF8:
	253	/* control */
	254	NVRAM->buffer[0x1FF8] = (val & ~0xA0) \| 0x90;
255	break;
256	case 0x1FF9:
257	/* seconds (BCD) */
258	tmp = fromBCD(val & 0x7F);
259	if (tmp >= 0 && tmp <= 59) {
260	get_time(NVRAM, &tm);
261	tm.tm_sec = tmp;
262	set_time(NVRAM, &tm);
263	}
264	if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
265	if (val & 0x80) {
266	NVRAM->stop_time = time(NULL);
267	} else {
268	NVRAM->time_offset += NVRAM->stop_time - time(NULL);
269	NVRAM->stop_time = 0;
270	}
271	}
272	NVRAM->buffer[0x1FF9] = val & 0x80;
273	break;
274	case 0x1FFA:
275	/* minutes (BCD) */
276	tmp = fromBCD(val & 0x7F);
277	if (tmp >= 0 && tmp <= 59) {
278	get_time(NVRAM, &tm);
279	tm.tm_min = tmp;
280	set_time(NVRAM, &tm);
281	}
282	break;
283	case 0x1FFB:
284	/* hours (BCD) */
285	tmp = fromBCD(val & 0x3F);
286	if (tmp >= 0 && tmp <= 23) {
287	get_time(NVRAM, &tm);
288	tm.tm_hour = tmp;
289	set_time(NVRAM, &tm);
290	}
291	break;
292	case 0x1FFC:
293	/* day of the week / century */
294	tmp = fromBCD(val & 0x07);
295	get_time(NVRAM, &tm);
296	tm.tm_wday = tmp;
297	set_time(NVRAM, &tm);
298	NVRAM->buffer[0x1FFC] = val & 0x40;
299	break;
300	case 0x1FFD:
301	/* date */
302	tmp = fromBCD(val & 0x1F);
303	if (tmp != 0) {
304	get_time(NVRAM, &tm);
305	tm.tm_mday = tmp;
306	set_time(NVRAM, &tm);
307	}
308	break;
309	case 0x1FFE:
310	/* month */
311	tmp = fromBCD(val & 0x1F);
312	if (tmp >= 1 && tmp <= 12) {
313	get_time(NVRAM, &tm);
314	tm.tm_mon = tmp - 1;
315	set_time(NVRAM, &tm);
316	}
317	break;
318	case 0x1FFF:
319	/* year */
320	tmp = fromBCD(val);
321	if (tmp >= 0 && tmp <= 99) {
322	get_time(NVRAM, &tm);
323	tm.tm_year = fromBCD(val);
324	set_time(NVRAM, &tm);
325	}
326	break;
327	default:
13ab5daa FB	328	/* Check lock registers state */
	329	if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
	330	break;
	331	if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
	332	break;
a541f297 FB	333	if (NVRAM->addr < 0x1FF0 \|\|
	334	(NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
	335	NVRAM->buffer[NVRAM->addr] = val & 0xFF;
	336	}
	337	break;
	338	}
	339	}
	340
c5df018e	341	uint32_t m48t59_read (m48t59_t *NVRAM)
a541f297	342	{
a541f297 FB	343	struct tm tm;
	344	uint32_t retval = 0xFF;
	345
	346	switch (NVRAM->addr) {
	347	case 0x1FF0:
	348	/* flags register */
	349	goto do_read;
	350	case 0x1FF1:
	351	/* unused */
	352	retval = 0;
	353	break;
	354	case 0x1FF2:
	355	/* alarm seconds */
	356	goto do_read;
	357	case 0x1FF3:
	358	/* alarm minutes */
	359	goto do_read;
	360	case 0x1FF4:
	361	/* alarm hours */
	362	goto do_read;
	363	case 0x1FF5:
	364	/* alarm date */
	365	goto do_read;
	366	case 0x1FF6:
	367	/* interrupts */
	368	goto do_read;
	369	case 0x1FF7:
	370	/* A read resets the watchdog */
	371	set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
	372	goto do_read;
	373	case 0x1FF8:
	374	/* control */
	375	goto do_read;
	376	case 0x1FF9:
	377	/* seconds (BCD) */
	378	get_time(NVRAM, &tm);
	379	retval = (NVRAM->buffer[0x1FF9] & 0x80) \| toBCD(tm.tm_sec);
	380	break;
	381	case 0x1FFA:
	382	/* minutes (BCD) */
	383	get_time(NVRAM, &tm);
	384	retval = toBCD(tm.tm_min);
	385	break;
	386	case 0x1FFB:
	387	/* hours (BCD) */
	388	get_time(NVRAM, &tm);
	389	retval = toBCD(tm.tm_hour);
	390	break;
	391	case 0x1FFC:
	392	/* day of the week / century */
	393	get_time(NVRAM, &tm);
	394	retval = NVRAM->buffer[0x1FFC] \| tm.tm_wday;
	395	break;
	396	case 0x1FFD:
	397	/* date */
	398	get_time(NVRAM, &tm);
	399	retval = toBCD(tm.tm_mday);
	400	break;
	401	case 0x1FFE:
	402	/* month */
	403	get_time(NVRAM, &tm);
	404	retval = toBCD(tm.tm_mon + 1);
	405	break;
	406	case 0x1FFF:
407	/* year */
408	get_time(NVRAM, &tm);
409	retval = toBCD(tm.tm_year);
410	break;
411	default:
13ab5daa FB	412	/* Check lock registers state */
	413	if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
	414	break;
	415	if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
	416	break;
a541f297 FB	417	if (NVRAM->addr < 0x1FF0 \|\|
	418	(NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
	419	do_read:
	420	retval = NVRAM->buffer[NVRAM->addr];
	421	}
	422	break;
	423	}
	424	if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000)
	425	NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);
	426
	427	return retval;
	428	}
	429
c5df018e	430	void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr)
a541f297	431	{
a541f297 FB	432	NVRAM->addr = addr;
	433	}
	434
13ab5daa FB	435	void m48t59_toggle_lock (m48t59_t *NVRAM, int lock)
	436	{
	437	NVRAM->lock ^= 1 << lock;
	438	}
	439
a541f297 FB	440	/* IO access to NVRAM */
	441	static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
	442	{
	443	m48t59_t *NVRAM = opaque;
	444
	445	addr -= NVRAM->io_base;
13ab5daa	446	NVRAM_PRINTF("0x%08x => 0x%08x\n", addr, val);
a541f297 FB	447	switch (addr) {
	448	case 0:
	449	NVRAM->addr &= ~0x00FF;
	450	NVRAM->addr \|= val;
	451	break;
	452	case 1:
	453	NVRAM->addr &= ~0xFF00;
	454	NVRAM->addr \|= val << 8;
	455	break;
	456	case 3:
	457	m48t59_write(NVRAM, val);
	458	NVRAM->addr = 0x0000;
	459	break;
	460	default:
	461	break;
	462	}
	463	}
	464
	465	static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
	466	{
	467	m48t59_t *NVRAM = opaque;
13ab5daa	468	uint32_t retval;
a541f297	469
13ab5daa FB	470	addr -= NVRAM->io_base;
	471	switch (addr) {
	472	case 3:
	473	retval = m48t59_read(NVRAM);
	474	break;
	475	default:
	476	retval = -1;
	477	break;
	478	}
	479	NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
a541f297	480
13ab5daa	481	return retval;
a541f297 FB	482	}
	483
	484	/* Initialisation routine */
c5df018e	485	m48t59_t *m48t59_init (int IRQ, uint32_t io_base, uint16_t size)
a541f297	486	{
c5df018e	487	m48t59_t *s;
a541f297	488
c5df018e FB	489	s = qemu_mallocz(sizeof(m48t59_t));
c5df018e FB	490	if (!s)
a541f297	491	return NULL;
c5df018e FB	492	s->buffer = qemu_mallocz(size);
	493	if (!s->buffer) {
	494	qemu_free(s);
	495	return NULL;
	496	}
	497	s->IRQ = IRQ;
	498	s->size = size;
	499	s->io_base = io_base;
	500	s->addr = 0;
	501	register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
	502	register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
	503	s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
	504	s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
13ab5daa FB	505	s->lock = 0;
13ab5daa FB	506
c5df018e	507	return s;
a541f297	508	}