[mirror_qemu.git] / hw / m68k / mcf5208.c

/*
 * Motorola ColdFire MCF5208 SoC emulation.
 *
 * Copyright (c) 2007 CodeSourcery.
 *
 * This code is licensed under the GPL
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/irq.h"
#include "hw/m68k/mcf.h"
#include "hw/m68k/mcf_fec.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
#include "net/net.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "elf.h"

#define SYS_FREQ 166666666

#define ROM_SIZE 0x200000

#define PCSR_EN         0x0001
#define PCSR_RLD        0x0002
#define PCSR_PIF        0x0004
#define PCSR_PIE        0x0008
#define PCSR_OVW        0x0010
#define PCSR_DBG        0x0020
#define PCSR_DOZE       0x0040
#define PCSR_PRE_SHIFT  8
#define PCSR_PRE_MASK   0x0f00

typedef struct {
    MemoryRegion iomem;
    qemu_irq irq;
    ptimer_state *timer;
    uint16_t pcsr;
    uint16_t pmr;
    uint16_t pcntr;
} m5208_timer_state;

static void m5208_timer_update(m5208_timer_state *s)
{
    if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void m5208_timer_write(void *opaque, hwaddr offset,
                              uint64_t value, unsigned size)
{
    m5208_timer_state *s = (m5208_timer_state *)opaque;
    int prescale;
    int limit;
    switch (offset) {
    case 0:
        /* The PIF bit is set-to-clear.  */
        if (value & PCSR_PIF) {
            s->pcsr &= ~PCSR_PIF;
            value &= ~PCSR_PIF;
        }
        /* Avoid frobbing the timer if we're just twiddling IRQ bits. */
        if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) {
            s->pcsr = value;
            m5208_timer_update(s);
            return;
        }

        ptimer_transaction_begin(s->timer);
        if (s->pcsr & PCSR_EN)
            ptimer_stop(s->timer);

        s->pcsr = value;

        prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
        ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
        if (s->pcsr & PCSR_RLD)
            limit = s->pmr;
        else
            limit = 0xffff;
        ptimer_set_limit(s->timer, limit, 0);

        if (s->pcsr & PCSR_EN)
            ptimer_run(s->timer, 0);
        ptimer_transaction_commit(s->timer);
        break;
    case 2:
        ptimer_transaction_begin(s->timer);
        s->pmr = value;
        s->pcsr &= ~PCSR_PIF;
        if ((s->pcsr & PCSR_RLD) == 0) {
            if (s->pcsr & PCSR_OVW)
                ptimer_set_count(s->timer, value);
        } else {
            ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
        }
        ptimer_transaction_commit(s->timer);
        break;
    case 4:
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
                      __func__, offset);
        return;
    }
    m5208_timer_update(s);
}

static void m5208_timer_trigger(void *opaque)
{
    m5208_timer_state *s = (m5208_timer_state *)opaque;
    s->pcsr |= PCSR_PIF;
    m5208_timer_update(s);
}

static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
                                 unsigned size)
{
    m5208_timer_state *s = (m5208_timer_state *)opaque;
    switch (addr) {
    case 0:
        return s->pcsr;
    case 2:
        return s->pmr;
    case 4:
        return ptimer_get_count(s->timer);
    default:
        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
                      __func__, addr);
        return 0;
    }
}

static const MemoryRegionOps m5208_timer_ops = {
    .read = m5208_timer_read,
    .write = m5208_timer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
                               unsigned size)
{
    switch (addr) {
    case 0x110: /* SDCS0 */
        {
            int n;
            for (n = 0; n < 32; n++) {
                if (current_machine->ram_size < (2u << n)) {
                    break;
                }
            }
            return (n - 1)  | 0x40000000;
        }
    case 0x114: /* SDCS1 */
        return 0;

    default:
        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
                      __func__, addr);
        return 0;
    }
}

static void m5208_sys_write(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size)
{
    qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
                  __func__, addr);
}

static const MemoryRegionOps m5208_sys_ops = {
    .read = m5208_sys_read,
    .write = m5208_sys_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
{
    MemoryRegion *iomem = g_new(MemoryRegion, 1);
    m5208_timer_state *s;
    int i;

    /* SDRAMC.  */
    memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
    memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
    /* Timers.  */
    for (i = 0; i < 2; i++) {
        s = g_new0(m5208_timer_state, 1);
        s->timer = ptimer_init(m5208_timer_trigger, s, PTIMER_POLICY_DEFAULT);
        memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s,
                              "m5208-timer", 0x00004000);
        memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
                                    &s->iomem);
        s->irq = pic[4 + i];
    }
}

static void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd, hwaddr base,
                         qemu_irq *irqs)
{
    DeviceState *dev;
    SysBusDevice *s;
    int i;

    qemu_check_nic_model(nd, TYPE_MCF_FEC_NET);
    dev = qdev_new(TYPE_MCF_FEC_NET);
    qdev_set_nic_properties(dev, nd);

    s = SYS_BUS_DEVICE(dev);
    sysbus_realize_and_unref(s, &error_fatal);
    for (i = 0; i < FEC_NUM_IRQ; i++) {
        sysbus_connect_irq(s, i, irqs[i]);
    }

    memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(s, 0));
}

static void mcf5208evb_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *kernel_filename = machine->kernel_filename;
    M68kCPU *cpu;
    CPUM68KState *env;
    int kernel_size;
    uint64_t elf_entry;
    hwaddr entry;
    qemu_irq *pic;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *rom = g_new(MemoryRegion, 1);
    MemoryRegion *sram = g_new(MemoryRegion, 1);

    cpu = M68K_CPU(cpu_create(machine->cpu_type));
    env = &cpu->env;

    /* Initialize CPU registers.  */
    env->vbr = 0;
    /* TODO: Configure BARs.  */

    /* ROM at 0x00000000 */
    memory_region_init_rom(rom, NULL, "mcf5208.rom", ROM_SIZE, &error_fatal);
    memory_region_add_subregion(address_space_mem, 0x00000000, rom);

    /* DRAM at 0x40000000 */
    memory_region_add_subregion(address_space_mem, 0x40000000, machine->ram);

    /* Internal SRAM.  */
    memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal);
    memory_region_add_subregion(address_space_mem, 0x80000000, sram);

    /* Internal peripherals.  */
    pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu);

    mcf_uart_mm_init(0xfc060000, pic[26], serial_hd(0));
    mcf_uart_mm_init(0xfc064000, pic[27], serial_hd(1));
    mcf_uart_mm_init(0xfc068000, pic[28], serial_hd(2));

    mcf5208_sys_init(address_space_mem, pic);

    if (nb_nics > 1) {
        error_report("Too many NICs");
        exit(1);
    }
    if (nd_table[0].used) {
        mcf_fec_init(address_space_mem, &nd_table[0],
                     0xfc030000, pic + 36);
    }

    g_free(pic);

    /*  0xfc000000 SCM.  */
    /*  0xfc004000 XBS.  */
    /*  0xfc008000 FlexBus CS.  */
    /* 0xfc030000 FEC.  */
    /*  0xfc040000 SCM + Power management.  */
    /*  0xfc044000 eDMA.  */
    /* 0xfc048000 INTC.  */
    /*  0xfc058000 I2C.  */
    /*  0xfc05c000 QSPI.  */
    /* 0xfc060000 UART0.  */
    /* 0xfc064000 UART0.  */
    /* 0xfc068000 UART0.  */
    /*  0xfc070000 DMA timers.  */
    /* 0xfc080000 PIT0.  */
    /* 0xfc084000 PIT1.  */
    /*  0xfc088000 EPORT.  */
    /*  0xfc08c000 Watchdog.  */
    /*  0xfc090000 clock module.  */
    /*  0xfc0a0000 CCM + reset.  */
    /*  0xfc0a4000 GPIO.  */
    /* 0xfc0a8000 SDRAM controller.  */

    /* Load firmware */
    if (machine->firmware) {
        char *fn;
        uint8_t *ptr;

        fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
        if (!fn) {
            error_report("Could not find ROM image '%s'", machine->firmware);
            exit(1);
        }
        if (load_image_targphys(fn, 0x0, ROM_SIZE) < 8) {
            error_report("Could not load ROM image '%s'", machine->firmware);
            exit(1);
        }
        g_free(fn);
        /* Initial PC is always at offset 4 in firmware binaries */
        ptr = rom_ptr(0x4, 4);
        assert(ptr != NULL);
        env->pc = ldl_p(ptr);
    }

    /* Load kernel.  */
    if (!kernel_filename) {
        if (qtest_enabled() || machine->firmware) {
            return;
        }
        error_report("Kernel image must be specified");
        exit(1);
    }

    kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry,
                           NULL, NULL, NULL, 1, EM_68K, 0, 0);
    entry = elf_entry;
    if (kernel_size < 0) {
        kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL,
                                  NULL, NULL);
    }
    if (kernel_size < 0) {
        kernel_size = load_image_targphys(kernel_filename, 0x40000000,
                                          ram_size);
        entry = 0x40000000;
    }
    if (kernel_size < 0) {
        error_report("Could not load kernel '%s'", kernel_filename);
        exit(1);
    }

    env->pc = entry;
}

static void mcf5208evb_machine_init(MachineClass *mc)
{
    mc->desc = "MCF5208EVB";
    mc->init = mcf5208evb_init;
    mc->is_default = true;
    mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208");
    mc->default_ram_id = "mcf5208.ram";
}

DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init)
Commit	Line	Data
5fafdf24	1	/*
20dcee94 PB	2	* Motorola ColdFire MCF5208 SoC emulation.
	3	*
	4	* Copyright (c) 2007 CodeSourcery.
	5	*
8e31bf38	6	* This code is licensed under the GPL
20dcee94	7	*/
64552b6b	8
d8416665	9	#include "qemu/osdep.h"
4dab9c73	10	#include "qemu/units.h"
45876e91	11	#include "qemu/error-report.h"
b8096678	12	#include "qemu/log.h"
da34e65c	13	#include "qapi/error.h"
2c65db5e	14	#include "qemu/datadir.h"
4771d756	15	#include "cpu.h"
64552b6b	16	#include "hw/irq.h"
0d09e41a	17	#include "hw/m68k/mcf.h"
6ac38ed4	18	#include "hw/m68k/mcf_fec.h"
1de7afc9	19	#include "qemu/timer.h"
83c9f4ca	20	#include "hw/ptimer.h"
9c17d615	21	#include "sysemu/sysemu.h"
5c12762c	22	#include "sysemu/qtest.h"
1422e32d	23	#include "net/net.h"
83c9f4ca PB	24	#include "hw/boards.h"
83c9f4ca PB	25	#include "hw/loader.h"
6ac38ed4	26	#include "hw/sysbus.h"
ca20cf32	27	#include "elf.h"
20dcee94	28
cbf061bd	29	#define SYS_FREQ 166666666
20dcee94	30
9f04e1d9 TH	31	#define ROM_SIZE 0x200000
9f04e1d9 TH	32
20dcee94 PB	33	#define PCSR_EN 0x0001
	34	#define PCSR_RLD 0x0002
	35	#define PCSR_PIF 0x0004
	36	#define PCSR_PIE 0x0008
	37	#define PCSR_OVW 0x0010
	38	#define PCSR_DBG 0x0020
	39	#define PCSR_DOZE 0x0040
	40	#define PCSR_PRE_SHIFT 8
	41	#define PCSR_PRE_MASK 0x0f00
	42
	43	typedef struct {
c378b364	44	MemoryRegion iomem;
20dcee94 PB	45	qemu_irq irq;
	46	ptimer_state *timer;
	47	uint16_t pcsr;
	48	uint16_t pmr;
	49	uint16_t pcntr;
	50	} m5208_timer_state;
	51
	52	static void m5208_timer_update(m5208_timer_state *s)
	53	{
	54	if ((s->pcsr & (PCSR_PIE \| PCSR_PIF)) == (PCSR_PIE \| PCSR_PIF))
	55	qemu_irq_raise(s->irq);
	56	else
	57	qemu_irq_lower(s->irq);
	58	}
	59
a8170e5e	60	static void m5208_timer_write(void *opaque, hwaddr offset,
c378b364	61	uint64_t value, unsigned size)
20dcee94	62	{
8da3ff18	63	m5208_timer_state s = (m5208_timer_state )opaque;
20dcee94 PB	64	int prescale;
	65	int limit;
	66	switch (offset) {
	67	case 0:
	68	/* The PIF bit is set-to-clear. */
	69	if (value & PCSR_PIF) {
	70	s->pcsr &= ~PCSR_PIF;
	71	value &= ~PCSR_PIF;
	72	}
	73	/* Avoid frobbing the timer if we're just twiddling IRQ bits. */
	74	if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) {
	75	s->pcsr = value;
	76	m5208_timer_update(s);
	77	return;
	78	}
	79
81b2d96b	80	ptimer_transaction_begin(s->timer);
20dcee94 PB	81	if (s->pcsr & PCSR_EN)
	82	ptimer_stop(s->timer);
	83
	84	s->pcsr = value;
	85
	86	prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
	87	ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
	88	if (s->pcsr & PCSR_RLD)
20dcee94	89	limit = s->pmr;
6d9db39c PB	90	else
6d9db39c PB	91	limit = 0xffff;
20dcee94 PB	92	ptimer_set_limit(s->timer, limit, 0);
	93
	94	if (s->pcsr & PCSR_EN)
	95	ptimer_run(s->timer, 0);
81b2d96b	96	ptimer_transaction_commit(s->timer);
20dcee94 PB	97	break;
20dcee94 PB	98	case 2:
81b2d96b	99	ptimer_transaction_begin(s->timer);
20dcee94 PB	100	s->pmr = value;
20dcee94 PB	101	s->pcsr &= ~PCSR_PIF;
6d9db39c PB	102	if ((s->pcsr & PCSR_RLD) == 0) {
	103	if (s->pcsr & PCSR_OVW)
	104	ptimer_set_count(s->timer, value);
	105	} else {
	106	ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
	107	}
81b2d96b	108	ptimer_transaction_commit(s->timer);
20dcee94 PB	109	break;
	110	case 4:
	111	break;
	112	default:
b8096678 PMD	113	qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
	114	__func__, offset);
	115	return;
20dcee94 PB	116	}
	117	m5208_timer_update(s);
	118	}
	119
	120	static void m5208_timer_trigger(void *opaque)
	121	{
	122	m5208_timer_state s = (m5208_timer_state )opaque;
	123	s->pcsr \|= PCSR_PIF;
	124	m5208_timer_update(s);
	125	}
	126
a8170e5e	127	static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
c378b364	128	unsigned size)
8da3ff18 PB	129	{
	130	m5208_timer_state s = (m5208_timer_state )opaque;
	131	switch (addr) {
	132	case 0:
	133	return s->pcsr;
	134	case 2:
	135	return s->pmr;
	136	case 4:
	137	return ptimer_get_count(s->timer);
	138	default:
b8096678 PMD	139	qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
b8096678 PMD	140	__func__, addr);
8da3ff18 PB	141	return 0;
	142	}
	143	}
	144
c378b364 AK	145	static const MemoryRegionOps m5208_timer_ops = {
	146	.read = m5208_timer_read,
	147	.write = m5208_timer_write,
	148	.endianness = DEVICE_NATIVE_ENDIAN,
8da3ff18 PB	149	};
8da3ff18 PB	150
a8170e5e	151	static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
c378b364	152	unsigned size)
20dcee94	153	{
20dcee94	154	switch (addr) {
8da3ff18	155	case 0x110: /* SDCS0 */
20dcee94 PB	156	{
	157	int n;
	158	for (n = 0; n < 32; n++) {
5601d241	159	if (current_machine->ram_size < (2u << n)) {
20dcee94	160	break;
5601d241	161	}
20dcee94 PB	162	}
	163	return (n - 1) \| 0x40000000;
	164	}
8da3ff18	165	case 0x114: /* SDCS1 */
20dcee94 PB	166	return 0;
	167
	168	default:
b8096678 PMD	169	qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
b8096678 PMD	170	__func__, addr);
20dcee94 PB	171	return 0;
	172	}
	173	}
	174
a8170e5e	175	static void m5208_sys_write(void *opaque, hwaddr addr,
c378b364	176	uint64_t value, unsigned size)
20dcee94	177	{
b8096678 PMD	178	qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
b8096678 PMD	179	__func__, addr);
20dcee94 PB	180	}
20dcee94 PB	181
c378b364 AK	182	static const MemoryRegionOps m5208_sys_ops = {
	183	.read = m5208_sys_read,
	184	.write = m5208_sys_write,
	185	.endianness = DEVICE_NATIVE_ENDIAN,
20dcee94 PB	186	};
20dcee94 PB	187
c378b364	188	static void mcf5208_sys_init(MemoryRegion address_space, qemu_irq pic)
20dcee94	189	{
c378b364	190	MemoryRegion *iomem = g_new(MemoryRegion, 1);
8da3ff18	191	m5208_timer_state *s;
20dcee94 PB	192	int i;
20dcee94 PB	193
20dcee94	194	/* SDRAMC. */
2c9b15ca	195	memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
c378b364	196	memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
20dcee94 PB	197	/* Timers. */
20dcee94 PB	198	for (i = 0; i < 2; i++) {
d3c92188	199	s = g_new0(m5208_timer_state, 1);
81b2d96b	200	s->timer = ptimer_init(m5208_timer_trigger, s, PTIMER_POLICY_DEFAULT);
2c9b15ca	201	memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s,
c378b364 AK	202	"m5208-timer", 0x00004000);
	203	memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
	204	&s->iomem);
8da3ff18	205	s->irq = pic[4 + i];
20dcee94 PB	206	}
	207	}
	208
6ac38ed4 TH	209	static void mcf_fec_init(MemoryRegion sysmem, NICInfo nd, hwaddr base,
	210	qemu_irq *irqs)
	211	{
	212	DeviceState *dev;
	213	SysBusDevice *s;
	214	int i;
	215
	216	qemu_check_nic_model(nd, TYPE_MCF_FEC_NET);
3e80f690	217	dev = qdev_new(TYPE_MCF_FEC_NET);
6ac38ed4	218	qdev_set_nic_properties(dev, nd);
6ac38ed4 TH	219
6ac38ed4 TH	220	s = SYS_BUS_DEVICE(dev);
3c6ef471	221	sysbus_realize_and_unref(s, &error_fatal);
6ac38ed4 TH	222	for (i = 0; i < FEC_NUM_IRQ; i++) {
	223	sysbus_connect_irq(s, i, irqs[i]);
	224	}
	225
	226	memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(s, 0));
	227	}
	228
3ef96221	229	static void mcf5208evb_init(MachineState *machine)
20dcee94	230	{
3ef96221	231	ram_addr_t ram_size = machine->ram_size;
3ef96221	232	const char *kernel_filename = machine->kernel_filename;
9a6ee9fd	233	M68kCPU *cpu;
7927df3a	234	CPUM68KState *env;
20dcee94 PB	235	int kernel_size;
20dcee94 PB	236	uint64_t elf_entry;
a8170e5e	237	hwaddr entry;
20dcee94	238	qemu_irq *pic;
c378b364	239	MemoryRegion *address_space_mem = get_system_memory();
9f04e1d9	240	MemoryRegion *rom = g_new(MemoryRegion, 1);
c378b364	241	MemoryRegion *sram = g_new(MemoryRegion, 1);
20dcee94	242
ddbcc16f	243	cpu = M68K_CPU(cpu_create(machine->cpu_type));
9a6ee9fd	244	env = &cpu->env;
20dcee94 PB	245
	246	/* Initialize CPU registers. */
	247	env->vbr = 0;
	248	/* TODO: Configure BARs. */
	249
9f04e1d9 TH	250	/* ROM at 0x00000000 */
	251	memory_region_init_rom(rom, NULL, "mcf5208.rom", ROM_SIZE, &error_fatal);
	252	memory_region_add_subregion(address_space_mem, 0x00000000, rom);
	253
dcac9679	254	/* DRAM at 0x40000000 */
32c245cf	255	memory_region_add_subregion(address_space_mem, 0x40000000, machine->ram);
20dcee94 PB	256
20dcee94 PB	257	/* Internal SRAM. */
4dab9c73	258	memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal);
c378b364	259	memory_region_add_subregion(address_space_mem, 0x80000000, sram);
20dcee94 PB	260
20dcee94 PB	261	/* Internal peripherals. */
9a6ee9fd	262	pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu);
20dcee94	263
9bca0edb PM	264	mcf_uart_mm_init(0xfc060000, pic[26], serial_hd(0));
	265	mcf_uart_mm_init(0xfc064000, pic[27], serial_hd(1));
	266	mcf_uart_mm_init(0xfc068000, pic[28], serial_hd(2));
20dcee94	267
c378b364	268	mcf5208_sys_init(address_space_mem, pic);
20dcee94	269
7e049b8a	270	if (nb_nics > 1) {
45876e91	271	error_report("Too many NICs");
7e049b8a PB	272	exit(1);
7e049b8a PB	273	}
6ac38ed4	274	if (nd_table[0].used) {
c65fc1df BC	275	mcf_fec_init(address_space_mem, &nd_table[0],
c65fc1df BC	276	0xfc030000, pic + 36);
6ac38ed4	277	}
7e049b8a	278
67c1ea99 PB	279	g_free(pic);
67c1ea99 PB	280
20dcee94 PB	281	/* 0xfc000000 SCM. */
	282	/* 0xfc004000 XBS. */
	283	/* 0xfc008000 FlexBus CS. */
7e049b8a	284	/* 0xfc030000 FEC. */
20dcee94 PB	285	/* 0xfc040000 SCM + Power management. */
	286	/* 0xfc044000 eDMA. */
	287	/* 0xfc048000 INTC. */
	288	/* 0xfc058000 I2C. */
	289	/* 0xfc05c000 QSPI. */
	290	/* 0xfc060000 UART0. */
	291	/* 0xfc064000 UART0. */
	292	/* 0xfc068000 UART0. */
	293	/* 0xfc070000 DMA timers. */
	294	/* 0xfc080000 PIT0. */
	295	/* 0xfc084000 PIT1. */
	296	/* 0xfc088000 EPORT. */
	297	/* 0xfc08c000 Watchdog. */
	298	/* 0xfc090000 clock module. */
	299	/* 0xfc0a0000 CCM + reset. */
	300	/* 0xfc0a4000 GPIO. */
	301	/* 0xfc0a8000 SDRAM controller. */
	302
9f04e1d9	303	/* Load firmware */
1684273c	304	if (machine->firmware) {
9f04e1d9 TH	305	char *fn;
	306	uint8_t *ptr;
	307
1684273c	308	fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
9f04e1d9	309	if (!fn) {
1684273c	310	error_report("Could not find ROM image '%s'", machine->firmware);
9f04e1d9 TH	311	exit(1);
	312	}
	313	if (load_image_targphys(fn, 0x0, ROM_SIZE) < 8) {
1684273c	314	error_report("Could not load ROM image '%s'", machine->firmware);
9f04e1d9 TH	315	exit(1);
	316	}
	317	g_free(fn);
	318	/* Initial PC is always at offset 4 in firmware binaries */
	319	ptr = rom_ptr(0x4, 4);
	320	assert(ptr != NULL);
	321	env->pc = ldl_p(ptr);
	322	}
	323
20dcee94 PB	324	/* Load kernel. */
20dcee94 PB	325	if (!kernel_filename) {
1684273c	326	if (qtest_enabled() \|\| machine->firmware) {
5c12762c AF	327	return;
5c12762c AF	328	}
45876e91	329	error_report("Kernel image must be specified");
20dcee94 PB	330	exit(1);
	331	}
	332
4366e1db	333	kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry,
6cdda0ff	334	NULL, NULL, NULL, 1, EM_68K, 0, 0);
20dcee94 PB	335	entry = elf_entry;
20dcee94 PB	336	if (kernel_size < 0) {
25bda50a MF	337	kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL,
25bda50a MF	338	NULL, NULL);
20dcee94 PB	339	}
20dcee94 PB	340	if (kernel_size < 0) {
dcac9679 PB	341	kernel_size = load_image_targphys(kernel_filename, 0x40000000,
	342	ram_size);
	343	entry = 0x40000000;
20dcee94 PB	344	}
20dcee94 PB	345	if (kernel_size < 0) {
45876e91	346	error_report("Could not load kernel '%s'", kernel_filename);
20dcee94 PB	347	exit(1);
	348	}
	349
	350	env->pc = entry;
	351	}
	352
e264d29d	353	static void mcf5208evb_machine_init(MachineClass *mc)
f80f9ec9	354	{
83dc62f6	355	mc->desc = "MCF5208EVB";
e264d29d	356	mc->init = mcf5208evb_init;
ea0ac7f6	357	mc->is_default = true;
ddbcc16f	358	mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208");
32c245cf	359	mc->default_ram_id = "mcf5208.ram";
f80f9ec9 AL	360	}
f80f9ec9 AL	361
e264d29d	362	DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init)