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Commit | Line | Data |
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04e7ca8d LV |
1 | /* |
2 | * QEMU Motorla 680x0 Macintosh hardware System Emulator | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
5 | * of this software and associated documentation files (the "Software"), to deal | |
6 | * in the Software without restriction, including without limitation the rights | |
7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
8 | * copies of the Software, and to permit persons to whom the Software is | |
9 | * furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
20 | * THE SOFTWARE. | |
21 | */ | |
22 | ||
23 | #include "qemu/osdep.h" | |
24 | #include "qemu/units.h" | |
2c65db5e | 25 | #include "qemu/datadir.h" |
693869a6 | 26 | #include "qemu/guest-random.h" |
04e7ca8d LV |
27 | #include "sysemu/sysemu.h" |
28 | #include "cpu.h" | |
04e7ca8d | 29 | #include "hw/boards.h" |
95264861 | 30 | #include "hw/or-irq.h" |
3ea74abe | 31 | #include "hw/nmi.h" |
04e7ca8d LV |
32 | #include "elf.h" |
33 | #include "hw/loader.h" | |
34 | #include "ui/console.h" | |
04e7ca8d LV |
35 | #include "hw/char/escc.h" |
36 | #include "hw/sysbus.h" | |
37 | #include "hw/scsi/esp.h" | |
382d71af LV |
38 | #include "standard-headers/asm-m68k/bootinfo.h" |
39 | #include "standard-headers/asm-m68k/bootinfo-mac.h" | |
04e7ca8d | 40 | #include "bootinfo.h" |
a8019229 | 41 | #include "hw/m68k/q800.h" |
04e7ca8d LV |
42 | #include "hw/misc/mac_via.h" |
43 | #include "hw/input/adb.h" | |
44 | #include "hw/nubus/mac-nubus-bridge.h" | |
45 | #include "hw/display/macfb.h" | |
46 | #include "hw/block/swim.h" | |
47 | #include "net/net.h" | |
48 | #include "qapi/error.h" | |
cc37d98b | 49 | #include "qemu/error-report.h" |
04e7ca8d LV |
50 | #include "sysemu/qtest.h" |
51 | #include "sysemu/runstate.h" | |
52 | #include "sysemu/reset.h" | |
07e39012 | 53 | #include "migration/vmstate.h" |
04e7ca8d | 54 | |
e24e58e8 | 55 | #define MACROM_ADDR 0x40800000 |
04e7ca8d LV |
56 | #define MACROM_SIZE 0x00100000 |
57 | ||
58 | #define MACROM_FILENAME "MacROM.bin" | |
59 | ||
653901ca LV |
60 | #define IO_BASE 0x50000000 |
61 | #define IO_SLICE 0x00040000 | |
62 | #define IO_SIZE 0x04000000 | |
63 | ||
64 | #define VIA_BASE (IO_BASE + 0x00000) | |
65 | #define SONIC_PROM_BASE (IO_BASE + 0x08000) | |
66 | #define SONIC_BASE (IO_BASE + 0x0a000) | |
67 | #define SCC_BASE (IO_BASE + 0x0c020) | |
68 | #define ESP_BASE (IO_BASE + 0x10000) | |
69 | #define ESP_PDMA (IO_BASE + 0x10100) | |
70 | #define ASC_BASE (IO_BASE + 0x14000) | |
71 | #define SWIM_BASE (IO_BASE + 0x1E000) | |
72 | ||
408c5733 MCA |
73 | #define SONIC_PROM_SIZE 0x1000 |
74 | ||
04e7ca8d LV |
75 | /* |
76 | * the video base, whereas it a Nubus address, | |
77 | * is needed by the kernel to have early display and | |
78 | * thus provided by the bootloader | |
79 | */ | |
df8abbba | 80 | #define VIDEO_BASE 0xf9000000 |
04e7ca8d LV |
81 | |
82 | #define MAC_CLOCK 3686418 | |
83 | ||
5ef25141 MCA |
84 | /* |
85 | * Slot 0x9 is reserved for use by the in-built framebuffer whilst only | |
86 | * slots 0xc, 0xd and 0xe physically exist on the Quadra 800 | |
87 | */ | |
88 | #define Q800_NUBUS_SLOTS_AVAILABLE (BIT(0x9) | BIT(0xc) | BIT(0xd) | \ | |
89 | BIT(0xe)) | |
90 | ||
04e7ca8d LV |
91 | /* |
92 | * The GLUE (General Logic Unit) is an Apple custom integrated circuit chip | |
93 | * that performs a variety of functions (RAM management, clock generation, ...). | |
94 | * The GLUE chip receives interrupt requests from various devices, | |
95 | * assign priority to each, and asserts one or more interrupt line to the | |
96 | * CPU. | |
97 | */ | |
98 | ||
07e39012 PM |
99 | #define TYPE_GLUE "q800-glue" |
100 | OBJECT_DECLARE_SIMPLE_TYPE(GLUEState, GLUE) | |
101 | ||
102 | struct GLUEState { | |
103 | SysBusDevice parent_obj; | |
cbba1243 | 104 | |
04e7ca8d LV |
105 | M68kCPU *cpu; |
106 | uint8_t ipr; | |
a85d18aa | 107 | uint8_t auxmode; |
f7c6e12e | 108 | qemu_irq irqs[1]; |
3ea74abe | 109 | QEMUTimer *nmi_release; |
07e39012 | 110 | }; |
04e7ca8d | 111 | |
91ff5e4d MCA |
112 | #define GLUE_IRQ_IN_VIA1 0 |
113 | #define GLUE_IRQ_IN_VIA2 1 | |
114 | #define GLUE_IRQ_IN_SONIC 2 | |
115 | #define GLUE_IRQ_IN_ESCC 3 | |
3ea74abe | 116 | #define GLUE_IRQ_IN_NMI 4 |
91ff5e4d | 117 | |
f7c6e12e MCA |
118 | #define GLUE_IRQ_NUBUS_9 0 |
119 | ||
c7710c1e MCA |
120 | /* |
121 | * The GLUE logic on the Quadra 800 supports 2 different IRQ routing modes | |
122 | * controlled from the VIA1 auxmode GPIO (port B bit 6) which are documented | |
123 | * in NetBSD as follows: | |
124 | * | |
125 | * A/UX mode (Linux, NetBSD, auxmode GPIO low) | |
126 | * | |
127 | * Level 0: Spurious: ignored | |
128 | * Level 1: Software | |
129 | * Level 2: VIA2 (except ethernet, sound) | |
130 | * Level 3: Ethernet | |
131 | * Level 4: Serial (SCC) | |
132 | * Level 5: Sound | |
133 | * Level 6: VIA1 | |
134 | * Level 7: NMIs: parity errors, RESET button, YANCC error | |
135 | * | |
136 | * Classic mode (default: used by MacOS, A/UX 3.0.1, auxmode GPIO high) | |
137 | * | |
138 | * Level 0: Spurious: ignored | |
139 | * Level 1: VIA1 (clock, ADB) | |
140 | * Level 2: VIA2 (NuBus, SCSI) | |
141 | * Level 3: | |
142 | * Level 4: Serial (SCC) | |
143 | * Level 5: | |
144 | * Level 6: | |
145 | * Level 7: Non-maskable: parity errors, RESET button | |
146 | * | |
147 | * Note that despite references to A/UX mode in Linux and NetBSD, at least | |
148 | * A/UX 3.0.1 still uses Classic mode. | |
149 | */ | |
150 | ||
04e7ca8d LV |
151 | static void GLUE_set_irq(void *opaque, int irq, int level) |
152 | { | |
153 | GLUEState *s = opaque; | |
154 | int i; | |
155 | ||
f7c6e12e MCA |
156 | if (s->auxmode) { |
157 | /* Classic mode */ | |
158 | switch (irq) { | |
c7710c1e MCA |
159 | case GLUE_IRQ_IN_VIA1: |
160 | irq = 0; | |
161 | break; | |
162 | ||
163 | case GLUE_IRQ_IN_VIA2: | |
164 | irq = 1; | |
165 | break; | |
166 | ||
f7c6e12e MCA |
167 | case GLUE_IRQ_IN_SONIC: |
168 | /* Route to VIA2 instead */ | |
169 | qemu_set_irq(s->irqs[GLUE_IRQ_NUBUS_9], level); | |
170 | return; | |
c7710c1e MCA |
171 | |
172 | case GLUE_IRQ_IN_ESCC: | |
173 | irq = 3; | |
174 | break; | |
175 | ||
3ea74abe MCA |
176 | case GLUE_IRQ_IN_NMI: |
177 | irq = 6; | |
178 | break; | |
179 | ||
c7710c1e MCA |
180 | default: |
181 | g_assert_not_reached(); | |
f7c6e12e MCA |
182 | } |
183 | } else { | |
184 | /* A/UX mode */ | |
185 | switch (irq) { | |
186 | case GLUE_IRQ_IN_VIA1: | |
187 | irq = 5; | |
188 | break; | |
189 | ||
190 | case GLUE_IRQ_IN_VIA2: | |
191 | irq = 1; | |
192 | break; | |
193 | ||
194 | case GLUE_IRQ_IN_SONIC: | |
195 | irq = 2; | |
196 | break; | |
197 | ||
198 | case GLUE_IRQ_IN_ESCC: | |
199 | irq = 3; | |
200 | break; | |
c7710c1e | 201 | |
3ea74abe MCA |
202 | case GLUE_IRQ_IN_NMI: |
203 | irq = 6; | |
204 | break; | |
205 | ||
c7710c1e MCA |
206 | default: |
207 | g_assert_not_reached(); | |
f7c6e12e | 208 | } |
91ff5e4d MCA |
209 | } |
210 | ||
04e7ca8d LV |
211 | if (level) { |
212 | s->ipr |= 1 << irq; | |
213 | } else { | |
214 | s->ipr &= ~(1 << irq); | |
215 | } | |
216 | ||
217 | for (i = 7; i >= 0; i--) { | |
218 | if ((s->ipr >> i) & 1) { | |
219 | m68k_set_irq_level(s->cpu, i + 1, i + 25); | |
220 | return; | |
221 | } | |
222 | } | |
223 | m68k_set_irq_level(s->cpu, 0, 0); | |
224 | } | |
225 | ||
a85d18aa MCA |
226 | static void glue_auxmode_set_irq(void *opaque, int irq, int level) |
227 | { | |
228 | GLUEState *s = GLUE(opaque); | |
229 | ||
230 | s->auxmode = level; | |
231 | } | |
232 | ||
3ea74abe MCA |
233 | static void glue_nmi(NMIState *n, int cpu_index, Error **errp) |
234 | { | |
235 | GLUEState *s = GLUE(n); | |
236 | ||
237 | /* Hold NMI active for 100ms */ | |
238 | GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 1); | |
239 | timer_mod(s->nmi_release, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100); | |
240 | } | |
241 | ||
242 | static void glue_nmi_release(void *opaque) | |
243 | { | |
244 | GLUEState *s = GLUE(opaque); | |
245 | ||
246 | GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 0); | |
247 | } | |
248 | ||
07e39012 PM |
249 | static void glue_reset(DeviceState *dev) |
250 | { | |
251 | GLUEState *s = GLUE(dev); | |
252 | ||
253 | s->ipr = 0; | |
a85d18aa | 254 | s->auxmode = 0; |
3ea74abe MCA |
255 | |
256 | timer_del(s->nmi_release); | |
07e39012 PM |
257 | } |
258 | ||
259 | static const VMStateDescription vmstate_glue = { | |
260 | .name = "q800-glue", | |
261 | .version_id = 0, | |
262 | .minimum_version_id = 0, | |
263 | .fields = (VMStateField[]) { | |
264 | VMSTATE_UINT8(ipr, GLUEState), | |
a85d18aa | 265 | VMSTATE_UINT8(auxmode, GLUEState), |
3ea74abe | 266 | VMSTATE_TIMER_PTR(nmi_release, GLUEState), |
07e39012 PM |
267 | VMSTATE_END_OF_LIST(), |
268 | }, | |
269 | }; | |
270 | ||
271 | /* | |
272 | * If the m68k CPU implemented its inbound irq lines as GPIO lines | |
273 | * rather than via the m68k_set_irq_level() function we would not need | |
274 | * this cpu link property and could instead provide outbound IRQ lines | |
275 | * that the board could wire up to the CPU. | |
276 | */ | |
277 | static Property glue_properties[] = { | |
278 | DEFINE_PROP_LINK("cpu", GLUEState, cpu, TYPE_M68K_CPU, M68kCPU *), | |
279 | DEFINE_PROP_END_OF_LIST(), | |
280 | }; | |
281 | ||
3ea74abe MCA |
282 | static void glue_finalize(Object *obj) |
283 | { | |
284 | GLUEState *s = GLUE(obj); | |
285 | ||
286 | timer_free(s->nmi_release); | |
287 | } | |
288 | ||
07e39012 PM |
289 | static void glue_init(Object *obj) |
290 | { | |
291 | DeviceState *dev = DEVICE(obj); | |
f7c6e12e | 292 | GLUEState *s = GLUE(dev); |
07e39012 PM |
293 | |
294 | qdev_init_gpio_in(dev, GLUE_set_irq, 8); | |
a85d18aa | 295 | qdev_init_gpio_in_named(dev, glue_auxmode_set_irq, "auxmode", 1); |
f7c6e12e MCA |
296 | |
297 | qdev_init_gpio_out(dev, s->irqs, 1); | |
3ea74abe MCA |
298 | |
299 | /* NMI release timer */ | |
300 | s->nmi_release = timer_new_ms(QEMU_CLOCK_VIRTUAL, glue_nmi_release, s); | |
07e39012 PM |
301 | } |
302 | ||
303 | static void glue_class_init(ObjectClass *klass, void *data) | |
304 | { | |
305 | DeviceClass *dc = DEVICE_CLASS(klass); | |
3ea74abe | 306 | NMIClass *nc = NMI_CLASS(klass); |
07e39012 PM |
307 | |
308 | dc->vmsd = &vmstate_glue; | |
309 | dc->reset = glue_reset; | |
310 | device_class_set_props(dc, glue_properties); | |
3ea74abe | 311 | nc->nmi_monitor_handler = glue_nmi; |
07e39012 PM |
312 | } |
313 | ||
314 | static const TypeInfo glue_info = { | |
315 | .name = TYPE_GLUE, | |
316 | .parent = TYPE_SYS_BUS_DEVICE, | |
317 | .instance_size = sizeof(GLUEState), | |
318 | .instance_init = glue_init, | |
3ea74abe | 319 | .instance_finalize = glue_finalize, |
07e39012 | 320 | .class_init = glue_class_init, |
3ea74abe MCA |
321 | .interfaces = (InterfaceInfo[]) { |
322 | { TYPE_NMI }, | |
323 | { } | |
324 | }, | |
07e39012 PM |
325 | }; |
326 | ||
04e7ca8d LV |
327 | static void main_cpu_reset(void *opaque) |
328 | { | |
fbbbe7eb | 329 | M68kCPU *cpu = opaque; |
04e7ca8d LV |
330 | CPUState *cs = CPU(cpu); |
331 | ||
332 | cpu_reset(cs); | |
333 | cpu->env.aregs[7] = ldl_phys(cs->as, 0); | |
334 | cpu->env.pc = ldl_phys(cs->as, 4); | |
335 | } | |
336 | ||
fbbbe7eb JD |
337 | static void rerandomize_rng_seed(void *opaque) |
338 | { | |
339 | struct bi_record *rng_seed = opaque; | |
340 | qemu_guest_getrandom_nofail((void *)rng_seed->data + 2, | |
341 | be16_to_cpu(*(uint16_t *)rng_seed->data)); | |
342 | } | |
343 | ||
e24e58e8 JD |
344 | static uint8_t fake_mac_rom[] = { |
345 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
346 | ||
347 | /* offset: 0xa - mac_reset */ | |
348 | ||
349 | /* via2[vDirB] |= VIA2B_vPower */ | |
350 | 0x20, 0x7C, 0x50, 0xF0, 0x24, 0x00, /* moveal VIA2_BASE+vDirB,%a0 */ | |
351 | 0x10, 0x10, /* moveb %a0@,%d0 */ | |
352 | 0x00, 0x00, 0x00, 0x04, /* orib #4,%d0 */ | |
353 | 0x10, 0x80, /* moveb %d0,%a0@ */ | |
354 | ||
355 | /* via2[vBufB] &= ~VIA2B_vPower */ | |
356 | 0x20, 0x7C, 0x50, 0xF0, 0x20, 0x00, /* moveal VIA2_BASE+vBufB,%a0 */ | |
357 | 0x10, 0x10, /* moveb %a0@,%d0 */ | |
358 | 0x02, 0x00, 0xFF, 0xFB, /* andib #-5,%d0 */ | |
359 | 0x10, 0x80, /* moveb %d0,%a0@ */ | |
360 | ||
361 | /* while (true) ; */ | |
362 | 0x60, 0xFE /* bras [self] */ | |
363 | }; | |
364 | ||
1a514d3a | 365 | static void q800_machine_init(MachineState *machine) |
04e7ca8d | 366 | { |
36e2e338 | 367 | Q800MachineState *m = Q800_MACHINE(machine); |
04e7ca8d LV |
368 | int linux_boot; |
369 | int32_t kernel_size; | |
370 | uint64_t elf_entry; | |
371 | char *filename; | |
372 | int bios_size; | |
373 | ram_addr_t initrd_base; | |
374 | int32_t initrd_size; | |
653901ca | 375 | MemoryRegion *io; |
408c5733 MCA |
376 | MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1); |
377 | uint8_t *prom; | |
653901ca | 378 | const int io_slice_nb = (IO_SIZE / IO_SLICE) - 1; |
408c5733 | 379 | int i, checksum; |
df8abbba | 380 | MacFbMode *macfb_mode; |
04e7ca8d LV |
381 | ram_addr_t ram_size = machine->ram_size; |
382 | const char *kernel_filename = machine->kernel_filename; | |
383 | const char *initrd_filename = machine->initrd_filename; | |
384 | const char *kernel_cmdline = machine->kernel_cmdline; | |
1684273c | 385 | const char *bios_name = machine->firmware ?: MACROM_FILENAME; |
04e7ca8d LV |
386 | hwaddr parameters_base; |
387 | CPUState *cs; | |
388 | DeviceState *dev; | |
02a68a3e | 389 | DeviceState *via1_dev, *via2_dev; |
95264861 | 390 | DeviceState *escc_orgate; |
04e7ca8d LV |
391 | SysBusESPState *sysbus_esp; |
392 | ESPState *esp; | |
393 | SysBusDevice *sysbus; | |
394 | BusState *adb_bus; | |
395 | NubusBus *nubus; | |
07e39012 | 396 | DeviceState *glue; |
eb064db9 | 397 | DriveInfo *dinfo; |
693869a6 | 398 | uint8_t rng_seed[32]; |
04e7ca8d LV |
399 | |
400 | linux_boot = (kernel_filename != NULL); | |
401 | ||
402 | if (ram_size > 1 * GiB) { | |
403 | error_report("Too much memory for this machine: %" PRId64 " MiB, " | |
404 | "maximum 1024 MiB", ram_size / MiB); | |
405 | exit(1); | |
406 | } | |
407 | ||
408 | /* init CPUs */ | |
36e2e338 MCA |
409 | object_initialize_child(OBJECT(machine), "cpu", &m->cpu, machine->cpu_type); |
410 | qdev_realize(DEVICE(&m->cpu), NULL, &error_fatal); | |
411 | qemu_register_reset(main_cpu_reset, &m->cpu); | |
04e7ca8d | 412 | |
653901ca | 413 | /* RAM */ |
8591a179 | 414 | memory_region_add_subregion(get_system_memory(), 0, machine->ram); |
04e7ca8d | 415 | |
653901ca LV |
416 | /* |
417 | * Memory from IO_BASE to IO_BASE + IO_SLICE is repeated | |
418 | * from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE | |
419 | */ | |
420 | io = g_new(MemoryRegion, io_slice_nb); | |
421 | for (i = 0; i < io_slice_nb; i++) { | |
422 | char *name = g_strdup_printf("mac_m68k.io[%d]", i + 1); | |
423 | ||
424 | memory_region_init_alias(&io[i], NULL, name, get_system_memory(), | |
425 | IO_BASE, IO_SLICE); | |
426 | memory_region_add_subregion(get_system_memory(), | |
427 | IO_BASE + (i + 1) * IO_SLICE, &io[i]); | |
428 | g_free(name); | |
429 | } | |
430 | ||
04e7ca8d | 431 | /* IRQ Glue */ |
07e39012 | 432 | glue = qdev_new(TYPE_GLUE); |
36e2e338 MCA |
433 | object_property_set_link(OBJECT(glue), "cpu", OBJECT(&m->cpu), |
434 | &error_abort); | |
07e39012 | 435 | sysbus_realize_and_unref(SYS_BUS_DEVICE(glue), &error_fatal); |
04e7ca8d | 436 | |
02a68a3e MCA |
437 | /* VIA 1 */ |
438 | via1_dev = qdev_new(TYPE_MOS6522_Q800_VIA1); | |
eb064db9 LV |
439 | dinfo = drive_get(IF_MTD, 0, 0); |
440 | if (dinfo) { | |
02a68a3e | 441 | qdev_prop_set_drive(via1_dev, "drive", blk_by_legacy_dinfo(dinfo)); |
eb064db9 | 442 | } |
02a68a3e | 443 | sysbus = SYS_BUS_DEVICE(via1_dev); |
3c6ef471 | 444 | sysbus_realize_and_unref(sysbus, &error_fatal); |
02a68a3e | 445 | sysbus_mmio_map(sysbus, 1, VIA_BASE); |
91ff5e4d | 446 | sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA1)); |
a85d18aa MCA |
447 | /* A/UX mode */ |
448 | qdev_connect_gpio_out(via1_dev, 0, | |
449 | qdev_get_gpio_in_named(glue, "auxmode", 0)); | |
02a68a3e MCA |
450 | |
451 | adb_bus = qdev_get_child_bus(via1_dev, "adb.0"); | |
3e80f690 MA |
452 | dev = qdev_new(TYPE_ADB_KEYBOARD); |
453 | qdev_realize_and_unref(dev, adb_bus, &error_fatal); | |
454 | dev = qdev_new(TYPE_ADB_MOUSE); | |
455 | qdev_realize_and_unref(dev, adb_bus, &error_fatal); | |
04e7ca8d | 456 | |
02a68a3e MCA |
457 | /* VIA 2 */ |
458 | via2_dev = qdev_new(TYPE_MOS6522_Q800_VIA2); | |
459 | sysbus = SYS_BUS_DEVICE(via2_dev); | |
460 | sysbus_realize_and_unref(sysbus, &error_fatal); | |
461 | sysbus_mmio_map(sysbus, 1, VIA_BASE + VIA_SIZE); | |
91ff5e4d | 462 | sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA2)); |
02a68a3e | 463 | |
04e7ca8d LV |
464 | /* MACSONIC */ |
465 | ||
466 | if (nb_nics > 1) { | |
467 | error_report("q800 can only have one ethernet interface"); | |
468 | exit(1); | |
469 | } | |
470 | ||
471 | qemu_check_nic_model(&nd_table[0], "dp83932"); | |
472 | ||
473 | /* | |
474 | * MacSonic driver needs an Apple MAC address | |
475 | * Valid prefix are: | |
476 | * 00:05:02 Apple | |
477 | * 00:80:19 Dayna Communications, Inc. | |
478 | * 00:A0:40 Apple | |
479 | * 08:00:07 Apple | |
480 | * (Q800 use the last one) | |
481 | */ | |
482 | nd_table[0].macaddr.a[0] = 0x08; | |
483 | nd_table[0].macaddr.a[1] = 0x00; | |
484 | nd_table[0].macaddr.a[2] = 0x07; | |
485 | ||
3e80f690 | 486 | dev = qdev_new("dp8393x"); |
04e7ca8d LV |
487 | qdev_set_nic_properties(dev, &nd_table[0]); |
488 | qdev_prop_set_uint8(dev, "it_shift", 2); | |
489 | qdev_prop_set_bit(dev, "big_endian", true); | |
5325cc34 MA |
490 | object_property_set_link(OBJECT(dev), "dma_mr", |
491 | OBJECT(get_system_memory()), &error_abort); | |
04e7ca8d | 492 | sysbus = SYS_BUS_DEVICE(dev); |
3c6ef471 | 493 | sysbus_realize_and_unref(sysbus, &error_fatal); |
04e7ca8d | 494 | sysbus_mmio_map(sysbus, 0, SONIC_BASE); |
91ff5e4d | 495 | sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_SONIC)); |
04e7ca8d | 496 | |
408c5733 MCA |
497 | memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-q800.prom", |
498 | SONIC_PROM_SIZE, &error_fatal); | |
499 | memory_region_add_subregion(get_system_memory(), SONIC_PROM_BASE, | |
500 | dp8393x_prom); | |
501 | ||
502 | /* Add MAC address with valid checksum to PROM */ | |
503 | prom = memory_region_get_ram_ptr(dp8393x_prom); | |
504 | checksum = 0; | |
505 | for (i = 0; i < 6; i++) { | |
2f0e10a4 | 506 | prom[i] = revbit8(nd_table[0].macaddr.a[i]); |
846feac2 | 507 | checksum ^= prom[i]; |
408c5733 MCA |
508 | } |
509 | prom[7] = 0xff - checksum; | |
510 | ||
04e7ca8d LV |
511 | /* SCC */ |
512 | ||
3e80f690 | 513 | dev = qdev_new(TYPE_ESCC); |
04e7ca8d LV |
514 | qdev_prop_set_uint32(dev, "disabled", 0); |
515 | qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK); | |
516 | qdev_prop_set_uint32(dev, "it_shift", 1); | |
517 | qdev_prop_set_bit(dev, "bit_swap", true); | |
518 | qdev_prop_set_chr(dev, "chrA", serial_hd(0)); | |
519 | qdev_prop_set_chr(dev, "chrB", serial_hd(1)); | |
520 | qdev_prop_set_uint32(dev, "chnBtype", 0); | |
521 | qdev_prop_set_uint32(dev, "chnAtype", 0); | |
04e7ca8d | 522 | sysbus = SYS_BUS_DEVICE(dev); |
3c6ef471 | 523 | sysbus_realize_and_unref(sysbus, &error_fatal); |
95264861 PM |
524 | |
525 | /* Logically OR both its IRQs together */ | |
526 | escc_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | |
527 | object_property_set_int(OBJECT(escc_orgate), "num-lines", 2, &error_fatal); | |
528 | qdev_realize_and_unref(escc_orgate, NULL, &error_fatal); | |
529 | sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(escc_orgate, 0)); | |
530 | sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(escc_orgate, 1)); | |
7d5b0d68 | 531 | qdev_connect_gpio_out(escc_orgate, 0, |
91ff5e4d | 532 | qdev_get_gpio_in(glue, GLUE_IRQ_IN_ESCC)); |
04e7ca8d LV |
533 | sysbus_mmio_map(sysbus, 0, SCC_BASE); |
534 | ||
535 | /* SCSI */ | |
536 | ||
84fbefed MCA |
537 | dev = qdev_new(TYPE_SYSBUS_ESP); |
538 | sysbus_esp = SYSBUS_ESP(dev); | |
04e7ca8d LV |
539 | esp = &sysbus_esp->esp; |
540 | esp->dma_memory_read = NULL; | |
541 | esp->dma_memory_write = NULL; | |
542 | esp->dma_opaque = NULL; | |
543 | sysbus_esp->it_shift = 4; | |
544 | esp->dma_enabled = 1; | |
04e7ca8d LV |
545 | |
546 | sysbus = SYS_BUS_DEVICE(dev); | |
3c6ef471 | 547 | sysbus_realize_and_unref(sysbus, &error_fatal); |
b793b4ef MCA |
548 | /* SCSI and SCSI data IRQs are negative edge triggered */ |
549 | sysbus_connect_irq(sysbus, 0, qemu_irq_invert(qdev_get_gpio_in(via2_dev, | |
550 | VIA2_IRQ_SCSI_BIT))); | |
551 | sysbus_connect_irq(sysbus, 1, qemu_irq_invert(qdev_get_gpio_in(via2_dev, | |
552 | VIA2_IRQ_SCSI_DATA_BIT))); | |
04e7ca8d LV |
553 | sysbus_mmio_map(sysbus, 0, ESP_BASE); |
554 | sysbus_mmio_map(sysbus, 1, ESP_PDMA); | |
555 | ||
556 | scsi_bus_legacy_handle_cmdline(&esp->bus); | |
557 | ||
558 | /* SWIM floppy controller */ | |
559 | ||
3e80f690 | 560 | dev = qdev_new(TYPE_SWIM); |
3c6ef471 | 561 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
04e7ca8d LV |
562 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE); |
563 | ||
564 | /* NuBus */ | |
565 | ||
3e80f690 | 566 | dev = qdev_new(TYPE_MAC_NUBUS_BRIDGE); |
5ef25141 MCA |
567 | qdev_prop_set_uint32(dev, "slot-available-mask", |
568 | Q800_NUBUS_SLOTS_AVAILABLE); | |
3c6ef471 | 569 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
62437f90 MCA |
570 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, |
571 | MAC_NUBUS_FIRST_SLOT * NUBUS_SUPER_SLOT_SIZE); | |
572 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE + | |
573 | MAC_NUBUS_FIRST_SLOT * NUBUS_SLOT_SIZE); | |
efd0c37e MCA |
574 | qdev_connect_gpio_out(dev, 9, |
575 | qdev_get_gpio_in_named(via2_dev, "nubus-irq", | |
576 | VIA2_NUBUS_IRQ_INTVIDEO)); | |
577 | for (i = 1; i < VIA2_NUBUS_IRQ_NB; i++) { | |
b297843e MCA |
578 | qdev_connect_gpio_out(dev, 9 + i, |
579 | qdev_get_gpio_in_named(via2_dev, "nubus-irq", | |
580 | VIA2_NUBUS_IRQ_9 + i)); | |
581 | } | |
582 | ||
f7c6e12e MCA |
583 | /* |
584 | * Since the framebuffer in slot 0x9 uses a separate IRQ, wire the unused | |
585 | * IRQ via GLUE for use by SONIC Ethernet in classic mode | |
586 | */ | |
587 | qdev_connect_gpio_out(glue, GLUE_IRQ_NUBUS_9, | |
588 | qdev_get_gpio_in_named(via2_dev, "nubus-irq", | |
589 | VIA2_NUBUS_IRQ_9)); | |
590 | ||
d585d89d | 591 | nubus = &NUBUS_BRIDGE(dev)->bus; |
04e7ca8d LV |
592 | |
593 | /* framebuffer in nubus slot #9 */ | |
594 | ||
3e80f690 | 595 | dev = qdev_new(TYPE_NUBUS_MACFB); |
efd0c37e | 596 | qdev_prop_set_uint32(dev, "slot", 9); |
04e7ca8d LV |
597 | qdev_prop_set_uint32(dev, "width", graphic_width); |
598 | qdev_prop_set_uint32(dev, "height", graphic_height); | |
599 | qdev_prop_set_uint8(dev, "depth", graphic_depth); | |
a56c12fb | 600 | if (graphic_width == 1152 && graphic_height == 870) { |
4317c518 MCA |
601 | qdev_prop_set_uint8(dev, "display", MACFB_DISPLAY_APPLE_21_COLOR); |
602 | } else { | |
603 | qdev_prop_set_uint8(dev, "display", MACFB_DISPLAY_VGA); | |
604 | } | |
3e80f690 | 605 | qdev_realize_and_unref(dev, BUS(nubus), &error_fatal); |
04e7ca8d | 606 | |
df8abbba MCA |
607 | macfb_mode = (NUBUS_MACFB(dev)->macfb).mode; |
608 | ||
36e2e338 | 609 | cs = CPU(&m->cpu); |
04e7ca8d LV |
610 | if (linux_boot) { |
611 | uint64_t high; | |
281ac13e JD |
612 | void *param_blob, *param_ptr, *param_rng_seed; |
613 | ||
614 | if (kernel_cmdline) { | |
615 | param_blob = g_malloc(strlen(kernel_cmdline) + 1024); | |
616 | } else { | |
617 | param_blob = g_malloc(1024); | |
618 | } | |
619 | ||
04e7ca8d | 620 | kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, |
6cdda0ff | 621 | &elf_entry, NULL, &high, NULL, 1, |
04e7ca8d LV |
622 | EM_68K, 0, 0); |
623 | if (kernel_size < 0) { | |
624 | error_report("could not load kernel '%s'", kernel_filename); | |
625 | exit(1); | |
626 | } | |
627 | stl_phys(cs->as, 4, elf_entry); /* reset initial PC */ | |
628 | parameters_base = (high + 1) & ~1; | |
281ac13e JD |
629 | param_ptr = param_blob; |
630 | ||
631 | BOOTINFO1(param_ptr, BI_MACHTYPE, MACH_MAC); | |
632 | BOOTINFO1(param_ptr, BI_FPUTYPE, FPU_68040); | |
633 | BOOTINFO1(param_ptr, BI_MMUTYPE, MMU_68040); | |
634 | BOOTINFO1(param_ptr, BI_CPUTYPE, CPU_68040); | |
635 | BOOTINFO1(param_ptr, BI_MAC_CPUID, CPUB_68040); | |
636 | BOOTINFO1(param_ptr, BI_MAC_MODEL, MAC_MODEL_Q800); | |
637 | BOOTINFO1(param_ptr, | |
04e7ca8d | 638 | BI_MAC_MEMSIZE, ram_size >> 20); /* in MB */ |
281ac13e JD |
639 | BOOTINFO2(param_ptr, BI_MEMCHUNK, 0, ram_size); |
640 | BOOTINFO1(param_ptr, BI_MAC_VADDR, | |
df8abbba | 641 | VIDEO_BASE + macfb_mode->offset); |
281ac13e JD |
642 | BOOTINFO1(param_ptr, BI_MAC_VDEPTH, graphic_depth); |
643 | BOOTINFO1(param_ptr, BI_MAC_VDIM, | |
04e7ca8d | 644 | (graphic_height << 16) | graphic_width); |
281ac13e JD |
645 | BOOTINFO1(param_ptr, BI_MAC_VROW, macfb_mode->stride); |
646 | BOOTINFO1(param_ptr, BI_MAC_SCCBASE, SCC_BASE); | |
04e7ca8d | 647 | |
0b9b41fb | 648 | memory_region_init_ram_ptr(&m->rom, NULL, "m68k_fake_mac.rom", |
e24e58e8 | 649 | sizeof(fake_mac_rom), fake_mac_rom); |
0b9b41fb MCA |
650 | memory_region_set_readonly(&m->rom, true); |
651 | memory_region_add_subregion(get_system_memory(), MACROM_ADDR, &m->rom); | |
e24e58e8 | 652 | |
04e7ca8d | 653 | if (kernel_cmdline) { |
281ac13e | 654 | BOOTINFOSTR(param_ptr, BI_COMMAND_LINE, |
04e7ca8d LV |
655 | kernel_cmdline); |
656 | } | |
657 | ||
693869a6 | 658 | /* Pass seed to RNG. */ |
281ac13e | 659 | param_rng_seed = param_ptr; |
693869a6 | 660 | qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); |
281ac13e | 661 | BOOTINFODATA(param_ptr, BI_RNG_SEED, |
693869a6 JD |
662 | rng_seed, sizeof(rng_seed)); |
663 | ||
04e7ca8d LV |
664 | /* load initrd */ |
665 | if (initrd_filename) { | |
666 | initrd_size = get_image_size(initrd_filename); | |
667 | if (initrd_size < 0) { | |
668 | error_report("could not load initial ram disk '%s'", | |
669 | initrd_filename); | |
670 | exit(1); | |
671 | } | |
672 | ||
673 | initrd_base = (ram_size - initrd_size) & TARGET_PAGE_MASK; | |
674 | load_image_targphys(initrd_filename, initrd_base, | |
675 | ram_size - initrd_base); | |
281ac13e | 676 | BOOTINFO2(param_ptr, BI_RAMDISK, initrd_base, |
04e7ca8d LV |
677 | initrd_size); |
678 | } else { | |
679 | initrd_base = 0; | |
680 | initrd_size = 0; | |
681 | } | |
281ac13e JD |
682 | BOOTINFO0(param_ptr, BI_LAST); |
683 | rom_add_blob_fixed_as("bootinfo", param_blob, param_ptr - param_blob, | |
684 | parameters_base, cs->as); | |
fbbbe7eb JD |
685 | qemu_register_reset_nosnapshotload(rerandomize_rng_seed, |
686 | rom_ptr_for_as(cs->as, parameters_base, | |
687 | param_ptr - param_blob) + | |
688 | (param_rng_seed - param_blob)); | |
281ac13e | 689 | g_free(param_blob); |
04e7ca8d LV |
690 | } else { |
691 | uint8_t *ptr; | |
692 | /* allocate and load BIOS */ | |
0b9b41fb | 693 | memory_region_init_rom(&m->rom, NULL, "m68k_mac.rom", MACROM_SIZE, |
04e7ca8d | 694 | &error_abort); |
04e7ca8d | 695 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
0b9b41fb | 696 | memory_region_add_subregion(get_system_memory(), MACROM_ADDR, &m->rom); |
04e7ca8d LV |
697 | |
698 | /* Load MacROM binary */ | |
699 | if (filename) { | |
700 | bios_size = load_image_targphys(filename, MACROM_ADDR, MACROM_SIZE); | |
701 | g_free(filename); | |
702 | } else { | |
703 | bios_size = -1; | |
704 | } | |
705 | ||
706 | /* Remove qtest_enabled() check once firmware files are in the tree */ | |
707 | if (!qtest_enabled()) { | |
0969e00b | 708 | if (bios_size <= 0 || bios_size > MACROM_SIZE) { |
04e7ca8d LV |
709 | error_report("could not load MacROM '%s'", bios_name); |
710 | exit(1); | |
711 | } | |
712 | ||
0969e00b LV |
713 | ptr = rom_ptr(MACROM_ADDR, bios_size); |
714 | assert(ptr != NULL); | |
04e7ca8d LV |
715 | stl_phys(cs->as, 0, ldl_p(ptr)); /* reset initial SP */ |
716 | stl_phys(cs->as, 4, | |
717 | MACROM_ADDR + ldl_p(ptr + 4)); /* reset initial PC */ | |
718 | } | |
719 | } | |
720 | } | |
721 | ||
f3582410 | 722 | static GlobalProperty hw_compat_q800[] = { |
26fcbf00 | 723 | { "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on" }, |
0fc37ada MCA |
724 | { "scsi-hd", "vendor", " SEAGATE" }, |
725 | { "scsi-hd", "product", " ST225N" }, | |
726 | { "scsi-hd", "ver", "1.0 " }, | |
26fcbf00 MCA |
727 | { "scsi-cd", "quirk_mode_page_apple_vendor", "on" }, |
728 | { "scsi-cd", "quirk_mode_sense_rom_use_dbd", "on" }, | |
729 | { "scsi-cd", "quirk_mode_page_vendor_specific_apple", "on" }, | |
730 | { "scsi-cd", "quirk_mode_page_truncated", "on" }, | |
74518fb6 MCA |
731 | { "scsi-cd", "vendor", "MATSHITA" }, |
732 | { "scsi-cd", "product", "CD-ROM CR-8005" }, | |
733 | { "scsi-cd", "ver", "1.0k" }, | |
f3582410 MCA |
734 | }; |
735 | static const size_t hw_compat_q800_len = G_N_ELEMENTS(hw_compat_q800); | |
736 | ||
36e2e338 MCA |
737 | static const char *q800_machine_valid_cpu_types[] = { |
738 | M68K_CPU_TYPE_NAME("m68040"), | |
739 | NULL | |
740 | }; | |
741 | ||
04e7ca8d LV |
742 | static void q800_machine_class_init(ObjectClass *oc, void *data) |
743 | { | |
744 | MachineClass *mc = MACHINE_CLASS(oc); | |
1a514d3a | 745 | |
04e7ca8d | 746 | mc->desc = "Macintosh Quadra 800"; |
1a514d3a | 747 | mc->init = q800_machine_init; |
04e7ca8d | 748 | mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); |
36e2e338 | 749 | mc->valid_cpu_types = q800_machine_valid_cpu_types; |
04e7ca8d | 750 | mc->max_cpus = 1; |
04e7ca8d | 751 | mc->block_default_type = IF_SCSI; |
8591a179 | 752 | mc->default_ram_id = "m68k_mac.ram"; |
f3582410 | 753 | compat_props_add(mc->compat_props, hw_compat_q800, hw_compat_q800_len); |
04e7ca8d LV |
754 | } |
755 | ||
756 | static const TypeInfo q800_machine_typeinfo = { | |
757 | .name = MACHINE_TYPE_NAME("q800"), | |
758 | .parent = TYPE_MACHINE, | |
a8019229 | 759 | .instance_size = sizeof(Q800MachineState), |
04e7ca8d LV |
760 | .class_init = q800_machine_class_init, |
761 | }; | |
762 | ||
763 | static void q800_machine_register_types(void) | |
764 | { | |
765 | type_register_static(&q800_machine_typeinfo); | |
07e39012 | 766 | type_register_static(&glue_info); |
04e7ca8d LV |
767 | } |
768 | ||
769 | type_init(q800_machine_register_types) |