[mirror_qemu.git] / hw / mc146818rtc.c

/*
 * QEMU MC146818 RTC emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "pc.h"
#include "isa.h"

//#define DEBUG_CMOS

#define RTC_SECONDS             0
#define RTC_SECONDS_ALARM       1
#define RTC_MINUTES             2
#define RTC_MINUTES_ALARM       3
#define RTC_HOURS               4
#define RTC_HOURS_ALARM         5
#define RTC_ALARM_DONT_CARE    0xC0

#define RTC_DAY_OF_WEEK         6
#define RTC_DAY_OF_MONTH        7
#define RTC_MONTH               8
#define RTC_YEAR                9

#define RTC_REG_A               10
#define RTC_REG_B               11
#define RTC_REG_C               12
#define RTC_REG_D               13

#define REG_A_UIP 0x80

#define REG_B_SET 0x80
#define REG_B_PIE 0x40
#define REG_B_AIE 0x20
#define REG_B_UIE 0x10

struct RTCState {
    uint8_t cmos_data[128];
    uint8_t cmos_index;
    struct tm current_tm;
    qemu_irq irq;
    target_phys_addr_t base;
    int it_shift;
    /* periodic timer */
    QEMUTimer *periodic_timer;
    int64_t next_periodic_time;
    /* second update */
    int64_t next_second_time;
    QEMUTimer *second_timer;
    QEMUTimer *second_timer2;
};

static void rtc_set_time(RTCState *s);
static void rtc_copy_date(RTCState *s);

static void rtc_timer_update(RTCState *s, int64_t current_time)
{
    int period_code, period;
    int64_t cur_clock, next_irq_clock;

    period_code = s->cmos_data[RTC_REG_A] & 0x0f;
    if (period_code != 0 &&
        (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
        if (period_code <= 2)
            period_code += 7;
        /* period in 32 Khz cycles */
        period = 1 << (period_code - 1);
        /* compute 32 khz clock */
        cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
        next_irq_clock = (cur_clock & ~(period - 1)) + period;
        s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1;
        qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
    } else {
        qemu_del_timer(s->periodic_timer);
    }
}

static void rtc_periodic_timer(void *opaque)
{
    RTCState *s = opaque;

    rtc_timer_update(s, s->next_periodic_time);
    s->cmos_data[RTC_REG_C] |= 0xc0;
    qemu_irq_raise(s->irq);
}

static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
{
    RTCState *s = opaque;

    if ((addr & 1) == 0) {
        s->cmos_index = data & 0x7f;
    } else {
#ifdef DEBUG_CMOS
        printf("cmos: write index=0x%02x val=0x%02x\n",
               s->cmos_index, data);
#endif
        switch(s->cmos_index) {
        case RTC_SECONDS_ALARM:
        case RTC_MINUTES_ALARM:
        case RTC_HOURS_ALARM:
            /* XXX: not supported */
            s->cmos_data[s->cmos_index] = data;
            break;
        case RTC_SECONDS:
        case RTC_MINUTES:
        case RTC_HOURS:
        case RTC_DAY_OF_WEEK:
        case RTC_DAY_OF_MONTH:
        case RTC_MONTH:
        case RTC_YEAR:
            s->cmos_data[s->cmos_index] = data;
            /* if in set mode, do not update the time */
            if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
                rtc_set_time(s);
            }
            break;
        case RTC_REG_A:
            /* UIP bit is read only */
            s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
                (s->cmos_data[RTC_REG_A] & REG_A_UIP);
            rtc_timer_update(s, qemu_get_clock(vm_clock));
            break;
        case RTC_REG_B:
            if (data & REG_B_SET) {
                /* set mode: reset UIP mode */
                s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
                data &= ~REG_B_UIE;
            } else {
                /* if disabling set mode, update the time */
                if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
                    rtc_set_time(s);
                }
            }
            s->cmos_data[RTC_REG_B] = data;
            rtc_timer_update(s, qemu_get_clock(vm_clock));
            break;
        case RTC_REG_C:
        case RTC_REG_D:
            /* cannot write to them */
            break;
        default:
            s->cmos_data[s->cmos_index] = data;
            break;
        }
    }
}

static inline int to_bcd(RTCState *s, int a)
{
    if (s->cmos_data[RTC_REG_B] & 0x04) {
        return a;
    } else {
        return ((a / 10) << 4) | (a % 10);
    }
}

static inline int from_bcd(RTCState *s, int a)
{
    if (s->cmos_data[RTC_REG_B] & 0x04) {
        return a;
    } else {
        return ((a >> 4) * 10) + (a & 0x0f);
    }
}

static void rtc_set_time(RTCState *s)
{
    struct tm *tm = &s->current_tm;

    tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
    tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
    tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
    if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
        (s->cmos_data[RTC_HOURS] & 0x80)) {
        tm->tm_hour += 12;
    }
    tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
    tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
    tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
    tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
}

static void rtc_copy_date(RTCState *s)
{
    const struct tm *tm = &s->current_tm;

    s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
    s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
    if (s->cmos_data[RTC_REG_B] & 0x02) {
        /* 24 hour format */
        s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
    } else {
        /* 12 hour format */
        s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
        if (tm->tm_hour >= 12)
            s->cmos_data[RTC_HOURS] |= 0x80;
    }
    s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
    s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
    s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
    s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
}

/* month is between 0 and 11. */
static int get_days_in_month(int month, int year)
{
    static const int days_tab[12] = {
        31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
    };
    int d;
    if ((unsigned )month >= 12)
        return 31;
    d = days_tab[month];
    if (month == 1) {
        if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
            d++;
    }
    return d;
}

/* update 'tm' to the next second */
static void rtc_next_second(struct tm *tm)
{
    int days_in_month;

    tm->tm_sec++;
    if ((unsigned)tm->tm_sec >= 60) {
        tm->tm_sec = 0;
        tm->tm_min++;
        if ((unsigned)tm->tm_min >= 60) {
            tm->tm_min = 0;
            tm->tm_hour++;
            if ((unsigned)tm->tm_hour >= 24) {
                tm->tm_hour = 0;
                /* next day */
                tm->tm_wday++;
                if ((unsigned)tm->tm_wday >= 7)
                    tm->tm_wday = 0;
                days_in_month = get_days_in_month(tm->tm_mon,
                                                  tm->tm_year + 1900);
                tm->tm_mday++;
                if (tm->tm_mday < 1) {
                    tm->tm_mday = 1;
                } else if (tm->tm_mday > days_in_month) {
                    tm->tm_mday = 1;
                    tm->tm_mon++;
                    if (tm->tm_mon >= 12) {
                        tm->tm_mon = 0;
                        tm->tm_year++;
                    }
                }
            }
        }
    }
}


static void rtc_update_second(void *opaque)
{
    RTCState *s = opaque;
    int64_t delay;

    /* if the oscillator is not in normal operation, we do not update */
    if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
        s->next_second_time += ticks_per_sec;
        qemu_mod_timer(s->second_timer, s->next_second_time);
    } else {
        rtc_next_second(&s->current_tm);

        if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
            /* update in progress bit */
            s->cmos_data[RTC_REG_A] |= REG_A_UIP;
        }
        /* should be 244 us = 8 / 32768 seconds, but currently the
           timers do not have the necessary resolution. */
        delay = (ticks_per_sec * 1) / 100;
        if (delay < 1)
            delay = 1;
        qemu_mod_timer(s->second_timer2,
                       s->next_second_time + delay);
    }
}

static void rtc_update_second2(void *opaque)
{
    RTCState *s = opaque;

    if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
        rtc_copy_date(s);
    }

    /* check alarm */
    if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
        if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
             s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
            ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
             s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
            ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
             s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {

            s->cmos_data[RTC_REG_C] |= 0xa0;
            qemu_irq_raise(s->irq);
        }
    }

    /* update ended interrupt */
    if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
        s->cmos_data[RTC_REG_C] |= 0x90;
        qemu_irq_raise(s->irq);
    }

    /* clear update in progress bit */
    s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;

    s->next_second_time += ticks_per_sec;
    qemu_mod_timer(s->second_timer, s->next_second_time);
}

static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
{
    RTCState *s = opaque;
    int ret;
    if ((addr & 1) == 0) {
        return 0xff;
    } else {
        switch(s->cmos_index) {
        case RTC_SECONDS:
        case RTC_MINUTES:
        case RTC_HOURS:
        case RTC_DAY_OF_WEEK:
        case RTC_DAY_OF_MONTH:
        case RTC_MONTH:
        case RTC_YEAR:
            ret = s->cmos_data[s->cmos_index];
            break;
        case RTC_REG_A:
            ret = s->cmos_data[s->cmos_index];
            break;
        case RTC_REG_C:
            ret = s->cmos_data[s->cmos_index];
            qemu_irq_lower(s->irq);
            s->cmos_data[RTC_REG_C] = 0x00;
            break;
        default:
            ret = s->cmos_data[s->cmos_index];
            break;
        }
#ifdef DEBUG_CMOS
        printf("cmos: read index=0x%02x val=0x%02x\n",
               s->cmos_index, ret);
#endif
        return ret;
    }
}

void rtc_set_memory(RTCState *s, int addr, int val)
{
    if (addr >= 0 && addr <= 127)
        s->cmos_data[addr] = val;
}

void rtc_set_date(RTCState *s, const struct tm *tm)
{
    s->current_tm = *tm;
    rtc_copy_date(s);
}

/* PC cmos mappings */
#define REG_IBM_CENTURY_BYTE        0x32
#define REG_IBM_PS2_CENTURY_BYTE    0x37

static void rtc_set_date_from_host(RTCState *s)
{
    struct tm tm;
    int val;

    /* set the CMOS date */
    qemu_get_timedate(&tm, 0);
    rtc_set_date(s, &tm);

    val = to_bcd(s, (tm.tm_year / 100) + 19);
    rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
    rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
}

static void rtc_save(QEMUFile *f, void *opaque)
{
    RTCState *s = opaque;

    qemu_put_buffer(f, s->cmos_data, 128);
    qemu_put_8s(f, &s->cmos_index);

    qemu_put_be32(f, s->current_tm.tm_sec);
    qemu_put_be32(f, s->current_tm.tm_min);
    qemu_put_be32(f, s->current_tm.tm_hour);
    qemu_put_be32(f, s->current_tm.tm_wday);
    qemu_put_be32(f, s->current_tm.tm_mday);
    qemu_put_be32(f, s->current_tm.tm_mon);
    qemu_put_be32(f, s->current_tm.tm_year);

    qemu_put_timer(f, s->periodic_timer);
    qemu_put_be64(f, s->next_periodic_time);

    qemu_put_be64(f, s->next_second_time);
    qemu_put_timer(f, s->second_timer);
    qemu_put_timer(f, s->second_timer2);
}

static int rtc_load(QEMUFile *f, void *opaque, int version_id)
{
    RTCState *s = opaque;

    if (version_id != 1)
        return -EINVAL;

    qemu_get_buffer(f, s->cmos_data, 128);
    qemu_get_8s(f, &s->cmos_index);

    s->current_tm.tm_sec=qemu_get_be32(f);
    s->current_tm.tm_min=qemu_get_be32(f);
    s->current_tm.tm_hour=qemu_get_be32(f);
    s->current_tm.tm_wday=qemu_get_be32(f);
    s->current_tm.tm_mday=qemu_get_be32(f);
    s->current_tm.tm_mon=qemu_get_be32(f);
    s->current_tm.tm_year=qemu_get_be32(f);

    qemu_get_timer(f, s->periodic_timer);
    s->next_periodic_time=qemu_get_be64(f);

    s->next_second_time=qemu_get_be64(f);
    qemu_get_timer(f, s->second_timer);
    qemu_get_timer(f, s->second_timer2);
    return 0;
}

RTCState *rtc_init(int base, qemu_irq irq)
{
    RTCState *s;

    s = qemu_mallocz(sizeof(RTCState));
    if (!s)
        return NULL;

    s->irq = irq;
    s->cmos_data[RTC_REG_A] = 0x26;
    s->cmos_data[RTC_REG_B] = 0x02;
    s->cmos_data[RTC_REG_C] = 0x00;
    s->cmos_data[RTC_REG_D] = 0x80;

    rtc_set_date_from_host(s);

    s->periodic_timer = qemu_new_timer(vm_clock,
                                       rtc_periodic_timer, s);
    s->second_timer = qemu_new_timer(vm_clock,
                                     rtc_update_second, s);
    s->second_timer2 = qemu_new_timer(vm_clock,
                                      rtc_update_second2, s);

    s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
    qemu_mod_timer(s->second_timer2, s->next_second_time);

    register_ioport_write(base, 2, 1, cmos_ioport_write, s);
    register_ioport_read(base, 2, 1, cmos_ioport_read, s);

    register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
    return s;
}

/* Memory mapped interface */
static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
{
    RTCState *s = opaque;

    return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
}

static void cmos_mm_writeb (void *opaque,
                            target_phys_addr_t addr, uint32_t value)
{
    RTCState *s = opaque;

    cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}

static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
{
    RTCState *s = opaque;
    uint32_t val;

    val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif
    return val;
}

static void cmos_mm_writew (void *opaque,
                            target_phys_addr_t addr, uint32_t value)
{
    RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap16(value);
#endif
    cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}

static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
{
    RTCState *s = opaque;
    uint32_t val;

    val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    return val;
}

static void cmos_mm_writel (void *opaque,
                            target_phys_addr_t addr, uint32_t value)
{
    RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap32(value);
#endif
    cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value);
}

static CPUReadMemoryFunc *rtc_mm_read[] = {
    &cmos_mm_readb,
    &cmos_mm_readw,
    &cmos_mm_readl,
};

static CPUWriteMemoryFunc *rtc_mm_write[] = {
    &cmos_mm_writeb,
    &cmos_mm_writew,
    &cmos_mm_writel,
};

RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
{
    RTCState *s;
    int io_memory;

    s = qemu_mallocz(sizeof(RTCState));
    if (!s)
        return NULL;

    s->irq = irq;
    s->cmos_data[RTC_REG_A] = 0x26;
    s->cmos_data[RTC_REG_B] = 0x02;
    s->cmos_data[RTC_REG_C] = 0x00;
    s->cmos_data[RTC_REG_D] = 0x80;
    s->base = base;

    rtc_set_date_from_host(s);

    s->periodic_timer = qemu_new_timer(vm_clock,
                                       rtc_periodic_timer, s);
    s->second_timer = qemu_new_timer(vm_clock,
                                     rtc_update_second, s);
    s->second_timer2 = qemu_new_timer(vm_clock,
                                      rtc_update_second2, s);

    s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
    qemu_mod_timer(s->second_timer2, s->next_second_time);

    io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
    cpu_register_physical_memory(base, 2 << it_shift, io_memory);

    register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
    return s;
}
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU MC146818 RTC emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "qemu-timer.h"
	26	#include "sysemu.h"
	27	#include "pc.h"
	28	#include "isa.h"
80cabfad FB	29
	30	//#define DEBUG_CMOS
	31
	32	#define RTC_SECONDS 0
	33	#define RTC_SECONDS_ALARM 1
	34	#define RTC_MINUTES 2
	35	#define RTC_MINUTES_ALARM 3
	36	#define RTC_HOURS 4
	37	#define RTC_HOURS_ALARM 5
	38	#define RTC_ALARM_DONT_CARE 0xC0
	39
	40	#define RTC_DAY_OF_WEEK 6
	41	#define RTC_DAY_OF_MONTH 7
	42	#define RTC_MONTH 8
	43	#define RTC_YEAR 9
	44
	45	#define RTC_REG_A 10
	46	#define RTC_REG_B 11
	47	#define RTC_REG_C 12
	48	#define RTC_REG_D 13
	49
dff38e7b	50	#define REG_A_UIP 0x80
80cabfad	51
dff38e7b FB	52	#define REG_B_SET 0x80
	53	#define REG_B_PIE 0x40
	54	#define REG_B_AIE 0x20
	55	#define REG_B_UIE 0x10
	56
	57	struct RTCState {
	58	uint8_t cmos_data[128];
	59	uint8_t cmos_index;
43f493af	60	struct tm current_tm;
d537cf6c	61	qemu_irq irq;
2ca9d013	62	target_phys_addr_t base;
18c6e2ff	63	int it_shift;
dff38e7b FB	64	/* periodic timer */
	65	QEMUTimer *periodic_timer;
	66	int64_t next_periodic_time;
	67	/* second update */
	68	int64_t next_second_time;
	69	QEMUTimer *second_timer;
	70	QEMUTimer *second_timer2;
	71	};
	72
	73	static void rtc_set_time(RTCState *s);
dff38e7b FB	74	static void rtc_copy_date(RTCState *s);
	75
	76	static void rtc_timer_update(RTCState *s, int64_t current_time)
	77	{
	78	int period_code, period;
	79	int64_t cur_clock, next_irq_clock;
	80
	81	period_code = s->cmos_data[RTC_REG_A] & 0x0f;
5fafdf24	82	if (period_code != 0 &&
dff38e7b FB	83	(s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
	84	if (period_code <= 2)
	85	period_code += 7;
	86	/* period in 32 Khz cycles */
	87	period = 1 << (period_code - 1);
	88	/* compute 32 khz clock */
	89	cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
	90	next_irq_clock = (cur_clock & ~(period - 1)) + period;
	91	s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1;
	92	qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
	93	} else {
	94	qemu_del_timer(s->periodic_timer);
	95	}
	96	}
	97
	98	static void rtc_periodic_timer(void *opaque)
	99	{
	100	RTCState *s = opaque;
	101
	102	rtc_timer_update(s, s->next_periodic_time);
	103	s->cmos_data[RTC_REG_C] \|= 0xc0;
d537cf6c	104	qemu_irq_raise(s->irq);
dff38e7b	105	}
80cabfad	106
b41a2cd1	107	static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
80cabfad	108	{
b41a2cd1	109	RTCState *s = opaque;
80cabfad FB	110
	111	if ((addr & 1) == 0) {
	112	s->cmos_index = data & 0x7f;
	113	} else {
	114	#ifdef DEBUG_CMOS
	115	printf("cmos: write index=0x%02x val=0x%02x\n",
	116	s->cmos_index, data);
3b46e624	117	#endif
dff38e7b	118	switch(s->cmos_index) {
80cabfad FB	119	case RTC_SECONDS_ALARM:
	120	case RTC_MINUTES_ALARM:
	121	case RTC_HOURS_ALARM:
	122	/* XXX: not supported */
	123	s->cmos_data[s->cmos_index] = data;
	124	break;
	125	case RTC_SECONDS:
	126	case RTC_MINUTES:
	127	case RTC_HOURS:
	128	case RTC_DAY_OF_WEEK:
	129	case RTC_DAY_OF_MONTH:
	130	case RTC_MONTH:
	131	case RTC_YEAR:
	132	s->cmos_data[s->cmos_index] = data;
dff38e7b FB	133	/* if in set mode, do not update the time */
	134	if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
	135	rtc_set_time(s);
	136	}
80cabfad FB	137	break;
80cabfad FB	138	case RTC_REG_A:
dff38e7b FB	139	/* UIP bit is read only */
	140	s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) \|
	141	(s->cmos_data[RTC_REG_A] & REG_A_UIP);
	142	rtc_timer_update(s, qemu_get_clock(vm_clock));
	143	break;
80cabfad	144	case RTC_REG_B:
dff38e7b FB	145	if (data & REG_B_SET) {
	146	/* set mode: reset UIP mode */
	147	s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
	148	data &= ~REG_B_UIE;
	149	} else {
	150	/* if disabling set mode, update the time */
	151	if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
	152	rtc_set_time(s);
	153	}
	154	}
	155	s->cmos_data[RTC_REG_B] = data;
	156	rtc_timer_update(s, qemu_get_clock(vm_clock));
80cabfad FB	157	break;
	158	case RTC_REG_C:
	159	case RTC_REG_D:
	160	/* cannot write to them */
	161	break;
	162	default:
	163	s->cmos_data[s->cmos_index] = data;
	164	break;
	165	}
	166	}
	167	}
	168
dff38e7b	169	static inline int to_bcd(RTCState *s, int a)
80cabfad	170	{
dff38e7b FB	171	if (s->cmos_data[RTC_REG_B] & 0x04) {
	172	return a;
	173	} else {
	174	return ((a / 10) << 4) \| (a % 10);
	175	}
80cabfad FB	176	}
80cabfad FB	177
dff38e7b	178	static inline int from_bcd(RTCState *s, int a)
80cabfad	179	{
dff38e7b FB	180	if (s->cmos_data[RTC_REG_B] & 0x04) {
	181	return a;
	182	} else {
	183	return ((a >> 4) * 10) + (a & 0x0f);
	184	}
	185	}
	186
	187	static void rtc_set_time(RTCState *s)
	188	{
43f493af	189	struct tm *tm = &s->current_tm;
dff38e7b FB	190
	191	tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
	192	tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
43f493af FB	193	tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
	194	if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
	195	(s->cmos_data[RTC_HOURS] & 0x80)) {
	196	tm->tm_hour += 12;
	197	}
dff38e7b FB	198	tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
	199	tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
	200	tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
	201	tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
43f493af FB	202	}
	203
	204	static void rtc_copy_date(RTCState *s)
	205	{
	206	const struct tm *tm = &s->current_tm;
dff38e7b	207
43f493af FB	208	s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
	209	s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
	210	if (s->cmos_data[RTC_REG_B] & 0x02) {
	211	/* 24 hour format */
	212	s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
	213	} else {
	214	/* 12 hour format */
	215	s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
	216	if (tm->tm_hour >= 12)
	217	s->cmos_data[RTC_HOURS] \|= 0x80;
	218	}
	219	s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
	220	s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
	221	s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
	222	s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
	223	}
	224
	225	/* month is between 0 and 11. */
	226	static int get_days_in_month(int month, int year)
	227	{
5fafdf24 TS	228	static const int days_tab[12] = {
5fafdf24 TS	229	31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
43f493af FB	230	};
	231	int d;
	232	if ((unsigned )month >= 12)
	233	return 31;
	234	d = days_tab[month];
	235	if (month == 1) {
	236	if ((year % 4) == 0 && ((year % 100) != 0 \|\| (year % 400) == 0))
	237	d++;
	238	}
	239	return d;
	240	}
	241
	242	/* update 'tm' to the next second */
	243	static void rtc_next_second(struct tm *tm)
	244	{
	245	int days_in_month;
	246
	247	tm->tm_sec++;
	248	if ((unsigned)tm->tm_sec >= 60) {
	249	tm->tm_sec = 0;
	250	tm->tm_min++;
	251	if ((unsigned)tm->tm_min >= 60) {
	252	tm->tm_min = 0;
	253	tm->tm_hour++;
	254	if ((unsigned)tm->tm_hour >= 24) {
	255	tm->tm_hour = 0;
	256	/* next day */
	257	tm->tm_wday++;
	258	if ((unsigned)tm->tm_wday >= 7)
	259	tm->tm_wday = 0;
5fafdf24	260	days_in_month = get_days_in_month(tm->tm_mon,
43f493af FB	261	tm->tm_year + 1900);
	262	tm->tm_mday++;
	263	if (tm->tm_mday < 1) {
	264	tm->tm_mday = 1;
	265	} else if (tm->tm_mday > days_in_month) {
	266	tm->tm_mday = 1;
	267	tm->tm_mon++;
	268	if (tm->tm_mon >= 12) {
	269	tm->tm_mon = 0;
	270	tm->tm_year++;
	271	}
	272	}
	273	}
	274	}
	275	}
dff38e7b FB	276	}
dff38e7b FB	277
43f493af	278
dff38e7b FB	279	static void rtc_update_second(void *opaque)
	280	{
	281	RTCState *s = opaque;
4721c457	282	int64_t delay;
dff38e7b FB	283
	284	/* if the oscillator is not in normal operation, we do not update */
	285	if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
	286	s->next_second_time += ticks_per_sec;
	287	qemu_mod_timer(s->second_timer, s->next_second_time);
	288	} else {
43f493af	289	rtc_next_second(&s->current_tm);
3b46e624	290
dff38e7b FB	291	if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
	292	/* update in progress bit */
	293	s->cmos_data[RTC_REG_A] \|= REG_A_UIP;
	294	}
4721c457 FB	295	/* should be 244 us = 8 / 32768 seconds, but currently the
	296	timers do not have the necessary resolution. */
	297	delay = (ticks_per_sec * 1) / 100;
	298	if (delay < 1)
	299	delay = 1;
5fafdf24	300	qemu_mod_timer(s->second_timer2,
4721c457	301	s->next_second_time + delay);
dff38e7b FB	302	}
	303	}
	304
	305	static void rtc_update_second2(void *opaque)
	306	{
	307	RTCState *s = opaque;
dff38e7b FB	308
	309	if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
	310	rtc_copy_date(s);
	311	}
	312
	313	/* check alarm */
	314	if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
	315	if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 \|\|
43f493af	316	s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
dff38e7b	317	((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 \|\|
43f493af	318	s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
dff38e7b	319	((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 \|\|
43f493af	320	s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
dff38e7b	321
5fafdf24	322	s->cmos_data[RTC_REG_C] \|= 0xa0;
d537cf6c	323	qemu_irq_raise(s->irq);
dff38e7b FB	324	}
	325	}
	326
	327	/* update ended interrupt */
	328	if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
5fafdf24	329	s->cmos_data[RTC_REG_C] \|= 0x90;
d537cf6c	330	qemu_irq_raise(s->irq);
dff38e7b FB	331	}
	332
	333	/* clear update in progress bit */
	334	s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
	335
	336	s->next_second_time += ticks_per_sec;
	337	qemu_mod_timer(s->second_timer, s->next_second_time);
80cabfad FB	338	}
80cabfad FB	339
b41a2cd1	340	static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
80cabfad	341	{
b41a2cd1	342	RTCState *s = opaque;
80cabfad FB	343	int ret;
	344	if ((addr & 1) == 0) {
	345	return 0xff;
	346	} else {
	347	switch(s->cmos_index) {
	348	case RTC_SECONDS:
	349	case RTC_MINUTES:
	350	case RTC_HOURS:
	351	case RTC_DAY_OF_WEEK:
	352	case RTC_DAY_OF_MONTH:
	353	case RTC_MONTH:
	354	case RTC_YEAR:
80cabfad FB	355	ret = s->cmos_data[s->cmos_index];
	356	break;
	357	case RTC_REG_A:
	358	ret = s->cmos_data[s->cmos_index];
80cabfad FB	359	break;
	360	case RTC_REG_C:
	361	ret = s->cmos_data[s->cmos_index];
d537cf6c	362	qemu_irq_lower(s->irq);
5fafdf24	363	s->cmos_data[RTC_REG_C] = 0x00;
80cabfad FB	364	break;
	365	default:
	366	ret = s->cmos_data[s->cmos_index];
	367	break;
	368	}
	369	#ifdef DEBUG_CMOS
	370	printf("cmos: read index=0x%02x val=0x%02x\n",
	371	s->cmos_index, ret);
	372	#endif
	373	return ret;
	374	}
	375	}
	376
dff38e7b FB	377	void rtc_set_memory(RTCState *s, int addr, int val)
	378	{
	379	if (addr >= 0 && addr <= 127)
	380	s->cmos_data[addr] = val;
	381	}
	382
	383	void rtc_set_date(RTCState s, const struct tm tm)
	384	{
43f493af	385	s->current_tm = *tm;
dff38e7b FB	386	rtc_copy_date(s);
	387	}
	388
ea55ffb3 TS	389	/* PC cmos mappings */
	390	#define REG_IBM_CENTURY_BYTE 0x32
	391	#define REG_IBM_PS2_CENTURY_BYTE 0x37
	392
9596ebb7	393	static void rtc_set_date_from_host(RTCState *s)
ea55ffb3	394	{
f6503059	395	struct tm tm;
ea55ffb3 TS	396	int val;
	397
	398	/* set the CMOS date */
f6503059 AZ	399	qemu_get_timedate(&tm, 0);
f6503059 AZ	400	rtc_set_date(s, &tm);
ea55ffb3	401
f6503059	402	val = to_bcd(s, (tm.tm_year / 100) + 19);
ea55ffb3 TS	403	rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
	404	rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
	405	}
	406
dff38e7b FB	407	static void rtc_save(QEMUFile f, void opaque)
	408	{
	409	RTCState *s = opaque;
	410
	411	qemu_put_buffer(f, s->cmos_data, 128);
	412	qemu_put_8s(f, &s->cmos_index);
3b46e624	413
bee8d684 TS	414	qemu_put_be32(f, s->current_tm.tm_sec);
	415	qemu_put_be32(f, s->current_tm.tm_min);
	416	qemu_put_be32(f, s->current_tm.tm_hour);
	417	qemu_put_be32(f, s->current_tm.tm_wday);
	418	qemu_put_be32(f, s->current_tm.tm_mday);
	419	qemu_put_be32(f, s->current_tm.tm_mon);
	420	qemu_put_be32(f, s->current_tm.tm_year);
dff38e7b FB	421
dff38e7b FB	422	qemu_put_timer(f, s->periodic_timer);
bee8d684	423	qemu_put_be64(f, s->next_periodic_time);
dff38e7b	424
bee8d684	425	qemu_put_be64(f, s->next_second_time);
dff38e7b FB	426	qemu_put_timer(f, s->second_timer);
dff38e7b FB	427	qemu_put_timer(f, s->second_timer2);
80cabfad FB	428	}
80cabfad FB	429
dff38e7b	430	static int rtc_load(QEMUFile f, void opaque, int version_id)
80cabfad	431	{
dff38e7b FB	432	RTCState *s = opaque;
	433
	434	if (version_id != 1)
	435	return -EINVAL;
80cabfad	436
dff38e7b FB	437	qemu_get_buffer(f, s->cmos_data, 128);
dff38e7b FB	438	qemu_get_8s(f, &s->cmos_index);
43f493af	439
bee8d684 TS	440	s->current_tm.tm_sec=qemu_get_be32(f);
	441	s->current_tm.tm_min=qemu_get_be32(f);
	442	s->current_tm.tm_hour=qemu_get_be32(f);
	443	s->current_tm.tm_wday=qemu_get_be32(f);
	444	s->current_tm.tm_mday=qemu_get_be32(f);
	445	s->current_tm.tm_mon=qemu_get_be32(f);
	446	s->current_tm.tm_year=qemu_get_be32(f);
dff38e7b FB	447
dff38e7b FB	448	qemu_get_timer(f, s->periodic_timer);
bee8d684	449	s->next_periodic_time=qemu_get_be64(f);
dff38e7b	450
bee8d684	451	s->next_second_time=qemu_get_be64(f);
dff38e7b FB	452	qemu_get_timer(f, s->second_timer);
	453	qemu_get_timer(f, s->second_timer2);
	454	return 0;
	455	}
	456
d537cf6c	457	RTCState *rtc_init(int base, qemu_irq irq)
dff38e7b FB	458	{
	459	RTCState *s;
	460
	461	s = qemu_mallocz(sizeof(RTCState));
	462	if (!s)
	463	return NULL;
80cabfad FB	464
	465	s->irq = irq;
	466	s->cmos_data[RTC_REG_A] = 0x26;
	467	s->cmos_data[RTC_REG_B] = 0x02;
	468	s->cmos_data[RTC_REG_C] = 0x00;
	469	s->cmos_data[RTC_REG_D] = 0x80;
	470
ea55ffb3 TS	471	rtc_set_date_from_host(s);
ea55ffb3 TS	472
5fafdf24	473	s->periodic_timer = qemu_new_timer(vm_clock,
dff38e7b	474	rtc_periodic_timer, s);
5fafdf24	475	s->second_timer = qemu_new_timer(vm_clock,
dff38e7b	476	rtc_update_second, s);
5fafdf24	477	s->second_timer2 = qemu_new_timer(vm_clock,
dff38e7b FB	478	rtc_update_second2, s);
	479
	480	s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
	481	qemu_mod_timer(s->second_timer2, s->next_second_time);
	482
b41a2cd1 FB	483	register_ioport_write(base, 2, 1, cmos_ioport_write, s);
b41a2cd1 FB	484	register_ioport_read(base, 2, 1, cmos_ioport_read, s);
dff38e7b FB	485
	486	register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
	487	return s;
80cabfad FB	488	}
80cabfad FB	489
2ca9d013	490	/* Memory mapped interface */
9596ebb7	491	static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
2ca9d013 TS	492	{
	493	RTCState *s = opaque;
	494
18c6e2ff	495	return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
2ca9d013 TS	496	}
2ca9d013 TS	497
9596ebb7 PB	498	static void cmos_mm_writeb (void *opaque,
9596ebb7 PB	499	target_phys_addr_t addr, uint32_t value)
2ca9d013 TS	500	{
	501	RTCState *s = opaque;
	502
18c6e2ff	503	cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
2ca9d013 TS	504	}
2ca9d013 TS	505
9596ebb7	506	static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
2ca9d013 TS	507	{
2ca9d013 TS	508	RTCState *s = opaque;
18c6e2ff	509	uint32_t val;
2ca9d013	510
18c6e2ff TS	511	val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
	512	#ifdef TARGET_WORDS_BIGENDIAN
	513	val = bswap16(val);
	514	#endif
	515	return val;
2ca9d013 TS	516	}
2ca9d013 TS	517
9596ebb7 PB	518	static void cmos_mm_writew (void *opaque,
9596ebb7 PB	519	target_phys_addr_t addr, uint32_t value)
2ca9d013 TS	520	{
2ca9d013 TS	521	RTCState *s = opaque;
18c6e2ff TS	522	#ifdef TARGET_WORDS_BIGENDIAN
	523	value = bswap16(value);
	524	#endif
	525	cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
2ca9d013 TS	526	}
2ca9d013 TS	527
9596ebb7	528	static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
2ca9d013 TS	529	{
2ca9d013 TS	530	RTCState *s = opaque;
18c6e2ff	531	uint32_t val;
2ca9d013	532
18c6e2ff TS	533	val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift);
	534	#ifdef TARGET_WORDS_BIGENDIAN
	535	val = bswap32(val);
	536	#endif
	537	return val;
2ca9d013 TS	538	}
2ca9d013 TS	539
9596ebb7 PB	540	static void cmos_mm_writel (void *opaque,
9596ebb7 PB	541	target_phys_addr_t addr, uint32_t value)
2ca9d013 TS	542	{
2ca9d013 TS	543	RTCState *s = opaque;
18c6e2ff TS	544	#ifdef TARGET_WORDS_BIGENDIAN
	545	value = bswap32(value);
	546	#endif
	547	cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value);
2ca9d013 TS	548	}
	549
	550	static CPUReadMemoryFunc *rtc_mm_read[] = {
	551	&cmos_mm_readb,
	552	&cmos_mm_readw,
	553	&cmos_mm_readl,
	554	};
	555
	556	static CPUWriteMemoryFunc *rtc_mm_write[] = {
	557	&cmos_mm_writeb,
	558	&cmos_mm_writew,
	559	&cmos_mm_writel,
	560	};
	561
18c6e2ff	562	RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
2ca9d013 TS	563	{
	564	RTCState *s;
	565	int io_memory;
	566
	567	s = qemu_mallocz(sizeof(RTCState));
	568	if (!s)
	569	return NULL;
	570
	571	s->irq = irq;
	572	s->cmos_data[RTC_REG_A] = 0x26;
	573	s->cmos_data[RTC_REG_B] = 0x02;
	574	s->cmos_data[RTC_REG_C] = 0x00;
	575	s->cmos_data[RTC_REG_D] = 0x80;
	576	s->base = base;
	577
	578	rtc_set_date_from_host(s);
	579
	580	s->periodic_timer = qemu_new_timer(vm_clock,
	581	rtc_periodic_timer, s);
	582	s->second_timer = qemu_new_timer(vm_clock,
	583	rtc_update_second, s);
	584	s->second_timer2 = qemu_new_timer(vm_clock,
	585	rtc_update_second2, s);
	586
	587	s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
	588	qemu_mod_timer(s->second_timer2, s->next_second_time);
	589
	590	io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
18c6e2ff	591	cpu_register_physical_memory(base, 2 << it_shift, io_memory);
2ca9d013 TS	592
	593	register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
	594	return s;
	595	}