[mirror_qemu.git] / hw / mc146818rtc.c

/*
 * QEMU MC146818 RTC emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_CMOS

#define RTC_SECONDS             0
#define RTC_SECONDS_ALARM       1
#define RTC_MINUTES             2
#define RTC_MINUTES_ALARM       3
#define RTC_HOURS               4
#define RTC_HOURS_ALARM         5
#define RTC_ALARM_DONT_CARE    0xC0

#define RTC_DAY_OF_WEEK         6
#define RTC_DAY_OF_MONTH        7
#define RTC_MONTH               8
#define RTC_YEAR                9

#define RTC_REG_A               10
#define RTC_REG_B               11
#define RTC_REG_C               12
#define RTC_REG_D               13

#define REG_A_UIP 0x80

#define REG_B_SET 0x80
#define REG_B_PIE 0x40
#define REG_B_AIE 0x20
#define REG_B_UIE 0x10

struct RTCState {
    uint8_t cmos_data[128];
    uint8_t cmos_index;
    struct tm current_tm;
    qemu_irq irq;
    target_phys_addr_t base;
    int it_shift;
    /* periodic timer */
    QEMUTimer *periodic_timer;
    int64_t next_periodic_time;
    /* second update */
    int64_t next_second_time;
    QEMUTimer *second_timer;
    QEMUTimer *second_timer2;
};

static void rtc_set_time(RTCState *s);
static void rtc_copy_date(RTCState *s);

static void rtc_timer_update(RTCState *s, int64_t current_time)
{
    int period_code, period;
    int64_t cur_clock, next_irq_clock;

    period_code = s->cmos_data[RTC_REG_A] & 0x0f;
    if (period_code != 0 &&
        (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
        if (period_code <= 2)
            period_code += 7;
        /* period in 32 Khz cycles */
        period = 1 << (period_code - 1);
        /* compute 32 khz clock */
        cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
        next_irq_clock = (cur_clock & ~(period - 1)) + period;
        s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1;
        qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
    } else {
        qemu_del_timer(s->periodic_timer);
    }
}

static void rtc_periodic_timer(void *opaque)
{
    RTCState *s = opaque;

    rtc_timer_update(s, s->next_periodic_time);
    s->cmos_data[RTC_REG_C] |= 0xc0;
    qemu_irq_raise(s->irq);
}

static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
{
    RTCState *s = opaque;

    if ((addr & 1) == 0) {
        s->cmos_index = data & 0x7f;
    } else {
#ifdef DEBUG_CMOS
        printf("cmos: write index=0x%02x val=0x%02x\n",
               s->cmos_index, data);
#endif
        switch(s->cmos_index) {
        case RTC_SECONDS_ALARM:
        case RTC_MINUTES_ALARM:
        case RTC_HOURS_ALARM:
            /* XXX: not supported */
            s->cmos_data[s->cmos_index] = data;
            break;
        case RTC_SECONDS:
        case RTC_MINUTES:
        case RTC_HOURS:
        case RTC_DAY_OF_WEEK:
        case RTC_DAY_OF_MONTH:
        case RTC_MONTH:
        case RTC_YEAR:
            s->cmos_data[s->cmos_index] = data;
            /* if in set mode, do not update the time */
            if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
                rtc_set_time(s);
            }
            break;
        case RTC_REG_A:
            /* UIP bit is read only */
            s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
                (s->cmos_data[RTC_REG_A] & REG_A_UIP);
            rtc_timer_update(s, qemu_get_clock(vm_clock));
            break;
        case RTC_REG_B:
            if (data & REG_B_SET) {
                /* set mode: reset UIP mode */
                s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
                data &= ~REG_B_UIE;
            } else {
                /* if disabling set mode, update the time */
                if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
                    rtc_set_time(s);
                }
            }
            s->cmos_data[RTC_REG_B] = data;
            rtc_timer_update(s, qemu_get_clock(vm_clock));
            break;
        case RTC_REG_C:
        case RTC_REG_D:
            /* cannot write to them */
            break;
        default:
            s->cmos_data[s->cmos_index] = data;
            break;
        }
    }
}

static inline int to_bcd(RTCState *s, int a)
{
    if (s->cmos_data[RTC_REG_B] & 0x04) {
        return a;
    } else {
        return ((a / 10) << 4) | (a % 10);
    }
}

static inline int from_bcd(RTCState *s, int a)
{
    if (s->cmos_data[RTC_REG_B] & 0x04) {
        return a;
    } else {
        return ((a >> 4) * 10) + (a & 0x0f);
    }
}

static void rtc_set_time(RTCState *s)
{
    struct tm *tm = &s->current_tm;

    tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
    tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
    tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
    if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
        (s->cmos_data[RTC_HOURS] & 0x80)) {
        tm->tm_hour += 12;
    }
    tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
    tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
    tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
    tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
}

static void rtc_copy_date(RTCState *s)
{
    const struct tm *tm = &s->current_tm;

    s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
    s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
    if (s->cmos_data[RTC_REG_B] & 0x02) {
        /* 24 hour format */
        s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
    } else {
        /* 12 hour format */
        s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
        if (tm->tm_hour >= 12)
            s->cmos_data[RTC_HOURS] |= 0x80;
    }
    s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
    s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
    s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
    s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
}

/* month is between 0 and 11. */
static int get_days_in_month(int month, int year)
{
    static const int days_tab[12] = {
        31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
    };
    int d;
    if ((unsigned )month >= 12)
        return 31;
    d = days_tab[month];
    if (month == 1) {
        if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
            d++;
    }
    return d;
}

/* update 'tm' to the next second */
static void rtc_next_second(struct tm *tm)
{
    int days_in_month;

    tm->tm_sec++;
    if ((unsigned)tm->tm_sec >= 60) {
        tm->tm_sec = 0;
        tm->tm_min++;
        if ((unsigned)tm->tm_min >= 60) {
            tm->tm_min = 0;
            tm->tm_hour++;
            if ((unsigned)tm->tm_hour >= 24) {
                tm->tm_hour = 0;
                /* next day */
                tm->tm_wday++;
                if ((unsigned)tm->tm_wday >= 7)
                    tm->tm_wday = 0;
                days_in_month = get_days_in_month(tm->tm_mon,
                                                  tm->tm_year + 1900);
                tm->tm_mday++;
                if (tm->tm_mday < 1) {
                    tm->tm_mday = 1;
                } else if (tm->tm_mday > days_in_month) {
                    tm->tm_mday = 1;
                    tm->tm_mon++;
                    if (tm->tm_mon >= 12) {
                        tm->tm_mon = 0;
                        tm->tm_year++;
                    }
                }
            }
        }
    }
}


static void rtc_update_second(void *opaque)
{
    RTCState *s = opaque;
    int64_t delay;

    /* if the oscillator is not in normal operation, we do not update */
    if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
        s->next_second_time += ticks_per_sec;
        qemu_mod_timer(s->second_timer, s->next_second_time);
    } else {
        rtc_next_second(&s->current_tm);

        if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
            /* update in progress bit */
            s->cmos_data[RTC_REG_A] |= REG_A_UIP;
        }
        /* should be 244 us = 8 / 32768 seconds, but currently the
           timers do not have the necessary resolution. */
        delay = (ticks_per_sec * 1) / 100;
        if (delay < 1)
            delay = 1;
        qemu_mod_timer(s->second_timer2,
                       s->next_second_time + delay);
    }
}

static void rtc_update_second2(void *opaque)
{
    RTCState *s = opaque;

    if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
        rtc_copy_date(s);
    }

    /* check alarm */
    if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
        if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
             s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
            ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
             s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
            ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
             s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {

            s->cmos_data[RTC_REG_C] |= 0xa0;
            qemu_irq_raise(s->irq);
        }
    }

    /* update ended interrupt */
    if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
        s->cmos_data[RTC_REG_C] |= 0x90;
        qemu_irq_raise(s->irq);
    }

    /* clear update in progress bit */
    s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;

    s->next_second_time += ticks_per_sec;
    qemu_mod_timer(s->second_timer, s->next_second_time);
}

static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
{
    RTCState *s = opaque;
    int ret;
    if ((addr & 1) == 0) {
        return 0xff;
    } else {
        switch(s->cmos_index) {
        case RTC_SECONDS:
        case RTC_MINUTES:
        case RTC_HOURS:
        case RTC_DAY_OF_WEEK:
        case RTC_DAY_OF_MONTH:
        case RTC_MONTH:
        case RTC_YEAR:
            ret = s->cmos_data[s->cmos_index];
            break;
        case RTC_REG_A:
            ret = s->cmos_data[s->cmos_index];
            break;
        case RTC_REG_C:
            ret = s->cmos_data[s->cmos_index];
            qemu_irq_lower(s->irq);
            s->cmos_data[RTC_REG_C] = 0x00;
            break;
        default:
            ret = s->cmos_data[s->cmos_index];
            break;
        }
#ifdef DEBUG_CMOS
        printf("cmos: read index=0x%02x val=0x%02x\n",
               s->cmos_index, ret);
#endif
        return ret;
    }
}

void rtc_set_memory(RTCState *s, int addr, int val)
{
    if (addr >= 0 && addr <= 127)
        s->cmos_data[addr] = val;
}

void rtc_set_date(RTCState *s, const struct tm *tm)
{
    s->current_tm = *tm;
    rtc_copy_date(s);
}

/* PC cmos mappings */
#define REG_IBM_CENTURY_BYTE        0x32
#define REG_IBM_PS2_CENTURY_BYTE    0x37

void rtc_set_date_from_host(RTCState *s)
{
    time_t ti;
    struct tm *tm;
    int val;

    /* set the CMOS date */
    if (rtc_start_date == -1) {
        time(&ti);
        if (rtc_utc)
            tm = gmtime(&ti);
        else
            tm = localtime(&ti);
    } else {
        ti = rtc_start_date;
        tm = gmtime(&ti);
    }
    rtc_set_date(s, tm);

    val = to_bcd(s, (tm->tm_year / 100) + 19);
    rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
    rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
}

static void rtc_save(QEMUFile *f, void *opaque)
{
    RTCState *s = opaque;

    qemu_put_buffer(f, s->cmos_data, 128);
    qemu_put_8s(f, &s->cmos_index);

    qemu_put_be32s(f, &s->current_tm.tm_sec);
    qemu_put_be32s(f, &s->current_tm.tm_min);
    qemu_put_be32s(f, &s->current_tm.tm_hour);
    qemu_put_be32s(f, &s->current_tm.tm_wday);
    qemu_put_be32s(f, &s->current_tm.tm_mday);
    qemu_put_be32s(f, &s->current_tm.tm_mon);
    qemu_put_be32s(f, &s->current_tm.tm_year);

    qemu_put_timer(f, s->periodic_timer);
    qemu_put_be64s(f, &s->next_periodic_time);

    qemu_put_be64s(f, &s->next_second_time);
    qemu_put_timer(f, s->second_timer);
    qemu_put_timer(f, s->second_timer2);
}

static int rtc_load(QEMUFile *f, void *opaque, int version_id)
{
    RTCState *s = opaque;

    if (version_id != 1)
        return -EINVAL;

    qemu_get_buffer(f, s->cmos_data, 128);
    qemu_get_8s(f, &s->cmos_index);

    qemu_get_be32s(f, &s->current_tm.tm_sec);
    qemu_get_be32s(f, &s->current_tm.tm_min);
    qemu_get_be32s(f, &s->current_tm.tm_hour);
    qemu_get_be32s(f, &s->current_tm.tm_wday);
    qemu_get_be32s(f, &s->current_tm.tm_mday);
    qemu_get_be32s(f, &s->current_tm.tm_mon);
    qemu_get_be32s(f, &s->current_tm.tm_year);

    qemu_get_timer(f, s->periodic_timer);
    qemu_get_be64s(f, &s->next_periodic_time);

    qemu_get_be64s(f, &s->next_second_time);
    qemu_get_timer(f, s->second_timer);
    qemu_get_timer(f, s->second_timer2);
    return 0;
}

RTCState *rtc_init(int base, qemu_irq irq)
{
    RTCState *s;

    s = qemu_mallocz(sizeof(RTCState));
    if (!s)
        return NULL;

    s->irq = irq;
    s->cmos_data[RTC_REG_A] = 0x26;
    s->cmos_data[RTC_REG_B] = 0x02;
    s->cmos_data[RTC_REG_C] = 0x00;
    s->cmos_data[RTC_REG_D] = 0x80;

    rtc_set_date_from_host(s);

    s->periodic_timer = qemu_new_timer(vm_clock,
                                       rtc_periodic_timer, s);
    s->second_timer = qemu_new_timer(vm_clock,
                                     rtc_update_second, s);
    s->second_timer2 = qemu_new_timer(vm_clock,
                                      rtc_update_second2, s);

    s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
    qemu_mod_timer(s->second_timer2, s->next_second_time);

    register_ioport_write(base, 2, 1, cmos_ioport_write, s);
    register_ioport_read(base, 2, 1, cmos_ioport_read, s);

    register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
    return s;
}

/* Memory mapped interface */
uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
{
    RTCState *s = opaque;

    return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
}

void cmos_mm_writeb (void *opaque,
                     target_phys_addr_t addr, uint32_t value)
{
    RTCState *s = opaque;

    cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}

uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
{
    RTCState *s = opaque;
    uint32_t val;

    val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif
    return val;
}

void cmos_mm_writew (void *opaque,
                     target_phys_addr_t addr, uint32_t value)
{
    RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap16(value);
#endif
    cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}

uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
{
    RTCState *s = opaque;
    uint32_t val;

    val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    return val;
}

void cmos_mm_writel (void *opaque,
                     target_phys_addr_t addr, uint32_t value)
{
    RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap32(value);
#endif
    cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value);
}

static CPUReadMemoryFunc *rtc_mm_read[] = {
    &cmos_mm_readb,
    &cmos_mm_readw,
    &cmos_mm_readl,
};

static CPUWriteMemoryFunc *rtc_mm_write[] = {
    &cmos_mm_writeb,
    &cmos_mm_writew,
    &cmos_mm_writel,
};

RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
{
    RTCState *s;
    int io_memory;

    s = qemu_mallocz(sizeof(RTCState));
    if (!s)
        return NULL;

    s->irq = irq;
    s->cmos_data[RTC_REG_A] = 0x26;
    s->cmos_data[RTC_REG_B] = 0x02;
    s->cmos_data[RTC_REG_C] = 0x00;
    s->cmos_data[RTC_REG_D] = 0x80;
    s->base = base;

    rtc_set_date_from_host(s);

    s->periodic_timer = qemu_new_timer(vm_clock,
                                       rtc_periodic_timer, s);
    s->second_timer = qemu_new_timer(vm_clock,
                                     rtc_update_second, s);
    s->second_timer2 = qemu_new_timer(vm_clock,
                                      rtc_update_second2, s);

    s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
    qemu_mod_timer(s->second_timer2, s->next_second_time);

    io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
    cpu_register_physical_memory(base, 2 << it_shift, io_memory);

    register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
    return s;
}
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU MC146818 RTC emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80cabfad FB	24	#include "vl.h"
	25
	26	//#define DEBUG_CMOS
	27
	28	#define RTC_SECONDS 0
	29	#define RTC_SECONDS_ALARM 1
	30	#define RTC_MINUTES 2
	31	#define RTC_MINUTES_ALARM 3
	32	#define RTC_HOURS 4
	33	#define RTC_HOURS_ALARM 5
	34	#define RTC_ALARM_DONT_CARE 0xC0
	35
	36	#define RTC_DAY_OF_WEEK 6
	37	#define RTC_DAY_OF_MONTH 7
	38	#define RTC_MONTH 8
	39	#define RTC_YEAR 9
	40
	41	#define RTC_REG_A 10
	42	#define RTC_REG_B 11
	43	#define RTC_REG_C 12
	44	#define RTC_REG_D 13
	45
dff38e7b	46	#define REG_A_UIP 0x80
80cabfad	47
dff38e7b FB	48	#define REG_B_SET 0x80
	49	#define REG_B_PIE 0x40
	50	#define REG_B_AIE 0x20
	51	#define REG_B_UIE 0x10
	52
	53	struct RTCState {
	54	uint8_t cmos_data[128];
	55	uint8_t cmos_index;
43f493af	56	struct tm current_tm;
d537cf6c	57	qemu_irq irq;
2ca9d013	58	target_phys_addr_t base;
18c6e2ff	59	int it_shift;
dff38e7b FB	60	/* periodic timer */
	61	QEMUTimer *periodic_timer;
	62	int64_t next_periodic_time;
	63	/* second update */
	64	int64_t next_second_time;
	65	QEMUTimer *second_timer;
	66	QEMUTimer *second_timer2;
	67	};
	68
	69	static void rtc_set_time(RTCState *s);
dff38e7b FB	70	static void rtc_copy_date(RTCState *s);
	71
	72	static void rtc_timer_update(RTCState *s, int64_t current_time)
	73	{
	74	int period_code, period;
	75	int64_t cur_clock, next_irq_clock;
	76
	77	period_code = s->cmos_data[RTC_REG_A] & 0x0f;
5fafdf24	78	if (period_code != 0 &&
dff38e7b FB	79	(s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
	80	if (period_code <= 2)
	81	period_code += 7;
	82	/* period in 32 Khz cycles */
	83	period = 1 << (period_code - 1);
	84	/* compute 32 khz clock */
	85	cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
	86	next_irq_clock = (cur_clock & ~(period - 1)) + period;
	87	s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1;
	88	qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
	89	} else {
	90	qemu_del_timer(s->periodic_timer);
	91	}
	92	}
	93
	94	static void rtc_periodic_timer(void *opaque)
	95	{
	96	RTCState *s = opaque;
	97
	98	rtc_timer_update(s, s->next_periodic_time);
	99	s->cmos_data[RTC_REG_C] \|= 0xc0;
d537cf6c	100	qemu_irq_raise(s->irq);
dff38e7b	101	}
80cabfad	102
b41a2cd1	103	static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
80cabfad	104	{
b41a2cd1	105	RTCState *s = opaque;
80cabfad FB	106
	107	if ((addr & 1) == 0) {
	108	s->cmos_index = data & 0x7f;
	109	} else {
	110	#ifdef DEBUG_CMOS
	111	printf("cmos: write index=0x%02x val=0x%02x\n",
	112	s->cmos_index, data);
3b46e624	113	#endif
dff38e7b	114	switch(s->cmos_index) {
80cabfad FB	115	case RTC_SECONDS_ALARM:
	116	case RTC_MINUTES_ALARM:
	117	case RTC_HOURS_ALARM:
	118	/* XXX: not supported */
	119	s->cmos_data[s->cmos_index] = data;
	120	break;
	121	case RTC_SECONDS:
	122	case RTC_MINUTES:
	123	case RTC_HOURS:
	124	case RTC_DAY_OF_WEEK:
	125	case RTC_DAY_OF_MONTH:
	126	case RTC_MONTH:
	127	case RTC_YEAR:
	128	s->cmos_data[s->cmos_index] = data;
dff38e7b FB	129	/* if in set mode, do not update the time */
	130	if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
	131	rtc_set_time(s);
	132	}
80cabfad FB	133	break;
80cabfad FB	134	case RTC_REG_A:
dff38e7b FB	135	/* UIP bit is read only */
	136	s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) \|
	137	(s->cmos_data[RTC_REG_A] & REG_A_UIP);
	138	rtc_timer_update(s, qemu_get_clock(vm_clock));
	139	break;
80cabfad	140	case RTC_REG_B:
dff38e7b FB	141	if (data & REG_B_SET) {
	142	/* set mode: reset UIP mode */
	143	s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
	144	data &= ~REG_B_UIE;
	145	} else {
	146	/* if disabling set mode, update the time */
	147	if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
	148	rtc_set_time(s);
	149	}
	150	}
	151	s->cmos_data[RTC_REG_B] = data;
	152	rtc_timer_update(s, qemu_get_clock(vm_clock));
80cabfad FB	153	break;
	154	case RTC_REG_C:
	155	case RTC_REG_D:
	156	/* cannot write to them */
	157	break;
	158	default:
	159	s->cmos_data[s->cmos_index] = data;
	160	break;
	161	}
	162	}
	163	}
	164
dff38e7b	165	static inline int to_bcd(RTCState *s, int a)
80cabfad	166	{
dff38e7b FB	167	if (s->cmos_data[RTC_REG_B] & 0x04) {
	168	return a;
	169	} else {
	170	return ((a / 10) << 4) \| (a % 10);
	171	}
80cabfad FB	172	}
80cabfad FB	173
dff38e7b	174	static inline int from_bcd(RTCState *s, int a)
80cabfad	175	{
dff38e7b FB	176	if (s->cmos_data[RTC_REG_B] & 0x04) {
	177	return a;
	178	} else {
	179	return ((a >> 4) * 10) + (a & 0x0f);
	180	}
	181	}
	182
	183	static void rtc_set_time(RTCState *s)
	184	{
43f493af	185	struct tm *tm = &s->current_tm;
dff38e7b FB	186
	187	tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
	188	tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
43f493af FB	189	tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
	190	if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
	191	(s->cmos_data[RTC_HOURS] & 0x80)) {
	192	tm->tm_hour += 12;
	193	}
dff38e7b FB	194	tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
	195	tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
	196	tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
	197	tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
43f493af FB	198	}
	199
	200	static void rtc_copy_date(RTCState *s)
	201	{
	202	const struct tm *tm = &s->current_tm;
dff38e7b	203
43f493af FB	204	s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
	205	s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
	206	if (s->cmos_data[RTC_REG_B] & 0x02) {
	207	/* 24 hour format */
	208	s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
	209	} else {
	210	/* 12 hour format */
	211	s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
	212	if (tm->tm_hour >= 12)
	213	s->cmos_data[RTC_HOURS] \|= 0x80;
	214	}
	215	s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
	216	s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
	217	s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
	218	s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
	219	}
	220
	221	/* month is between 0 and 11. */
	222	static int get_days_in_month(int month, int year)
	223	{
5fafdf24 TS	224	static const int days_tab[12] = {
5fafdf24 TS	225	31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
43f493af FB	226	};
	227	int d;
	228	if ((unsigned )month >= 12)
	229	return 31;
	230	d = days_tab[month];
	231	if (month == 1) {
	232	if ((year % 4) == 0 && ((year % 100) != 0 \|\| (year % 400) == 0))
	233	d++;
	234	}
	235	return d;
	236	}
	237
	238	/* update 'tm' to the next second */
	239	static void rtc_next_second(struct tm *tm)
	240	{
	241	int days_in_month;
	242
	243	tm->tm_sec++;
	244	if ((unsigned)tm->tm_sec >= 60) {
	245	tm->tm_sec = 0;
	246	tm->tm_min++;
	247	if ((unsigned)tm->tm_min >= 60) {
	248	tm->tm_min = 0;
	249	tm->tm_hour++;
	250	if ((unsigned)tm->tm_hour >= 24) {
	251	tm->tm_hour = 0;
	252	/* next day */
	253	tm->tm_wday++;
	254	if ((unsigned)tm->tm_wday >= 7)
	255	tm->tm_wday = 0;
5fafdf24	256	days_in_month = get_days_in_month(tm->tm_mon,
43f493af FB	257	tm->tm_year + 1900);
	258	tm->tm_mday++;
	259	if (tm->tm_mday < 1) {
	260	tm->tm_mday = 1;
	261	} else if (tm->tm_mday > days_in_month) {
	262	tm->tm_mday = 1;
	263	tm->tm_mon++;
	264	if (tm->tm_mon >= 12) {
	265	tm->tm_mon = 0;
	266	tm->tm_year++;
	267	}
	268	}
	269	}
	270	}
	271	}
dff38e7b FB	272	}
dff38e7b FB	273
43f493af	274
dff38e7b FB	275	static void rtc_update_second(void *opaque)
	276	{
	277	RTCState *s = opaque;
4721c457	278	int64_t delay;
dff38e7b FB	279
	280	/* if the oscillator is not in normal operation, we do not update */
	281	if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
	282	s->next_second_time += ticks_per_sec;
	283	qemu_mod_timer(s->second_timer, s->next_second_time);
	284	} else {
43f493af	285	rtc_next_second(&s->current_tm);
3b46e624	286
dff38e7b FB	287	if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
	288	/* update in progress bit */
	289	s->cmos_data[RTC_REG_A] \|= REG_A_UIP;
	290	}
4721c457 FB	291	/* should be 244 us = 8 / 32768 seconds, but currently the
	292	timers do not have the necessary resolution. */
	293	delay = (ticks_per_sec * 1) / 100;
	294	if (delay < 1)
	295	delay = 1;
5fafdf24	296	qemu_mod_timer(s->second_timer2,
4721c457	297	s->next_second_time + delay);
dff38e7b FB	298	}
	299	}
	300
	301	static void rtc_update_second2(void *opaque)
	302	{
	303	RTCState *s = opaque;
dff38e7b FB	304
	305	if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
	306	rtc_copy_date(s);
	307	}
	308
	309	/* check alarm */
	310	if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
	311	if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 \|\|
43f493af	312	s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
dff38e7b	313	((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 \|\|
43f493af	314	s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
dff38e7b	315	((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 \|\|
43f493af	316	s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
dff38e7b	317
5fafdf24	318	s->cmos_data[RTC_REG_C] \|= 0xa0;
d537cf6c	319	qemu_irq_raise(s->irq);
dff38e7b FB	320	}
	321	}
	322
	323	/* update ended interrupt */
	324	if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
5fafdf24	325	s->cmos_data[RTC_REG_C] \|= 0x90;
d537cf6c	326	qemu_irq_raise(s->irq);
dff38e7b FB	327	}
	328
	329	/* clear update in progress bit */
	330	s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
	331
	332	s->next_second_time += ticks_per_sec;
	333	qemu_mod_timer(s->second_timer, s->next_second_time);
80cabfad FB	334	}
80cabfad FB	335
b41a2cd1	336	static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
80cabfad	337	{
b41a2cd1	338	RTCState *s = opaque;
80cabfad FB	339	int ret;
	340	if ((addr & 1) == 0) {
	341	return 0xff;
	342	} else {
	343	switch(s->cmos_index) {
	344	case RTC_SECONDS:
	345	case RTC_MINUTES:
	346	case RTC_HOURS:
	347	case RTC_DAY_OF_WEEK:
	348	case RTC_DAY_OF_MONTH:
	349	case RTC_MONTH:
	350	case RTC_YEAR:
80cabfad FB	351	ret = s->cmos_data[s->cmos_index];
	352	break;
	353	case RTC_REG_A:
	354	ret = s->cmos_data[s->cmos_index];
80cabfad FB	355	break;
	356	case RTC_REG_C:
	357	ret = s->cmos_data[s->cmos_index];
d537cf6c	358	qemu_irq_lower(s->irq);
5fafdf24	359	s->cmos_data[RTC_REG_C] = 0x00;
80cabfad FB	360	break;
	361	default:
	362	ret = s->cmos_data[s->cmos_index];
	363	break;
	364	}
	365	#ifdef DEBUG_CMOS
	366	printf("cmos: read index=0x%02x val=0x%02x\n",
	367	s->cmos_index, ret);
	368	#endif
	369	return ret;
	370	}
	371	}
	372
dff38e7b FB	373	void rtc_set_memory(RTCState *s, int addr, int val)
	374	{
	375	if (addr >= 0 && addr <= 127)
	376	s->cmos_data[addr] = val;
	377	}
	378
	379	void rtc_set_date(RTCState s, const struct tm tm)
	380	{
43f493af	381	s->current_tm = *tm;
dff38e7b FB	382	rtc_copy_date(s);
	383	}
	384
ea55ffb3 TS	385	/* PC cmos mappings */
	386	#define REG_IBM_CENTURY_BYTE 0x32
	387	#define REG_IBM_PS2_CENTURY_BYTE 0x37
	388
	389	void rtc_set_date_from_host(RTCState *s)
	390	{
	391	time_t ti;
	392	struct tm *tm;
	393	int val;
	394
	395	/* set the CMOS date */
7e0af5d0 FB	396	if (rtc_start_date == -1) {
	397	time(&ti);
	398	if (rtc_utc)
	399	tm = gmtime(&ti);
	400	else
	401	tm = localtime(&ti);
	402	} else {
	403	ti = rtc_start_date;
ea55ffb3	404	tm = gmtime(&ti);
7e0af5d0	405	}
ea55ffb3 TS	406	rtc_set_date(s, tm);
	407
	408	val = to_bcd(s, (tm->tm_year / 100) + 19);
	409	rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
	410	rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
	411	}
	412
dff38e7b FB	413	static void rtc_save(QEMUFile f, void opaque)
	414	{
	415	RTCState *s = opaque;
	416
	417	qemu_put_buffer(f, s->cmos_data, 128);
	418	qemu_put_8s(f, &s->cmos_index);
3b46e624	419
43f493af FB	420	qemu_put_be32s(f, &s->current_tm.tm_sec);
	421	qemu_put_be32s(f, &s->current_tm.tm_min);
	422	qemu_put_be32s(f, &s->current_tm.tm_hour);
	423	qemu_put_be32s(f, &s->current_tm.tm_wday);
	424	qemu_put_be32s(f, &s->current_tm.tm_mday);
	425	qemu_put_be32s(f, &s->current_tm.tm_mon);
	426	qemu_put_be32s(f, &s->current_tm.tm_year);
dff38e7b FB	427
	428	qemu_put_timer(f, s->periodic_timer);
	429	qemu_put_be64s(f, &s->next_periodic_time);
	430
	431	qemu_put_be64s(f, &s->next_second_time);
	432	qemu_put_timer(f, s->second_timer);
	433	qemu_put_timer(f, s->second_timer2);
80cabfad FB	434	}
80cabfad FB	435
dff38e7b	436	static int rtc_load(QEMUFile f, void opaque, int version_id)
80cabfad	437	{
dff38e7b FB	438	RTCState *s = opaque;
	439
	440	if (version_id != 1)
	441	return -EINVAL;
80cabfad	442
dff38e7b FB	443	qemu_get_buffer(f, s->cmos_data, 128);
dff38e7b FB	444	qemu_get_8s(f, &s->cmos_index);
43f493af FB	445
	446	qemu_get_be32s(f, &s->current_tm.tm_sec);
	447	qemu_get_be32s(f, &s->current_tm.tm_min);
	448	qemu_get_be32s(f, &s->current_tm.tm_hour);
	449	qemu_get_be32s(f, &s->current_tm.tm_wday);
	450	qemu_get_be32s(f, &s->current_tm.tm_mday);
	451	qemu_get_be32s(f, &s->current_tm.tm_mon);
	452	qemu_get_be32s(f, &s->current_tm.tm_year);
dff38e7b FB	453
	454	qemu_get_timer(f, s->periodic_timer);
	455	qemu_get_be64s(f, &s->next_periodic_time);
	456
	457	qemu_get_be64s(f, &s->next_second_time);
	458	qemu_get_timer(f, s->second_timer);
	459	qemu_get_timer(f, s->second_timer2);
	460	return 0;
	461	}
	462
d537cf6c	463	RTCState *rtc_init(int base, qemu_irq irq)
dff38e7b FB	464	{
	465	RTCState *s;
	466
	467	s = qemu_mallocz(sizeof(RTCState));
	468	if (!s)
	469	return NULL;
80cabfad FB	470
	471	s->irq = irq;
	472	s->cmos_data[RTC_REG_A] = 0x26;
	473	s->cmos_data[RTC_REG_B] = 0x02;
	474	s->cmos_data[RTC_REG_C] = 0x00;
	475	s->cmos_data[RTC_REG_D] = 0x80;
	476
ea55ffb3 TS	477	rtc_set_date_from_host(s);
ea55ffb3 TS	478
5fafdf24	479	s->periodic_timer = qemu_new_timer(vm_clock,
dff38e7b	480	rtc_periodic_timer, s);
5fafdf24	481	s->second_timer = qemu_new_timer(vm_clock,
dff38e7b	482	rtc_update_second, s);
5fafdf24	483	s->second_timer2 = qemu_new_timer(vm_clock,
dff38e7b FB	484	rtc_update_second2, s);
	485
	486	s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
	487	qemu_mod_timer(s->second_timer2, s->next_second_time);
	488
b41a2cd1 FB	489	register_ioport_write(base, 2, 1, cmos_ioport_write, s);
b41a2cd1 FB	490	register_ioport_read(base, 2, 1, cmos_ioport_read, s);
dff38e7b FB	491
	492	register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
	493	return s;
80cabfad FB	494	}
80cabfad FB	495
2ca9d013 TS	496	/* Memory mapped interface */
	497	uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
	498	{
	499	RTCState *s = opaque;
	500
18c6e2ff	501	return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
2ca9d013 TS	502	}
	503
	504	void cmos_mm_writeb (void *opaque,
	505	target_phys_addr_t addr, uint32_t value)
	506	{
	507	RTCState *s = opaque;
	508
18c6e2ff	509	cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
2ca9d013 TS	510	}
	511
	512	uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
	513	{
	514	RTCState *s = opaque;
18c6e2ff	515	uint32_t val;
2ca9d013	516
18c6e2ff TS	517	val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
	518	#ifdef TARGET_WORDS_BIGENDIAN
	519	val = bswap16(val);
	520	#endif
	521	return val;
2ca9d013 TS	522	}
	523
	524	void cmos_mm_writew (void *opaque,
	525	target_phys_addr_t addr, uint32_t value)
	526	{
	527	RTCState *s = opaque;
18c6e2ff TS	528	#ifdef TARGET_WORDS_BIGENDIAN
	529	value = bswap16(value);
	530	#endif
	531	cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
2ca9d013 TS	532	}
	533
	534	uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
	535	{
	536	RTCState *s = opaque;
18c6e2ff	537	uint32_t val;
2ca9d013	538
18c6e2ff TS	539	val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift);
	540	#ifdef TARGET_WORDS_BIGENDIAN
	541	val = bswap32(val);
	542	#endif
	543	return val;
2ca9d013 TS	544	}
	545
	546	void cmos_mm_writel (void *opaque,
	547	target_phys_addr_t addr, uint32_t value)
	548	{
	549	RTCState *s = opaque;
18c6e2ff TS	550	#ifdef TARGET_WORDS_BIGENDIAN
	551	value = bswap32(value);
	552	#endif
	553	cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value);
2ca9d013 TS	554	}
	555
	556	static CPUReadMemoryFunc *rtc_mm_read[] = {
	557	&cmos_mm_readb,
	558	&cmos_mm_readw,
	559	&cmos_mm_readl,
	560	};
	561
	562	static CPUWriteMemoryFunc *rtc_mm_write[] = {
	563	&cmos_mm_writeb,
	564	&cmos_mm_writew,
	565	&cmos_mm_writel,
	566	};
	567
18c6e2ff	568	RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
2ca9d013 TS	569	{
	570	RTCState *s;
	571	int io_memory;
	572
	573	s = qemu_mallocz(sizeof(RTCState));
	574	if (!s)
	575	return NULL;
	576
	577	s->irq = irq;
	578	s->cmos_data[RTC_REG_A] = 0x26;
	579	s->cmos_data[RTC_REG_B] = 0x02;
	580	s->cmos_data[RTC_REG_C] = 0x00;
	581	s->cmos_data[RTC_REG_D] = 0x80;
	582	s->base = base;
	583
	584	rtc_set_date_from_host(s);
	585
	586	s->periodic_timer = qemu_new_timer(vm_clock,
	587	rtc_periodic_timer, s);
	588	s->second_timer = qemu_new_timer(vm_clock,
	589	rtc_update_second, s);
	590	s->second_timer2 = qemu_new_timer(vm_clock,
	591	rtc_update_second2, s);
	592
	593	s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
	594	qemu_mod_timer(s->second_timer2, s->next_second_time);
	595
	596	io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
18c6e2ff	597	cpu_register_physical_memory(base, 2 << it_shift, io_memory);
2ca9d013 TS	598
	599	register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
	600	return s;
	601	}