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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU MC146818 RTC emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "qemu-timer.h" | |
26 | #include "sysemu.h" | |
1d914fa0 | 27 | #include "mc146818rtc.h" |
80cabfad | 28 | |
d362e757 JK |
29 | #ifdef TARGET_I386 |
30 | #include "apic.h" | |
31 | #endif | |
32 | ||
80cabfad | 33 | //#define DEBUG_CMOS |
aa6f63ff | 34 | //#define DEBUG_COALESCED |
80cabfad | 35 | |
ec51e364 IY |
36 | #ifdef DEBUG_CMOS |
37 | # define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
38 | #else | |
39 | # define CMOS_DPRINTF(format, ...) do { } while (0) | |
40 | #endif | |
41 | ||
aa6f63ff BS |
42 | #ifdef DEBUG_COALESCED |
43 | # define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__) | |
44 | #else | |
45 | # define DPRINTF_C(format, ...) do { } while (0) | |
46 | #endif | |
47 | ||
dd17765b | 48 | #define RTC_REINJECT_ON_ACK_COUNT 20 |
ba32edab | 49 | |
1d914fa0 | 50 | typedef struct RTCState { |
32e0c826 | 51 | ISADevice dev; |
b2c5009b | 52 | MemoryRegion io; |
dff38e7b FB |
53 | uint8_t cmos_data[128]; |
54 | uint8_t cmos_index; | |
43f493af | 55 | struct tm current_tm; |
32e0c826 | 56 | int32_t base_year; |
d537cf6c | 57 | qemu_irq irq; |
100d9891 | 58 | qemu_irq sqw_irq; |
18c6e2ff | 59 | int it_shift; |
dff38e7b FB |
60 | /* periodic timer */ |
61 | QEMUTimer *periodic_timer; | |
62 | int64_t next_periodic_time; | |
63 | /* second update */ | |
64 | int64_t next_second_time; | |
ba32edab | 65 | uint16_t irq_reinject_on_ack_count; |
73822ec8 AL |
66 | uint32_t irq_coalesced; |
67 | uint32_t period; | |
93b66569 | 68 | QEMUTimer *coalesced_timer; |
dff38e7b FB |
69 | QEMUTimer *second_timer; |
70 | QEMUTimer *second_timer2; | |
17604dac | 71 | Notifier clock_reset_notifier; |
433acf0d | 72 | LostTickPolicy lost_tick_policy; |
da98c8eb | 73 | Notifier suspend_notifier; |
1d914fa0 | 74 | } RTCState; |
dff38e7b FB |
75 | |
76 | static void rtc_set_time(RTCState *s); | |
dff38e7b FB |
77 | static void rtc_copy_date(RTCState *s); |
78 | ||
93b66569 AL |
79 | #ifdef TARGET_I386 |
80 | static void rtc_coalesced_timer_update(RTCState *s) | |
81 | { | |
82 | if (s->irq_coalesced == 0) { | |
83 | qemu_del_timer(s->coalesced_timer); | |
84 | } else { | |
85 | /* divide each RTC interval to 2 - 8 smaller intervals */ | |
86 | int c = MIN(s->irq_coalesced, 7) + 1; | |
74475455 | 87 | int64_t next_clock = qemu_get_clock_ns(rtc_clock) + |
6875204c | 88 | muldiv64(s->period / c, get_ticks_per_sec(), 32768); |
93b66569 AL |
89 | qemu_mod_timer(s->coalesced_timer, next_clock); |
90 | } | |
91 | } | |
92 | ||
93 | static void rtc_coalesced_timer(void *opaque) | |
94 | { | |
95 | RTCState *s = opaque; | |
96 | ||
97 | if (s->irq_coalesced != 0) { | |
98 | apic_reset_irq_delivered(); | |
99 | s->cmos_data[RTC_REG_C] |= 0xc0; | |
aa6f63ff | 100 | DPRINTF_C("cmos: injecting from timer\n"); |
7d932dfd | 101 | qemu_irq_raise(s->irq); |
93b66569 AL |
102 | if (apic_get_irq_delivered()) { |
103 | s->irq_coalesced--; | |
aa6f63ff BS |
104 | DPRINTF_C("cmos: coalesced irqs decreased to %d\n", |
105 | s->irq_coalesced); | |
93b66569 AL |
106 | } |
107 | } | |
108 | ||
109 | rtc_coalesced_timer_update(s); | |
110 | } | |
111 | #endif | |
112 | ||
dff38e7b FB |
113 | static void rtc_timer_update(RTCState *s, int64_t current_time) |
114 | { | |
115 | int period_code, period; | |
116 | int64_t cur_clock, next_irq_clock; | |
117 | ||
118 | period_code = s->cmos_data[RTC_REG_A] & 0x0f; | |
100d9891 | 119 | if (period_code != 0 |
7d932dfd | 120 | && ((s->cmos_data[RTC_REG_B] & REG_B_PIE) |
100d9891 | 121 | || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { |
dff38e7b FB |
122 | if (period_code <= 2) |
123 | period_code += 7; | |
124 | /* period in 32 Khz cycles */ | |
125 | period = 1 << (period_code - 1); | |
73822ec8 | 126 | #ifdef TARGET_I386 |
aa6f63ff | 127 | if (period != s->period) { |
73822ec8 | 128 | s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
aa6f63ff BS |
129 | DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced); |
130 | } | |
73822ec8 AL |
131 | s->period = period; |
132 | #endif | |
dff38e7b | 133 | /* compute 32 khz clock */ |
6ee093c9 | 134 | cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec()); |
dff38e7b | 135 | next_irq_clock = (cur_clock & ~(period - 1)) + period; |
6875204c JK |
136 | s->next_periodic_time = |
137 | muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1; | |
dff38e7b FB |
138 | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
139 | } else { | |
73822ec8 AL |
140 | #ifdef TARGET_I386 |
141 | s->irq_coalesced = 0; | |
142 | #endif | |
dff38e7b FB |
143 | qemu_del_timer(s->periodic_timer); |
144 | } | |
145 | } | |
146 | ||
147 | static void rtc_periodic_timer(void *opaque) | |
148 | { | |
149 | RTCState *s = opaque; | |
150 | ||
151 | rtc_timer_update(s, s->next_periodic_time); | |
663447d4 | 152 | s->cmos_data[RTC_REG_C] |= REG_C_PF; |
100d9891 | 153 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) { |
663447d4 | 154 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
93b66569 | 155 | #ifdef TARGET_I386 |
433acf0d | 156 | if (s->lost_tick_policy == LOST_TICK_SLEW) { |
ba32edab GN |
157 | if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT) |
158 | s->irq_reinject_on_ack_count = 0; | |
93b66569 | 159 | apic_reset_irq_delivered(); |
7d932dfd | 160 | qemu_irq_raise(s->irq); |
93b66569 AL |
161 | if (!apic_get_irq_delivered()) { |
162 | s->irq_coalesced++; | |
163 | rtc_coalesced_timer_update(s); | |
aa6f63ff BS |
164 | DPRINTF_C("cmos: coalesced irqs increased to %d\n", |
165 | s->irq_coalesced); | |
93b66569 AL |
166 | } |
167 | } else | |
168 | #endif | |
7d932dfd | 169 | qemu_irq_raise(s->irq); |
100d9891 AJ |
170 | } |
171 | if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) { | |
172 | /* Not square wave at all but we don't want 2048Hz interrupts! | |
173 | Must be seen as a pulse. */ | |
174 | qemu_irq_raise(s->sqw_irq); | |
175 | } | |
dff38e7b | 176 | } |
80cabfad | 177 | |
b41a2cd1 | 178 | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad | 179 | { |
b41a2cd1 | 180 | RTCState *s = opaque; |
80cabfad FB |
181 | |
182 | if ((addr & 1) == 0) { | |
183 | s->cmos_index = data & 0x7f; | |
184 | } else { | |
ec51e364 IY |
185 | CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n", |
186 | s->cmos_index, data); | |
dff38e7b | 187 | switch(s->cmos_index) { |
80cabfad FB |
188 | case RTC_SECONDS_ALARM: |
189 | case RTC_MINUTES_ALARM: | |
190 | case RTC_HOURS_ALARM: | |
80cabfad FB |
191 | s->cmos_data[s->cmos_index] = data; |
192 | break; | |
193 | case RTC_SECONDS: | |
194 | case RTC_MINUTES: | |
195 | case RTC_HOURS: | |
196 | case RTC_DAY_OF_WEEK: | |
197 | case RTC_DAY_OF_MONTH: | |
198 | case RTC_MONTH: | |
199 | case RTC_YEAR: | |
200 | s->cmos_data[s->cmos_index] = data; | |
dff38e7b FB |
201 | /* if in set mode, do not update the time */ |
202 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
203 | rtc_set_time(s); | |
204 | } | |
80cabfad FB |
205 | break; |
206 | case RTC_REG_A: | |
dff38e7b FB |
207 | /* UIP bit is read only */ |
208 | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | | |
209 | (s->cmos_data[RTC_REG_A] & REG_A_UIP); | |
74475455 | 210 | rtc_timer_update(s, qemu_get_clock_ns(rtc_clock)); |
dff38e7b | 211 | break; |
80cabfad | 212 | case RTC_REG_B: |
dff38e7b FB |
213 | if (data & REG_B_SET) { |
214 | /* set mode: reset UIP mode */ | |
215 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
216 | data &= ~REG_B_UIE; | |
217 | } else { | |
218 | /* if disabling set mode, update the time */ | |
219 | if (s->cmos_data[RTC_REG_B] & REG_B_SET) { | |
220 | rtc_set_time(s); | |
221 | } | |
222 | } | |
bedc572e | 223 | s->cmos_data[RTC_REG_B] = data; |
74475455 | 224 | rtc_timer_update(s, qemu_get_clock_ns(rtc_clock)); |
80cabfad FB |
225 | break; |
226 | case RTC_REG_C: | |
227 | case RTC_REG_D: | |
228 | /* cannot write to them */ | |
229 | break; | |
230 | default: | |
231 | s->cmos_data[s->cmos_index] = data; | |
232 | break; | |
233 | } | |
234 | } | |
235 | } | |
236 | ||
abd0c6bd | 237 | static inline int rtc_to_bcd(RTCState *s, int a) |
80cabfad | 238 | { |
6f1bf24d | 239 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
240 | return a; |
241 | } else { | |
242 | return ((a / 10) << 4) | (a % 10); | |
243 | } | |
80cabfad FB |
244 | } |
245 | ||
abd0c6bd | 246 | static inline int rtc_from_bcd(RTCState *s, int a) |
80cabfad | 247 | { |
6f1bf24d | 248 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
249 | return a; |
250 | } else { | |
251 | return ((a >> 4) * 10) + (a & 0x0f); | |
252 | } | |
253 | } | |
254 | ||
255 | static void rtc_set_time(RTCState *s) | |
256 | { | |
43f493af | 257 | struct tm *tm = &s->current_tm; |
dff38e7b | 258 | |
abd0c6bd PB |
259 | tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
260 | tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
261 | tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f); | |
3b89eb43 PB |
262 | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) { |
263 | tm->tm_hour %= 12; | |
264 | if (s->cmos_data[RTC_HOURS] & 0x80) { | |
265 | tm->tm_hour += 12; | |
266 | } | |
43f493af | 267 | } |
abd0c6bd PB |
268 | tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1; |
269 | tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); | |
270 | tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1; | |
271 | tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900; | |
80cd3478 LC |
272 | |
273 | rtc_change_mon_event(tm); | |
43f493af FB |
274 | } |
275 | ||
276 | static void rtc_copy_date(RTCState *s) | |
277 | { | |
278 | const struct tm *tm = &s->current_tm; | |
42fc73a1 | 279 | int year; |
dff38e7b | 280 | |
abd0c6bd PB |
281 | s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
282 | s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); | |
c29cd656 | 283 | if (s->cmos_data[RTC_REG_B] & REG_B_24H) { |
43f493af | 284 | /* 24 hour format */ |
abd0c6bd | 285 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
43f493af FB |
286 | } else { |
287 | /* 12 hour format */ | |
3b89eb43 PB |
288 | int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12; |
289 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h); | |
43f493af FB |
290 | if (tm->tm_hour >= 12) |
291 | s->cmos_data[RTC_HOURS] |= 0x80; | |
292 | } | |
abd0c6bd PB |
293 | s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1); |
294 | s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); | |
295 | s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1); | |
42fc73a1 AJ |
296 | year = (tm->tm_year - s->base_year) % 100; |
297 | if (year < 0) | |
298 | year += 100; | |
abd0c6bd | 299 | s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year); |
43f493af FB |
300 | } |
301 | ||
302 | /* month is between 0 and 11. */ | |
303 | static int get_days_in_month(int month, int year) | |
304 | { | |
5fafdf24 TS |
305 | static const int days_tab[12] = { |
306 | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 | |
43f493af FB |
307 | }; |
308 | int d; | |
309 | if ((unsigned )month >= 12) | |
310 | return 31; | |
311 | d = days_tab[month]; | |
312 | if (month == 1) { | |
313 | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) | |
314 | d++; | |
315 | } | |
316 | return d; | |
317 | } | |
318 | ||
319 | /* update 'tm' to the next second */ | |
320 | static void rtc_next_second(struct tm *tm) | |
321 | { | |
322 | int days_in_month; | |
323 | ||
324 | tm->tm_sec++; | |
325 | if ((unsigned)tm->tm_sec >= 60) { | |
326 | tm->tm_sec = 0; | |
327 | tm->tm_min++; | |
328 | if ((unsigned)tm->tm_min >= 60) { | |
329 | tm->tm_min = 0; | |
330 | tm->tm_hour++; | |
331 | if ((unsigned)tm->tm_hour >= 24) { | |
332 | tm->tm_hour = 0; | |
333 | /* next day */ | |
334 | tm->tm_wday++; | |
335 | if ((unsigned)tm->tm_wday >= 7) | |
336 | tm->tm_wday = 0; | |
5fafdf24 | 337 | days_in_month = get_days_in_month(tm->tm_mon, |
43f493af FB |
338 | tm->tm_year + 1900); |
339 | tm->tm_mday++; | |
340 | if (tm->tm_mday < 1) { | |
341 | tm->tm_mday = 1; | |
342 | } else if (tm->tm_mday > days_in_month) { | |
343 | tm->tm_mday = 1; | |
344 | tm->tm_mon++; | |
345 | if (tm->tm_mon >= 12) { | |
346 | tm->tm_mon = 0; | |
347 | tm->tm_year++; | |
348 | } | |
349 | } | |
350 | } | |
351 | } | |
352 | } | |
dff38e7b FB |
353 | } |
354 | ||
43f493af | 355 | |
dff38e7b FB |
356 | static void rtc_update_second(void *opaque) |
357 | { | |
358 | RTCState *s = opaque; | |
4721c457 | 359 | int64_t delay; |
dff38e7b FB |
360 | |
361 | /* if the oscillator is not in normal operation, we do not update */ | |
362 | if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { | |
6ee093c9 | 363 | s->next_second_time += get_ticks_per_sec(); |
dff38e7b FB |
364 | qemu_mod_timer(s->second_timer, s->next_second_time); |
365 | } else { | |
43f493af | 366 | rtc_next_second(&s->current_tm); |
3b46e624 | 367 | |
dff38e7b FB |
368 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { |
369 | /* update in progress bit */ | |
370 | s->cmos_data[RTC_REG_A] |= REG_A_UIP; | |
371 | } | |
4721c457 FB |
372 | /* should be 244 us = 8 / 32768 seconds, but currently the |
373 | timers do not have the necessary resolution. */ | |
6ee093c9 | 374 | delay = (get_ticks_per_sec() * 1) / 100; |
4721c457 FB |
375 | if (delay < 1) |
376 | delay = 1; | |
5fafdf24 | 377 | qemu_mod_timer(s->second_timer2, |
4721c457 | 378 | s->next_second_time + delay); |
dff38e7b FB |
379 | } |
380 | } | |
381 | ||
382 | static void rtc_update_second2(void *opaque) | |
383 | { | |
384 | RTCState *s = opaque; | |
dff38e7b FB |
385 | |
386 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
387 | rtc_copy_date(s); | |
388 | } | |
389 | ||
390 | /* check alarm */ | |
eea86673 PB |
391 | if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
392 | rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]) == s->current_tm.tm_sec) && | |
393 | ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || | |
394 | rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]) == s->current_tm.tm_min) && | |
395 | ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || | |
396 | rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]) == s->current_tm.tm_hour)) { | |
397 | ||
398 | s->cmos_data[RTC_REG_C] |= REG_C_AF; | |
399 | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) { | |
62aeb0f7 | 400 | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC); |
7d932dfd | 401 | qemu_irq_raise(s->irq); |
eea86673 | 402 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
dff38e7b FB |
403 | } |
404 | } | |
405 | ||
406 | /* update ended interrupt */ | |
98815437 | 407 | s->cmos_data[RTC_REG_C] |= REG_C_UF; |
dff38e7b | 408 | if (s->cmos_data[RTC_REG_B] & REG_B_UIE) { |
7d932dfd JK |
409 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
410 | qemu_irq_raise(s->irq); | |
dff38e7b FB |
411 | } |
412 | ||
413 | /* clear update in progress bit */ | |
414 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
415 | ||
6ee093c9 | 416 | s->next_second_time += get_ticks_per_sec(); |
dff38e7b | 417 | qemu_mod_timer(s->second_timer, s->next_second_time); |
80cabfad FB |
418 | } |
419 | ||
b41a2cd1 | 420 | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
80cabfad | 421 | { |
b41a2cd1 | 422 | RTCState *s = opaque; |
80cabfad FB |
423 | int ret; |
424 | if ((addr & 1) == 0) { | |
425 | return 0xff; | |
426 | } else { | |
427 | switch(s->cmos_index) { | |
428 | case RTC_SECONDS: | |
429 | case RTC_MINUTES: | |
430 | case RTC_HOURS: | |
431 | case RTC_DAY_OF_WEEK: | |
432 | case RTC_DAY_OF_MONTH: | |
433 | case RTC_MONTH: | |
434 | case RTC_YEAR: | |
80cabfad FB |
435 | ret = s->cmos_data[s->cmos_index]; |
436 | break; | |
437 | case RTC_REG_A: | |
438 | ret = s->cmos_data[s->cmos_index]; | |
80cabfad FB |
439 | break; |
440 | case RTC_REG_C: | |
441 | ret = s->cmos_data[s->cmos_index]; | |
d537cf6c | 442 | qemu_irq_lower(s->irq); |
fbc15e27 | 443 | s->cmos_data[RTC_REG_C] = 0x00; |
ba32edab GN |
444 | #ifdef TARGET_I386 |
445 | if(s->irq_coalesced && | |
fbc15e27 | 446 | (s->cmos_data[RTC_REG_B] & REG_B_PIE) && |
ba32edab GN |
447 | s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
448 | s->irq_reinject_on_ack_count++; | |
fbc15e27 | 449 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF; |
ba32edab | 450 | apic_reset_irq_delivered(); |
aa6f63ff | 451 | DPRINTF_C("cmos: injecting on ack\n"); |
ba32edab | 452 | qemu_irq_raise(s->irq); |
aa6f63ff | 453 | if (apic_get_irq_delivered()) { |
ba32edab | 454 | s->irq_coalesced--; |
aa6f63ff BS |
455 | DPRINTF_C("cmos: coalesced irqs decreased to %d\n", |
456 | s->irq_coalesced); | |
457 | } | |
ba32edab GN |
458 | } |
459 | #endif | |
80cabfad FB |
460 | break; |
461 | default: | |
462 | ret = s->cmos_data[s->cmos_index]; | |
463 | break; | |
464 | } | |
ec51e364 IY |
465 | CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n", |
466 | s->cmos_index, ret); | |
80cabfad FB |
467 | return ret; |
468 | } | |
469 | } | |
470 | ||
1d914fa0 | 471 | void rtc_set_memory(ISADevice *dev, int addr, int val) |
dff38e7b | 472 | { |
1d914fa0 | 473 | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
dff38e7b FB |
474 | if (addr >= 0 && addr <= 127) |
475 | s->cmos_data[addr] = val; | |
476 | } | |
477 | ||
1d914fa0 | 478 | void rtc_set_date(ISADevice *dev, const struct tm *tm) |
dff38e7b | 479 | { |
1d914fa0 | 480 | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
43f493af | 481 | s->current_tm = *tm; |
dff38e7b FB |
482 | rtc_copy_date(s); |
483 | } | |
484 | ||
ea55ffb3 TS |
485 | /* PC cmos mappings */ |
486 | #define REG_IBM_CENTURY_BYTE 0x32 | |
487 | #define REG_IBM_PS2_CENTURY_BYTE 0x37 | |
488 | ||
1d914fa0 | 489 | static void rtc_set_date_from_host(ISADevice *dev) |
ea55ffb3 | 490 | { |
1d914fa0 | 491 | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
f6503059 | 492 | struct tm tm; |
ea55ffb3 TS |
493 | int val; |
494 | ||
495 | /* set the CMOS date */ | |
f6503059 | 496 | qemu_get_timedate(&tm, 0); |
1d914fa0 | 497 | rtc_set_date(dev, &tm); |
ea55ffb3 | 498 | |
abd0c6bd | 499 | val = rtc_to_bcd(s, (tm.tm_year / 100) + 19); |
1d914fa0 IY |
500 | rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val); |
501 | rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val); | |
ea55ffb3 TS |
502 | } |
503 | ||
6b075b8a | 504 | static int rtc_post_load(void *opaque, int version_id) |
80cabfad | 505 | { |
6b075b8a | 506 | #ifdef TARGET_I386 |
dff38e7b FB |
507 | RTCState *s = opaque; |
508 | ||
048c74c4 | 509 | if (version_id >= 2) { |
433acf0d | 510 | if (s->lost_tick_policy == LOST_TICK_SLEW) { |
048c74c4 JQ |
511 | rtc_coalesced_timer_update(s); |
512 | } | |
048c74c4 | 513 | } |
6b075b8a | 514 | #endif |
73822ec8 AL |
515 | return 0; |
516 | } | |
73822ec8 | 517 | |
6b075b8a JQ |
518 | static const VMStateDescription vmstate_rtc = { |
519 | .name = "mc146818rtc", | |
520 | .version_id = 2, | |
521 | .minimum_version_id = 1, | |
522 | .minimum_version_id_old = 1, | |
523 | .post_load = rtc_post_load, | |
524 | .fields = (VMStateField []) { | |
525 | VMSTATE_BUFFER(cmos_data, RTCState), | |
526 | VMSTATE_UINT8(cmos_index, RTCState), | |
527 | VMSTATE_INT32(current_tm.tm_sec, RTCState), | |
528 | VMSTATE_INT32(current_tm.tm_min, RTCState), | |
529 | VMSTATE_INT32(current_tm.tm_hour, RTCState), | |
530 | VMSTATE_INT32(current_tm.tm_wday, RTCState), | |
531 | VMSTATE_INT32(current_tm.tm_mday, RTCState), | |
532 | VMSTATE_INT32(current_tm.tm_mon, RTCState), | |
533 | VMSTATE_INT32(current_tm.tm_year, RTCState), | |
534 | VMSTATE_TIMER(periodic_timer, RTCState), | |
535 | VMSTATE_INT64(next_periodic_time, RTCState), | |
536 | VMSTATE_INT64(next_second_time, RTCState), | |
537 | VMSTATE_TIMER(second_timer, RTCState), | |
538 | VMSTATE_TIMER(second_timer2, RTCState), | |
539 | VMSTATE_UINT32_V(irq_coalesced, RTCState, 2), | |
540 | VMSTATE_UINT32_V(period, RTCState, 2), | |
541 | VMSTATE_END_OF_LIST() | |
542 | } | |
543 | }; | |
544 | ||
17604dac JK |
545 | static void rtc_notify_clock_reset(Notifier *notifier, void *data) |
546 | { | |
547 | RTCState *s = container_of(notifier, RTCState, clock_reset_notifier); | |
548 | int64_t now = *(int64_t *)data; | |
549 | ||
550 | rtc_set_date_from_host(&s->dev); | |
551 | s->next_second_time = now + (get_ticks_per_sec() * 99) / 100; | |
552 | qemu_mod_timer(s->second_timer2, s->next_second_time); | |
553 | rtc_timer_update(s, now); | |
554 | #ifdef TARGET_I386 | |
433acf0d | 555 | if (s->lost_tick_policy == LOST_TICK_SLEW) { |
17604dac JK |
556 | rtc_coalesced_timer_update(s); |
557 | } | |
558 | #endif | |
559 | } | |
560 | ||
da98c8eb GH |
561 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
562 | BIOS will read it and start S3 resume at POST Entry */ | |
563 | static void rtc_notify_suspend(Notifier *notifier, void *data) | |
564 | { | |
565 | RTCState *s = container_of(notifier, RTCState, suspend_notifier); | |
566 | rtc_set_memory(&s->dev, 0xF, 0xFE); | |
567 | } | |
568 | ||
eeb7c03c GN |
569 | static void rtc_reset(void *opaque) |
570 | { | |
571 | RTCState *s = opaque; | |
572 | ||
72716184 AL |
573 | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
574 | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); | |
eeb7c03c | 575 | |
72716184 | 576 | qemu_irq_lower(s->irq); |
eeb7c03c GN |
577 | |
578 | #ifdef TARGET_I386 | |
433acf0d JK |
579 | if (s->lost_tick_policy == LOST_TICK_SLEW) { |
580 | s->irq_coalesced = 0; | |
581 | } | |
eeb7c03c GN |
582 | #endif |
583 | } | |
584 | ||
b2c5009b RH |
585 | static const MemoryRegionPortio cmos_portio[] = { |
586 | {0, 2, 1, .read = cmos_ioport_read, .write = cmos_ioport_write }, | |
587 | PORTIO_END_OF_LIST(), | |
588 | }; | |
589 | ||
590 | static const MemoryRegionOps cmos_ops = { | |
591 | .old_portio = cmos_portio | |
592 | }; | |
593 | ||
57c9fafe | 594 | static void rtc_get_date(Object *obj, Visitor *v, void *opaque, |
18297050 AL |
595 | const char *name, Error **errp) |
596 | { | |
57c9fafe | 597 | ISADevice *isa = ISA_DEVICE(obj); |
18297050 AL |
598 | RTCState *s = DO_UPCAST(RTCState, dev, isa); |
599 | ||
600 | visit_start_struct(v, NULL, "struct tm", name, 0, errp); | |
601 | visit_type_int32(v, &s->current_tm.tm_year, "tm_year", errp); | |
602 | visit_type_int32(v, &s->current_tm.tm_mon, "tm_mon", errp); | |
603 | visit_type_int32(v, &s->current_tm.tm_mday, "tm_mday", errp); | |
604 | visit_type_int32(v, &s->current_tm.tm_hour, "tm_hour", errp); | |
605 | visit_type_int32(v, &s->current_tm.tm_min, "tm_min", errp); | |
606 | visit_type_int32(v, &s->current_tm.tm_sec, "tm_sec", errp); | |
607 | visit_end_struct(v, errp); | |
608 | } | |
609 | ||
32e0c826 | 610 | static int rtc_initfn(ISADevice *dev) |
dff38e7b | 611 | { |
32e0c826 GH |
612 | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
613 | int base = 0x70; | |
80cabfad | 614 | |
80cabfad FB |
615 | s->cmos_data[RTC_REG_A] = 0x26; |
616 | s->cmos_data[RTC_REG_B] = 0x02; | |
617 | s->cmos_data[RTC_REG_C] = 0x00; | |
618 | s->cmos_data[RTC_REG_D] = 0x80; | |
619 | ||
1d914fa0 | 620 | rtc_set_date_from_host(dev); |
ea55ffb3 | 621 | |
93b66569 | 622 | #ifdef TARGET_I386 |
433acf0d JK |
623 | switch (s->lost_tick_policy) { |
624 | case LOST_TICK_SLEW: | |
6875204c | 625 | s->coalesced_timer = |
74475455 | 626 | qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s); |
433acf0d JK |
627 | break; |
628 | case LOST_TICK_DISCARD: | |
629 | break; | |
630 | default: | |
631 | return -EINVAL; | |
632 | } | |
93b66569 | 633 | #endif |
433acf0d JK |
634 | |
635 | s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s); | |
74475455 PB |
636 | s->second_timer = qemu_new_timer_ns(rtc_clock, rtc_update_second, s); |
637 | s->second_timer2 = qemu_new_timer_ns(rtc_clock, rtc_update_second2, s); | |
dff38e7b | 638 | |
17604dac JK |
639 | s->clock_reset_notifier.notify = rtc_notify_clock_reset; |
640 | qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier); | |
641 | ||
da98c8eb GH |
642 | s->suspend_notifier.notify = rtc_notify_suspend; |
643 | qemu_register_suspend_notifier(&s->suspend_notifier); | |
644 | ||
6875204c | 645 | s->next_second_time = |
74475455 | 646 | qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100; |
dff38e7b FB |
647 | qemu_mod_timer(s->second_timer2, s->next_second_time); |
648 | ||
b2c5009b RH |
649 | memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2); |
650 | isa_register_ioport(dev, &s->io, base); | |
dff38e7b | 651 | |
dc683910 | 652 | qdev_set_legacy_instance_id(&dev->qdev, base, 2); |
a08d4367 | 653 | qemu_register_reset(rtc_reset, s); |
18297050 | 654 | |
57c9fafe AL |
655 | object_property_add(OBJECT(s), "date", "struct tm", |
656 | rtc_get_date, NULL, NULL, s, NULL); | |
18297050 | 657 | |
32e0c826 GH |
658 | return 0; |
659 | } | |
660 | ||
48a18b3c | 661 | ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq) |
32e0c826 GH |
662 | { |
663 | ISADevice *dev; | |
7d932dfd | 664 | RTCState *s; |
eeb7c03c | 665 | |
48a18b3c | 666 | dev = isa_create(bus, "mc146818rtc"); |
7d932dfd | 667 | s = DO_UPCAST(RTCState, dev, dev); |
32e0c826 | 668 | qdev_prop_set_int32(&dev->qdev, "base_year", base_year); |
e23a1b33 | 669 | qdev_init_nofail(&dev->qdev); |
7d932dfd JK |
670 | if (intercept_irq) { |
671 | s->irq = intercept_irq; | |
672 | } else { | |
673 | isa_init_irq(dev, &s->irq, RTC_ISA_IRQ); | |
674 | } | |
1d914fa0 | 675 | return dev; |
80cabfad FB |
676 | } |
677 | ||
39bffca2 AL |
678 | static Property mc146818rtc_properties[] = { |
679 | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), | |
680 | DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState, | |
681 | lost_tick_policy, LOST_TICK_DISCARD), | |
682 | DEFINE_PROP_END_OF_LIST(), | |
683 | }; | |
684 | ||
8f04ee08 AL |
685 | static void rtc_class_initfn(ObjectClass *klass, void *data) |
686 | { | |
39bffca2 | 687 | DeviceClass *dc = DEVICE_CLASS(klass); |
8f04ee08 AL |
688 | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
689 | ic->init = rtc_initfn; | |
39bffca2 AL |
690 | dc->no_user = 1; |
691 | dc->vmsd = &vmstate_rtc; | |
692 | dc->props = mc146818rtc_properties; | |
8f04ee08 AL |
693 | } |
694 | ||
39bffca2 AL |
695 | static TypeInfo mc146818rtc_info = { |
696 | .name = "mc146818rtc", | |
697 | .parent = TYPE_ISA_DEVICE, | |
698 | .instance_size = sizeof(RTCState), | |
699 | .class_init = rtc_class_initfn, | |
32e0c826 GH |
700 | }; |
701 | ||
83f7d43a | 702 | static void mc146818rtc_register_types(void) |
100d9891 | 703 | { |
39bffca2 | 704 | type_register_static(&mc146818rtc_info); |
100d9891 | 705 | } |
83f7d43a AF |
706 | |
707 | type_init(mc146818rtc_register_types) |