[mirror_qemu.git] / hw / mc146818rtc.c

/*
 * QEMU MC146818 RTC emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "pc.h"
#include "isa.h"
#include "hpet_emul.h"

//#define DEBUG_CMOS

#define RTC_SECONDS             0
#define RTC_SECONDS_ALARM       1
#define RTC_MINUTES             2
#define RTC_MINUTES_ALARM       3
#define RTC_HOURS               4
#define RTC_HOURS_ALARM         5
#define RTC_ALARM_DONT_CARE    0xC0

#define RTC_DAY_OF_WEEK         6
#define RTC_DAY_OF_MONTH        7
#define RTC_MONTH               8
#define RTC_YEAR                9

#define RTC_REG_A               10
#define RTC_REG_B               11
#define RTC_REG_C               12
#define RTC_REG_D               13

#define REG_A_UIP 0x80

#define REG_B_SET 0x80
#define REG_B_PIE 0x40
#define REG_B_AIE 0x20
#define REG_B_UIE 0x10

struct RTCState {
    uint8_t cmos_data[128];
    uint8_t cmos_index;
    struct tm current_tm;
    qemu_irq irq;
    int it_shift;
    /* periodic timer */
    QEMUTimer *periodic_timer;
    int64_t next_periodic_time;
    /* second update */
    int64_t next_second_time;
    QEMUTimer *second_timer;
    QEMUTimer *second_timer2;
};

static void rtc_irq_raise(qemu_irq irq) {
    /* When HPET is operating in legacy mode, RTC interrupts are disabled 
     * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
     * mode is established while interrupt is raised. We want it to 
     * be lowered in any case
     */ 
#if defined TARGET_I386 || defined TARGET_X86_64
    if (!hpet_in_legacy_mode()) 
#endif
        qemu_irq_raise(irq);
}

static void rtc_set_time(RTCState *s);
static void rtc_copy_date(RTCState *s);

static void rtc_timer_update(RTCState *s, int64_t current_time)
{
    int period_code, period;
    int64_t cur_clock, next_irq_clock;

    period_code = s->cmos_data[RTC_REG_A] & 0x0f;
#if defined TARGET_I386 || defined TARGET_X86_64
    /* disable periodic timer if hpet is in legacy mode, since interrupts are 
     * disabled anyway.
     */
    if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE) && !hpet_in_legacy_mode()) {
#else
    if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
#endif
        if (period_code <= 2)
            period_code += 7;
        /* period in 32 Khz cycles */
        period = 1 << (period_code - 1);
        /* compute 32 khz clock */
        cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
        next_irq_clock = (cur_clock & ~(period - 1)) + period;
        s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1;
        qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
    } else {
        qemu_del_timer(s->periodic_timer);
    }
}

static void rtc_periodic_timer(void *opaque)
{
    RTCState *s = opaque;

    rtc_timer_update(s, s->next_periodic_time);
    s->cmos_data[RTC_REG_C] |= 0xc0;
    rtc_irq_raise(s->irq);
}

static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
{
    RTCState *s = opaque;

    if ((addr & 1) == 0) {
        s->cmos_index = data & 0x7f;
    } else {
#ifdef DEBUG_CMOS
        printf("cmos: write index=0x%02x val=0x%02x\n",
               s->cmos_index, data);
#endif
        switch(s->cmos_index) {
        case RTC_SECONDS_ALARM:
        case RTC_MINUTES_ALARM:
        case RTC_HOURS_ALARM:
            /* XXX: not supported */
            s->cmos_data[s->cmos_index] = data;
            break;
        case RTC_SECONDS:
        case RTC_MINUTES:
        case RTC_HOURS:
        case RTC_DAY_OF_WEEK:
        case RTC_DAY_OF_MONTH:
        case RTC_MONTH:
        case RTC_YEAR:
            s->cmos_data[s->cmos_index] = data;
            /* if in set mode, do not update the time */
            if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
                rtc_set_time(s);
            }
            break;
        case RTC_REG_A:
            /* UIP bit is read only */
            s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
                (s->cmos_data[RTC_REG_A] & REG_A_UIP);
            rtc_timer_update(s, qemu_get_clock(vm_clock));
            break;
        case RTC_REG_B:
            if (data & REG_B_SET) {
                /* set mode: reset UIP mode */
                s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
                data &= ~REG_B_UIE;
            } else {
                /* if disabling set mode, update the time */
                if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
                    rtc_set_time(s);
                }
            }
            s->cmos_data[RTC_REG_B] = data;
            rtc_timer_update(s, qemu_get_clock(vm_clock));
            break;
        case RTC_REG_C:
        case RTC_REG_D:
            /* cannot write to them */
            break;
        default:
            s->cmos_data[s->cmos_index] = data;
            break;
        }
    }
}

static inline int to_bcd(RTCState *s, int a)
{
    if (s->cmos_data[RTC_REG_B] & 0x04) {
        return a;
    } else {
        return ((a / 10) << 4) | (a % 10);
    }
}

static inline int from_bcd(RTCState *s, int a)
{
    if (s->cmos_data[RTC_REG_B] & 0x04) {
        return a;
    } else {
        return ((a >> 4) * 10) + (a & 0x0f);
    }
}

static void rtc_set_time(RTCState *s)
{
    struct tm *tm = &s->current_tm;

    tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
    tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
    tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
    if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
        (s->cmos_data[RTC_HOURS] & 0x80)) {
        tm->tm_hour += 12;
    }
    tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
    tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
    tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
    tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
}

static void rtc_copy_date(RTCState *s)
{
    const struct tm *tm = &s->current_tm;

    s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
    s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
    if (s->cmos_data[RTC_REG_B] & 0x02) {
        /* 24 hour format */
        s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
    } else {
        /* 12 hour format */
        s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
        if (tm->tm_hour >= 12)
            s->cmos_data[RTC_HOURS] |= 0x80;
    }
    s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
    s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
    s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
    s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
}

/* month is between 0 and 11. */
static int get_days_in_month(int month, int year)
{
    static const int days_tab[12] = {
        31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
    };
    int d;
    if ((unsigned )month >= 12)
        return 31;
    d = days_tab[month];
    if (month == 1) {
        if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
            d++;
    }
    return d;
}

/* update 'tm' to the next second */
static void rtc_next_second(struct tm *tm)
{
    int days_in_month;

    tm->tm_sec++;
    if ((unsigned)tm->tm_sec >= 60) {
        tm->tm_sec = 0;
        tm->tm_min++;
        if ((unsigned)tm->tm_min >= 60) {
            tm->tm_min = 0;
            tm->tm_hour++;
            if ((unsigned)tm->tm_hour >= 24) {
                tm->tm_hour = 0;
                /* next day */
                tm->tm_wday++;
                if ((unsigned)tm->tm_wday >= 7)
                    tm->tm_wday = 0;
                days_in_month = get_days_in_month(tm->tm_mon,
                                                  tm->tm_year + 1900);
                tm->tm_mday++;
                if (tm->tm_mday < 1) {
                    tm->tm_mday = 1;
                } else if (tm->tm_mday > days_in_month) {
                    tm->tm_mday = 1;
                    tm->tm_mon++;
                    if (tm->tm_mon >= 12) {
                        tm->tm_mon = 0;
                        tm->tm_year++;
                    }
                }
            }
        }
    }
}


static void rtc_update_second(void *opaque)
{
    RTCState *s = opaque;
    int64_t delay;

    /* if the oscillator is not in normal operation, we do not update */
    if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
        s->next_second_time += ticks_per_sec;
        qemu_mod_timer(s->second_timer, s->next_second_time);
    } else {
        rtc_next_second(&s->current_tm);

        if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
            /* update in progress bit */
            s->cmos_data[RTC_REG_A] |= REG_A_UIP;
        }
        /* should be 244 us = 8 / 32768 seconds, but currently the
           timers do not have the necessary resolution. */
        delay = (ticks_per_sec * 1) / 100;
        if (delay < 1)
            delay = 1;
        qemu_mod_timer(s->second_timer2,
                       s->next_second_time + delay);
    }
}

static void rtc_update_second2(void *opaque)
{
    RTCState *s = opaque;

    if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
        rtc_copy_date(s);
    }

    /* check alarm */
    if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
        if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
             s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
            ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
             s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
            ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
             s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {

            s->cmos_data[RTC_REG_C] |= 0xa0;
            rtc_irq_raise(s->irq);
        }
    }

    /* update ended interrupt */
    if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
        s->cmos_data[RTC_REG_C] |= 0x90;
        rtc_irq_raise(s->irq);
    }

    /* clear update in progress bit */
    s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;

    s->next_second_time += ticks_per_sec;
    qemu_mod_timer(s->second_timer, s->next_second_time);
}

static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
{
    RTCState *s = opaque;
    int ret;
    if ((addr & 1) == 0) {
        return 0xff;
    } else {
        switch(s->cmos_index) {
        case RTC_SECONDS:
        case RTC_MINUTES:
        case RTC_HOURS:
        case RTC_DAY_OF_WEEK:
        case RTC_DAY_OF_MONTH:
        case RTC_MONTH:
        case RTC_YEAR:
            ret = s->cmos_data[s->cmos_index];
            break;
        case RTC_REG_A:
            ret = s->cmos_data[s->cmos_index];
            break;
        case RTC_REG_C:
            ret = s->cmos_data[s->cmos_index];
            qemu_irq_lower(s->irq);
            s->cmos_data[RTC_REG_C] = 0x00;
            break;
        default:
            ret = s->cmos_data[s->cmos_index];
            break;
        }
#ifdef DEBUG_CMOS
        printf("cmos: read index=0x%02x val=0x%02x\n",
               s->cmos_index, ret);
#endif
        return ret;
    }
}

void rtc_set_memory(RTCState *s, int addr, int val)
{
    if (addr >= 0 && addr <= 127)
        s->cmos_data[addr] = val;
}

void rtc_set_date(RTCState *s, const struct tm *tm)
{
    s->current_tm = *tm;
    rtc_copy_date(s);
}

/* PC cmos mappings */
#define REG_IBM_CENTURY_BYTE        0x32
#define REG_IBM_PS2_CENTURY_BYTE    0x37

static void rtc_set_date_from_host(RTCState *s)
{
    struct tm tm;
    int val;

    /* set the CMOS date */
    qemu_get_timedate(&tm, 0);
    rtc_set_date(s, &tm);

    val = to_bcd(s, (tm.tm_year / 100) + 19);
    rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
    rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
}

static void rtc_save(QEMUFile *f, void *opaque)
{
    RTCState *s = opaque;

    qemu_put_buffer(f, s->cmos_data, 128);
    qemu_put_8s(f, &s->cmos_index);

    qemu_put_be32(f, s->current_tm.tm_sec);
    qemu_put_be32(f, s->current_tm.tm_min);
    qemu_put_be32(f, s->current_tm.tm_hour);
    qemu_put_be32(f, s->current_tm.tm_wday);
    qemu_put_be32(f, s->current_tm.tm_mday);
    qemu_put_be32(f, s->current_tm.tm_mon);
    qemu_put_be32(f, s->current_tm.tm_year);

    qemu_put_timer(f, s->periodic_timer);
    qemu_put_be64(f, s->next_periodic_time);

    qemu_put_be64(f, s->next_second_time);
    qemu_put_timer(f, s->second_timer);
    qemu_put_timer(f, s->second_timer2);
}

static int rtc_load(QEMUFile *f, void *opaque, int version_id)
{
    RTCState *s = opaque;

    if (version_id != 1)
        return -EINVAL;

    qemu_get_buffer(f, s->cmos_data, 128);
    qemu_get_8s(f, &s->cmos_index);

    s->current_tm.tm_sec=qemu_get_be32(f);
    s->current_tm.tm_min=qemu_get_be32(f);
    s->current_tm.tm_hour=qemu_get_be32(f);
    s->current_tm.tm_wday=qemu_get_be32(f);
    s->current_tm.tm_mday=qemu_get_be32(f);
    s->current_tm.tm_mon=qemu_get_be32(f);
    s->current_tm.tm_year=qemu_get_be32(f);

    qemu_get_timer(f, s->periodic_timer);
    s->next_periodic_time=qemu_get_be64(f);

    s->next_second_time=qemu_get_be64(f);
    qemu_get_timer(f, s->second_timer);
    qemu_get_timer(f, s->second_timer2);
    return 0;
}

RTCState *rtc_init(int base, qemu_irq irq)
{
    RTCState *s;

    s = qemu_mallocz(sizeof(RTCState));
    if (!s)
        return NULL;

    s->irq = irq;
    s->cmos_data[RTC_REG_A] = 0x26;
    s->cmos_data[RTC_REG_B] = 0x02;
    s->cmos_data[RTC_REG_C] = 0x00;
    s->cmos_data[RTC_REG_D] = 0x80;

    rtc_set_date_from_host(s);

    s->periodic_timer = qemu_new_timer(vm_clock,
                                       rtc_periodic_timer, s);
    s->second_timer = qemu_new_timer(vm_clock,
                                     rtc_update_second, s);
    s->second_timer2 = qemu_new_timer(vm_clock,
                                      rtc_update_second2, s);

    s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
    qemu_mod_timer(s->second_timer2, s->next_second_time);

    register_ioport_write(base, 2, 1, cmos_ioport_write, s);
    register_ioport_read(base, 2, 1, cmos_ioport_read, s);

    register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
    return s;
}

/* Memory mapped interface */
static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
{
    RTCState *s = opaque;

    return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF;
}

static void cmos_mm_writeb (void *opaque,
                            target_phys_addr_t addr, uint32_t value)
{
    RTCState *s = opaque;

    cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
}

static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
{
    RTCState *s = opaque;
    uint32_t val;

    val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif
    return val;
}

static void cmos_mm_writew (void *opaque,
                            target_phys_addr_t addr, uint32_t value)
{
    RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap16(value);
#endif
    cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
}

static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
{
    RTCState *s = opaque;
    uint32_t val;

    val = cmos_ioport_read(s, addr >> s->it_shift);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    return val;
}

static void cmos_mm_writel (void *opaque,
                            target_phys_addr_t addr, uint32_t value)
{
    RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap32(value);
#endif
    cmos_ioport_write(s, addr >> s->it_shift, value);
}

static CPUReadMemoryFunc *rtc_mm_read[] = {
    &cmos_mm_readb,
    &cmos_mm_readw,
    &cmos_mm_readl,
};

static CPUWriteMemoryFunc *rtc_mm_write[] = {
    &cmos_mm_writeb,
    &cmos_mm_writew,
    &cmos_mm_writel,
};

RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
{
    RTCState *s;
    int io_memory;

    s = qemu_mallocz(sizeof(RTCState));
    if (!s)
        return NULL;

    s->irq = irq;
    s->cmos_data[RTC_REG_A] = 0x26;
    s->cmos_data[RTC_REG_B] = 0x02;
    s->cmos_data[RTC_REG_C] = 0x00;
    s->cmos_data[RTC_REG_D] = 0x80;

    rtc_set_date_from_host(s);

    s->periodic_timer = qemu_new_timer(vm_clock,
                                       rtc_periodic_timer, s);
    s->second_timer = qemu_new_timer(vm_clock,
                                     rtc_update_second, s);
    s->second_timer2 = qemu_new_timer(vm_clock,
                                      rtc_update_second2, s);

    s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
    qemu_mod_timer(s->second_timer2, s->next_second_time);

    io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
    cpu_register_physical_memory(base, 2 << it_shift, io_memory);

    register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
    return s;
}
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU MC146818 RTC emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "qemu-timer.h"
	26	#include "sysemu.h"
	27	#include "pc.h"
	28	#include "isa.h"
16b29ae1	29	#include "hpet_emul.h"
80cabfad FB	30
	31	//#define DEBUG_CMOS
	32
	33	#define RTC_SECONDS 0
	34	#define RTC_SECONDS_ALARM 1
	35	#define RTC_MINUTES 2
	36	#define RTC_MINUTES_ALARM 3
	37	#define RTC_HOURS 4
	38	#define RTC_HOURS_ALARM 5
	39	#define RTC_ALARM_DONT_CARE 0xC0
	40
	41	#define RTC_DAY_OF_WEEK 6
	42	#define RTC_DAY_OF_MONTH 7
	43	#define RTC_MONTH 8
	44	#define RTC_YEAR 9
	45
	46	#define RTC_REG_A 10
	47	#define RTC_REG_B 11
	48	#define RTC_REG_C 12
	49	#define RTC_REG_D 13
	50
dff38e7b	51	#define REG_A_UIP 0x80
80cabfad	52
dff38e7b FB	53	#define REG_B_SET 0x80
	54	#define REG_B_PIE 0x40
	55	#define REG_B_AIE 0x20
	56	#define REG_B_UIE 0x10
	57
	58	struct RTCState {
	59	uint8_t cmos_data[128];
	60	uint8_t cmos_index;
43f493af	61	struct tm current_tm;
d537cf6c	62	qemu_irq irq;
18c6e2ff	63	int it_shift;
dff38e7b FB	64	/* periodic timer */
	65	QEMUTimer *periodic_timer;
	66	int64_t next_periodic_time;
	67	/* second update */
	68	int64_t next_second_time;
	69	QEMUTimer *second_timer;
	70	QEMUTimer *second_timer2;
	71	};
	72
16b29ae1 AL	73	static void rtc_irq_raise(qemu_irq irq) {
	74	/* When HPET is operating in legacy mode, RTC interrupts are disabled
	75	* We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
	76	* mode is established while interrupt is raised. We want it to
	77	* be lowered in any case
	78	*/
	79	#if defined TARGET_I386 \|\| defined TARGET_X86_64
	80	if (!hpet_in_legacy_mode())
	81	#endif
	82	qemu_irq_raise(irq);
	83	}
	84
dff38e7b	85	static void rtc_set_time(RTCState *s);
dff38e7b FB	86	static void rtc_copy_date(RTCState *s);
	87
	88	static void rtc_timer_update(RTCState *s, int64_t current_time)
	89	{
	90	int period_code, period;
	91	int64_t cur_clock, next_irq_clock;
	92
	93	period_code = s->cmos_data[RTC_REG_A] & 0x0f;
16b29ae1 AL	94	#if defined TARGET_I386 \|\| defined TARGET_X86_64
	95	/* disable periodic timer if hpet is in legacy mode, since interrupts are
	96	* disabled anyway.
	97	*/
	98	if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE) && !hpet_in_legacy_mode()) {
	99	#else
	100	if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
	101	#endif
dff38e7b FB	102	if (period_code <= 2)
	103	period_code += 7;
	104	/* period in 32 Khz cycles */
	105	period = 1 << (period_code - 1);
	106	/* compute 32 khz clock */
	107	cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
	108	next_irq_clock = (cur_clock & ~(period - 1)) + period;
	109	s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1;
	110	qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
	111	} else {
	112	qemu_del_timer(s->periodic_timer);
	113	}
	114	}
	115
	116	static void rtc_periodic_timer(void *opaque)
	117	{
	118	RTCState *s = opaque;
	119
	120	rtc_timer_update(s, s->next_periodic_time);
	121	s->cmos_data[RTC_REG_C] \|= 0xc0;
16b29ae1	122	rtc_irq_raise(s->irq);
dff38e7b	123	}
80cabfad	124
b41a2cd1	125	static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
80cabfad	126	{
b41a2cd1	127	RTCState *s = opaque;
80cabfad FB	128
	129	if ((addr & 1) == 0) {
	130	s->cmos_index = data & 0x7f;
	131	} else {
	132	#ifdef DEBUG_CMOS
	133	printf("cmos: write index=0x%02x val=0x%02x\n",
	134	s->cmos_index, data);
3b46e624	135	#endif
dff38e7b	136	switch(s->cmos_index) {
80cabfad FB	137	case RTC_SECONDS_ALARM:
	138	case RTC_MINUTES_ALARM:
	139	case RTC_HOURS_ALARM:
	140	/* XXX: not supported */
	141	s->cmos_data[s->cmos_index] = data;
	142	break;
	143	case RTC_SECONDS:
	144	case RTC_MINUTES:
	145	case RTC_HOURS:
	146	case RTC_DAY_OF_WEEK:
	147	case RTC_DAY_OF_MONTH:
	148	case RTC_MONTH:
	149	case RTC_YEAR:
	150	s->cmos_data[s->cmos_index] = data;
dff38e7b FB	151	/* if in set mode, do not update the time */
	152	if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
	153	rtc_set_time(s);
	154	}
80cabfad FB	155	break;
80cabfad FB	156	case RTC_REG_A:
dff38e7b FB	157	/* UIP bit is read only */
	158	s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) \|
	159	(s->cmos_data[RTC_REG_A] & REG_A_UIP);
	160	rtc_timer_update(s, qemu_get_clock(vm_clock));
	161	break;
80cabfad	162	case RTC_REG_B:
dff38e7b FB	163	if (data & REG_B_SET) {
	164	/* set mode: reset UIP mode */
	165	s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
	166	data &= ~REG_B_UIE;
	167	} else {
	168	/* if disabling set mode, update the time */
	169	if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
	170	rtc_set_time(s);
	171	}
	172	}
	173	s->cmos_data[RTC_REG_B] = data;
	174	rtc_timer_update(s, qemu_get_clock(vm_clock));
80cabfad FB	175	break;
	176	case RTC_REG_C:
	177	case RTC_REG_D:
	178	/* cannot write to them */
	179	break;
	180	default:
	181	s->cmos_data[s->cmos_index] = data;
	182	break;
	183	}
	184	}
	185	}
	186
dff38e7b	187	static inline int to_bcd(RTCState *s, int a)
80cabfad	188	{
dff38e7b FB	189	if (s->cmos_data[RTC_REG_B] & 0x04) {
	190	return a;
	191	} else {
	192	return ((a / 10) << 4) \| (a % 10);
	193	}
80cabfad FB	194	}
80cabfad FB	195
dff38e7b	196	static inline int from_bcd(RTCState *s, int a)
80cabfad	197	{
dff38e7b FB	198	if (s->cmos_data[RTC_REG_B] & 0x04) {
	199	return a;
	200	} else {
	201	return ((a >> 4) * 10) + (a & 0x0f);
	202	}
	203	}
	204
	205	static void rtc_set_time(RTCState *s)
	206	{
43f493af	207	struct tm *tm = &s->current_tm;
dff38e7b FB	208
	209	tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
	210	tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
43f493af FB	211	tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
	212	if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
	213	(s->cmos_data[RTC_HOURS] & 0x80)) {
	214	tm->tm_hour += 12;
	215	}
dff38e7b FB	216	tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
	217	tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
	218	tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
	219	tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
43f493af FB	220	}
	221
	222	static void rtc_copy_date(RTCState *s)
	223	{
	224	const struct tm *tm = &s->current_tm;
dff38e7b	225
43f493af FB	226	s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
	227	s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
	228	if (s->cmos_data[RTC_REG_B] & 0x02) {
	229	/* 24 hour format */
	230	s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
	231	} else {
	232	/* 12 hour format */
	233	s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
	234	if (tm->tm_hour >= 12)
	235	s->cmos_data[RTC_HOURS] \|= 0x80;
	236	}
	237	s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
	238	s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
	239	s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
	240	s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
	241	}
	242
	243	/* month is between 0 and 11. */
	244	static int get_days_in_month(int month, int year)
	245	{
5fafdf24 TS	246	static const int days_tab[12] = {
5fafdf24 TS	247	31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
43f493af FB	248	};
	249	int d;
	250	if ((unsigned )month >= 12)
	251	return 31;
	252	d = days_tab[month];
	253	if (month == 1) {
	254	if ((year % 4) == 0 && ((year % 100) != 0 \|\| (year % 400) == 0))
	255	d++;
	256	}
	257	return d;
	258	}
	259
	260	/* update 'tm' to the next second */
	261	static void rtc_next_second(struct tm *tm)
	262	{
	263	int days_in_month;
	264
	265	tm->tm_sec++;
	266	if ((unsigned)tm->tm_sec >= 60) {
	267	tm->tm_sec = 0;
	268	tm->tm_min++;
	269	if ((unsigned)tm->tm_min >= 60) {
	270	tm->tm_min = 0;
	271	tm->tm_hour++;
	272	if ((unsigned)tm->tm_hour >= 24) {
	273	tm->tm_hour = 0;
	274	/* next day */
	275	tm->tm_wday++;
	276	if ((unsigned)tm->tm_wday >= 7)
	277	tm->tm_wday = 0;
5fafdf24	278	days_in_month = get_days_in_month(tm->tm_mon,
43f493af FB	279	tm->tm_year + 1900);
	280	tm->tm_mday++;
	281	if (tm->tm_mday < 1) {
	282	tm->tm_mday = 1;
	283	} else if (tm->tm_mday > days_in_month) {
	284	tm->tm_mday = 1;
	285	tm->tm_mon++;
	286	if (tm->tm_mon >= 12) {
	287	tm->tm_mon = 0;
	288	tm->tm_year++;
	289	}
	290	}
	291	}
	292	}
	293	}
dff38e7b FB	294	}
dff38e7b FB	295
43f493af	296
dff38e7b FB	297	static void rtc_update_second(void *opaque)
	298	{
	299	RTCState *s = opaque;
4721c457	300	int64_t delay;
dff38e7b FB	301
	302	/* if the oscillator is not in normal operation, we do not update */
	303	if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
	304	s->next_second_time += ticks_per_sec;
	305	qemu_mod_timer(s->second_timer, s->next_second_time);
	306	} else {
43f493af	307	rtc_next_second(&s->current_tm);
3b46e624	308
dff38e7b FB	309	if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
	310	/* update in progress bit */
	311	s->cmos_data[RTC_REG_A] \|= REG_A_UIP;
	312	}
4721c457 FB	313	/* should be 244 us = 8 / 32768 seconds, but currently the
	314	timers do not have the necessary resolution. */
	315	delay = (ticks_per_sec * 1) / 100;
	316	if (delay < 1)
	317	delay = 1;
5fafdf24	318	qemu_mod_timer(s->second_timer2,
4721c457	319	s->next_second_time + delay);
dff38e7b FB	320	}
	321	}
	322
	323	static void rtc_update_second2(void *opaque)
	324	{
	325	RTCState *s = opaque;
dff38e7b FB	326
	327	if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
	328	rtc_copy_date(s);
	329	}
	330
	331	/* check alarm */
	332	if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
	333	if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 \|\|
43f493af	334	s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
dff38e7b	335	((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 \|\|
43f493af	336	s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
dff38e7b	337	((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 \|\|
43f493af	338	s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
dff38e7b	339
5fafdf24	340	s->cmos_data[RTC_REG_C] \|= 0xa0;
16b29ae1	341	rtc_irq_raise(s->irq);
dff38e7b FB	342	}
	343	}
	344
	345	/* update ended interrupt */
	346	if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
5fafdf24	347	s->cmos_data[RTC_REG_C] \|= 0x90;
16b29ae1	348	rtc_irq_raise(s->irq);
dff38e7b FB	349	}
	350
	351	/* clear update in progress bit */
	352	s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
	353
	354	s->next_second_time += ticks_per_sec;
	355	qemu_mod_timer(s->second_timer, s->next_second_time);
80cabfad FB	356	}
80cabfad FB	357
b41a2cd1	358	static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
80cabfad	359	{
b41a2cd1	360	RTCState *s = opaque;
80cabfad FB	361	int ret;
	362	if ((addr & 1) == 0) {
	363	return 0xff;
	364	} else {
	365	switch(s->cmos_index) {
	366	case RTC_SECONDS:
	367	case RTC_MINUTES:
	368	case RTC_HOURS:
	369	case RTC_DAY_OF_WEEK:
	370	case RTC_DAY_OF_MONTH:
	371	case RTC_MONTH:
	372	case RTC_YEAR:
80cabfad FB	373	ret = s->cmos_data[s->cmos_index];
	374	break;
	375	case RTC_REG_A:
	376	ret = s->cmos_data[s->cmos_index];
80cabfad FB	377	break;
	378	case RTC_REG_C:
	379	ret = s->cmos_data[s->cmos_index];
d537cf6c	380	qemu_irq_lower(s->irq);
5fafdf24	381	s->cmos_data[RTC_REG_C] = 0x00;
80cabfad FB	382	break;
	383	default:
	384	ret = s->cmos_data[s->cmos_index];
	385	break;
	386	}
	387	#ifdef DEBUG_CMOS
	388	printf("cmos: read index=0x%02x val=0x%02x\n",
	389	s->cmos_index, ret);
	390	#endif
	391	return ret;
	392	}
	393	}
	394
dff38e7b FB	395	void rtc_set_memory(RTCState *s, int addr, int val)
	396	{
	397	if (addr >= 0 && addr <= 127)
	398	s->cmos_data[addr] = val;
	399	}
	400
	401	void rtc_set_date(RTCState s, const struct tm tm)
	402	{
43f493af	403	s->current_tm = *tm;
dff38e7b FB	404	rtc_copy_date(s);
	405	}
	406
ea55ffb3 TS	407	/* PC cmos mappings */
	408	#define REG_IBM_CENTURY_BYTE 0x32
	409	#define REG_IBM_PS2_CENTURY_BYTE 0x37
	410
9596ebb7	411	static void rtc_set_date_from_host(RTCState *s)
ea55ffb3	412	{
f6503059	413	struct tm tm;
ea55ffb3 TS	414	int val;
	415
	416	/* set the CMOS date */
f6503059 AZ	417	qemu_get_timedate(&tm, 0);
f6503059 AZ	418	rtc_set_date(s, &tm);
ea55ffb3	419
f6503059	420	val = to_bcd(s, (tm.tm_year / 100) + 19);
ea55ffb3 TS	421	rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
	422	rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
	423	}
	424
dff38e7b FB	425	static void rtc_save(QEMUFile f, void opaque)
	426	{
	427	RTCState *s = opaque;
	428
	429	qemu_put_buffer(f, s->cmos_data, 128);
	430	qemu_put_8s(f, &s->cmos_index);
3b46e624	431
bee8d684 TS	432	qemu_put_be32(f, s->current_tm.tm_sec);
	433	qemu_put_be32(f, s->current_tm.tm_min);
	434	qemu_put_be32(f, s->current_tm.tm_hour);
	435	qemu_put_be32(f, s->current_tm.tm_wday);
	436	qemu_put_be32(f, s->current_tm.tm_mday);
	437	qemu_put_be32(f, s->current_tm.tm_mon);
	438	qemu_put_be32(f, s->current_tm.tm_year);
dff38e7b FB	439
dff38e7b FB	440	qemu_put_timer(f, s->periodic_timer);
bee8d684	441	qemu_put_be64(f, s->next_periodic_time);
dff38e7b	442
bee8d684	443	qemu_put_be64(f, s->next_second_time);
dff38e7b FB	444	qemu_put_timer(f, s->second_timer);
dff38e7b FB	445	qemu_put_timer(f, s->second_timer2);
80cabfad FB	446	}
80cabfad FB	447
dff38e7b	448	static int rtc_load(QEMUFile f, void opaque, int version_id)
80cabfad	449	{
dff38e7b FB	450	RTCState *s = opaque;
	451
	452	if (version_id != 1)
	453	return -EINVAL;
80cabfad	454
dff38e7b FB	455	qemu_get_buffer(f, s->cmos_data, 128);
dff38e7b FB	456	qemu_get_8s(f, &s->cmos_index);
43f493af	457
bee8d684 TS	458	s->current_tm.tm_sec=qemu_get_be32(f);
	459	s->current_tm.tm_min=qemu_get_be32(f);
	460	s->current_tm.tm_hour=qemu_get_be32(f);
	461	s->current_tm.tm_wday=qemu_get_be32(f);
	462	s->current_tm.tm_mday=qemu_get_be32(f);
	463	s->current_tm.tm_mon=qemu_get_be32(f);
	464	s->current_tm.tm_year=qemu_get_be32(f);
dff38e7b FB	465
dff38e7b FB	466	qemu_get_timer(f, s->periodic_timer);
bee8d684	467	s->next_periodic_time=qemu_get_be64(f);
dff38e7b	468
bee8d684	469	s->next_second_time=qemu_get_be64(f);
dff38e7b FB	470	qemu_get_timer(f, s->second_timer);
	471	qemu_get_timer(f, s->second_timer2);
	472	return 0;
	473	}
	474
d537cf6c	475	RTCState *rtc_init(int base, qemu_irq irq)
dff38e7b FB	476	{
	477	RTCState *s;
	478
	479	s = qemu_mallocz(sizeof(RTCState));
	480	if (!s)
	481	return NULL;
80cabfad FB	482
	483	s->irq = irq;
	484	s->cmos_data[RTC_REG_A] = 0x26;
	485	s->cmos_data[RTC_REG_B] = 0x02;
	486	s->cmos_data[RTC_REG_C] = 0x00;
	487	s->cmos_data[RTC_REG_D] = 0x80;
	488
ea55ffb3 TS	489	rtc_set_date_from_host(s);
ea55ffb3 TS	490
5fafdf24	491	s->periodic_timer = qemu_new_timer(vm_clock,
dff38e7b	492	rtc_periodic_timer, s);
5fafdf24	493	s->second_timer = qemu_new_timer(vm_clock,
dff38e7b	494	rtc_update_second, s);
5fafdf24	495	s->second_timer2 = qemu_new_timer(vm_clock,
dff38e7b FB	496	rtc_update_second2, s);
	497
	498	s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
	499	qemu_mod_timer(s->second_timer2, s->next_second_time);
	500
b41a2cd1 FB	501	register_ioport_write(base, 2, 1, cmos_ioport_write, s);
b41a2cd1 FB	502	register_ioport_read(base, 2, 1, cmos_ioport_read, s);
dff38e7b FB	503
	504	register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
	505	return s;
80cabfad FB	506	}
80cabfad FB	507
2ca9d013	508	/* Memory mapped interface */
9596ebb7	509	static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
2ca9d013 TS	510	{
	511	RTCState *s = opaque;
	512
8da3ff18	513	return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF;
2ca9d013 TS	514	}
2ca9d013 TS	515
9596ebb7 PB	516	static void cmos_mm_writeb (void *opaque,
9596ebb7 PB	517	target_phys_addr_t addr, uint32_t value)
2ca9d013 TS	518	{
	519	RTCState *s = opaque;
	520
8da3ff18	521	cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
2ca9d013 TS	522	}
2ca9d013 TS	523
9596ebb7	524	static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
2ca9d013 TS	525	{
2ca9d013 TS	526	RTCState *s = opaque;
18c6e2ff	527	uint32_t val;
2ca9d013	528
8da3ff18	529	val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
18c6e2ff TS	530	#ifdef TARGET_WORDS_BIGENDIAN
	531	val = bswap16(val);
	532	#endif
	533	return val;
2ca9d013 TS	534	}
2ca9d013 TS	535
9596ebb7 PB	536	static void cmos_mm_writew (void *opaque,
9596ebb7 PB	537	target_phys_addr_t addr, uint32_t value)
2ca9d013 TS	538	{
2ca9d013 TS	539	RTCState *s = opaque;
18c6e2ff TS	540	#ifdef TARGET_WORDS_BIGENDIAN
	541	value = bswap16(value);
	542	#endif
8da3ff18	543	cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
2ca9d013 TS	544	}
2ca9d013 TS	545
9596ebb7	546	static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
2ca9d013 TS	547	{
2ca9d013 TS	548	RTCState *s = opaque;
18c6e2ff	549	uint32_t val;
2ca9d013	550
8da3ff18	551	val = cmos_ioport_read(s, addr >> s->it_shift);
18c6e2ff TS	552	#ifdef TARGET_WORDS_BIGENDIAN
	553	val = bswap32(val);
	554	#endif
	555	return val;
2ca9d013 TS	556	}
2ca9d013 TS	557
9596ebb7 PB	558	static void cmos_mm_writel (void *opaque,
9596ebb7 PB	559	target_phys_addr_t addr, uint32_t value)
2ca9d013 TS	560	{
2ca9d013 TS	561	RTCState *s = opaque;
18c6e2ff TS	562	#ifdef TARGET_WORDS_BIGENDIAN
	563	value = bswap32(value);
	564	#endif
8da3ff18	565	cmos_ioport_write(s, addr >> s->it_shift, value);
2ca9d013 TS	566	}
	567
	568	static CPUReadMemoryFunc *rtc_mm_read[] = {
	569	&cmos_mm_readb,
	570	&cmos_mm_readw,
	571	&cmos_mm_readl,
	572	};
	573
	574	static CPUWriteMemoryFunc *rtc_mm_write[] = {
	575	&cmos_mm_writeb,
	576	&cmos_mm_writew,
	577	&cmos_mm_writel,
	578	};
	579
18c6e2ff	580	RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
2ca9d013 TS	581	{
	582	RTCState *s;
	583	int io_memory;
	584
	585	s = qemu_mallocz(sizeof(RTCState));
	586	if (!s)
	587	return NULL;
	588
	589	s->irq = irq;
	590	s->cmos_data[RTC_REG_A] = 0x26;
	591	s->cmos_data[RTC_REG_B] = 0x02;
	592	s->cmos_data[RTC_REG_C] = 0x00;
	593	s->cmos_data[RTC_REG_D] = 0x80;
2ca9d013 TS	594
	595	rtc_set_date_from_host(s);
	596
	597	s->periodic_timer = qemu_new_timer(vm_clock,
	598	rtc_periodic_timer, s);
	599	s->second_timer = qemu_new_timer(vm_clock,
	600	rtc_update_second, s);
	601	s->second_timer2 = qemu_new_timer(vm_clock,
	602	rtc_update_second2, s);
	603
	604	s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
	605	qemu_mod_timer(s->second_timer2, s->next_second_time);
	606
	607	io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
18c6e2ff	608	cpu_register_physical_memory(base, 2 << it_shift, io_memory);
2ca9d013 TS	609
	610	register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
	611	return s;
	612	}