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5fafdf24 1/*
0633879f
PB
2 * Motorola ColdFire MCF5206 SoC embedded peripheral emulation.
3 *
4 * Copyright (c) 2007 CodeSourcery.
5 *
8e31bf38 6 * This code is licensed under the GPL
0633879f 7 */
87ecb68b
PB
8#include "hw.h"
9#include "mcf.h"
10#include "qemu-timer.h"
11#include "sysemu.h"
653fa85c 12#include "exec-memory.h"
0633879f
PB
13
14/* General purpose timer module. */
15typedef struct {
16 uint16_t tmr;
17 uint16_t trr;
18 uint16_t tcr;
19 uint16_t ter;
20 ptimer_state *timer;
21 qemu_irq irq;
22 int irq_state;
23} m5206_timer_state;
24
25#define TMR_RST 0x01
26#define TMR_CLK 0x06
27#define TMR_FRR 0x08
28#define TMR_ORI 0x10
29#define TMR_OM 0x20
30#define TMR_CE 0xc0
31
32#define TER_CAP 0x01
33#define TER_REF 0x02
34
35static void m5206_timer_update(m5206_timer_state *s)
36{
37 if ((s->tmr & TMR_ORI) != 0 && (s->ter & TER_REF))
38 qemu_irq_raise(s->irq);
39 else
40 qemu_irq_lower(s->irq);
41}
42
43static void m5206_timer_reset(m5206_timer_state *s)
44{
45 s->tmr = 0;
46 s->trr = 0;
47}
48
49static void m5206_timer_recalibrate(m5206_timer_state *s)
50{
51 int prescale;
52 int mode;
53
54 ptimer_stop(s->timer);
55
56 if ((s->tmr & TMR_RST) == 0)
57 return;
58
59 prescale = (s->tmr >> 8) + 1;
60 mode = (s->tmr >> 1) & 3;
61 if (mode == 2)
62 prescale *= 16;
63
64 if (mode == 3 || mode == 0)
2ac71179 65 hw_error("m5206_timer: mode %d not implemented\n", mode);
0633879f 66 if ((s->tmr & TMR_FRR) == 0)
2ac71179 67 hw_error("m5206_timer: free running mode not implemented\n");
0633879f
PB
68
69 /* Assume 66MHz system clock. */
70 ptimer_set_freq(s->timer, 66000000 / prescale);
71
72 ptimer_set_limit(s->timer, s->trr, 0);
73
74 ptimer_run(s->timer, 0);
75}
76
77static void m5206_timer_trigger(void *opaque)
78{
79 m5206_timer_state *s = (m5206_timer_state *)opaque;
80 s->ter |= TER_REF;
81 m5206_timer_update(s);
82}
83
84static uint32_t m5206_timer_read(m5206_timer_state *s, uint32_t addr)
85{
86 switch (addr) {
87 case 0:
88 return s->tmr;
89 case 4:
90 return s->trr;
91 case 8:
92 return s->tcr;
93 case 0xc:
94 return s->trr - ptimer_get_count(s->timer);
95 case 0x11:
96 return s->ter;
97 default:
98 return 0;
99 }
100}
101
102static void m5206_timer_write(m5206_timer_state *s, uint32_t addr, uint32_t val)
103{
104 switch (addr) {
105 case 0:
106 if ((s->tmr & TMR_RST) != 0 && (val & TMR_RST) == 0) {
107 m5206_timer_reset(s);
108 }
109 s->tmr = val;
110 m5206_timer_recalibrate(s);
111 break;
112 case 4:
113 s->trr = val;
114 m5206_timer_recalibrate(s);
115 break;
116 case 8:
117 s->tcr = val;
118 break;
119 case 0xc:
120 ptimer_set_count(s->timer, val);
121 break;
122 case 0x11:
123 s->ter &= ~val;
124 break;
125 default:
126 break;
127 }
128 m5206_timer_update(s);
129}
130
131static m5206_timer_state *m5206_timer_init(qemu_irq irq)
132{
133 m5206_timer_state *s;
134 QEMUBH *bh;
135
7267c094 136 s = (m5206_timer_state *)g_malloc0(sizeof(m5206_timer_state));
0633879f
PB
137 bh = qemu_bh_new(m5206_timer_trigger, s);
138 s->timer = ptimer_init(bh);
139 s->irq = irq;
140 m5206_timer_reset(s);
141 return s;
142}
143
0633879f
PB
144/* System Integration Module. */
145
146typedef struct {
147 CPUState *env;
653fa85c 148 MemoryRegion iomem;
0633879f 149 m5206_timer_state *timer[2];
20dcee94 150 void *uart[2];
0633879f
PB
151 uint8_t scr;
152 uint8_t icr[14];
153 uint16_t imr; /* 1 == interrupt is masked. */
154 uint16_t ipr;
155 uint8_t rsr;
156 uint8_t swivr;
157 uint8_t par;
158 /* Include the UART vector registers here. */
159 uint8_t uivr[2];
160} m5206_mbar_state;
161
162/* Interrupt controller. */
163
164static int m5206_find_pending_irq(m5206_mbar_state *s)
165{
166 int level;
167 int vector;
168 uint16_t active;
169 int i;
170
171 level = 0;
172 vector = 0;
173 active = s->ipr & ~s->imr;
174 if (!active)
175 return 0;
176
177 for (i = 1; i < 14; i++) {
178 if (active & (1 << i)) {
179 if ((s->icr[i] & 0x1f) > level) {
180 level = s->icr[i] & 0x1f;
181 vector = i;
182 }
183 }
184 }
185
186 if (level < 4)
187 vector = 0;
188
189 return vector;
190}
191
192static void m5206_mbar_update(m5206_mbar_state *s)
193{
194 int irq;
195 int vector;
196 int level;
197
198 irq = m5206_find_pending_irq(s);
199 if (irq) {
200 int tmp;
201 tmp = s->icr[irq];
202 level = (tmp >> 2) & 7;
203 if (tmp & 0x80) {
204 /* Autovector. */
205 vector = 24 + level;
206 } else {
207 switch (irq) {
208 case 8: /* SWT */
209 vector = s->swivr;
210 break;
211 case 12: /* UART1 */
212 vector = s->uivr[0];
213 break;
214 case 13: /* UART2 */
215 vector = s->uivr[1];
216 break;
217 default:
218 /* Unknown vector. */
219 fprintf(stderr, "Unhandled vector for IRQ %d\n", irq);
220 vector = 0xf;
221 break;
222 }
223 }
224 } else {
225 level = 0;
226 vector = 0;
227 }
228 m68k_set_irq_level(s->env, level, vector);
229}
230
231static void m5206_mbar_set_irq(void *opaque, int irq, int level)
232{
233 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
234 if (level) {
235 s->ipr |= 1 << irq;
236 } else {
237 s->ipr &= ~(1 << irq);
238 }
239 m5206_mbar_update(s);
240}
241
242/* System Integration Module. */
243
244static void m5206_mbar_reset(m5206_mbar_state *s)
245{
246 s->scr = 0xc0;
247 s->icr[1] = 0x04;
248 s->icr[2] = 0x08;
249 s->icr[3] = 0x0c;
250 s->icr[4] = 0x10;
251 s->icr[5] = 0x14;
252 s->icr[6] = 0x18;
253 s->icr[7] = 0x1c;
254 s->icr[8] = 0x1c;
255 s->icr[9] = 0x80;
256 s->icr[10] = 0x80;
257 s->icr[11] = 0x80;
258 s->icr[12] = 0x00;
259 s->icr[13] = 0x00;
260 s->imr = 0x3ffe;
261 s->rsr = 0x80;
262 s->swivr = 0x0f;
263 s->par = 0;
264}
265
aa6e4986
BC
266static uint64_t m5206_mbar_read(m5206_mbar_state *s,
267 uint64_t offset, unsigned size)
0633879f
PB
268{
269 if (offset >= 0x100 && offset < 0x120) {
270 return m5206_timer_read(s->timer[0], offset - 0x100);
271 } else if (offset >= 0x120 && offset < 0x140) {
272 return m5206_timer_read(s->timer[1], offset - 0x120);
273 } else if (offset >= 0x140 && offset < 0x160) {
aa6e4986 274 return mcf_uart_read(s->uart[0], offset - 0x140, size);
0633879f 275 } else if (offset >= 0x180 && offset < 0x1a0) {
aa6e4986 276 return mcf_uart_read(s->uart[1], offset - 0x180, size);
0633879f
PB
277 }
278 switch (offset) {
279 case 0x03: return s->scr;
280 case 0x14 ... 0x20: return s->icr[offset - 0x13];
281 case 0x36: return s->imr;
282 case 0x3a: return s->ipr;
283 case 0x40: return s->rsr;
284 case 0x41: return 0;
285 case 0x42: return s->swivr;
286 case 0x50:
287 /* DRAM mask register. */
288 /* FIXME: currently hardcoded to 128Mb. */
289 {
290 uint32_t mask = ~0;
291 while (mask > ram_size)
292 mask >>= 1;
293 return mask & 0x0ffe0000;
294 }
295 case 0x5c: return 1; /* DRAM bank 1 empty. */
296 case 0xcb: return s->par;
297 case 0x170: return s->uivr[0];
298 case 0x1b0: return s->uivr[1];
299 }
2ac71179 300 hw_error("Bad MBAR read offset 0x%x", (int)offset);
0633879f
PB
301 return 0;
302}
303
304static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset,
aa6e4986 305 uint64_t value, unsigned size)
0633879f
PB
306{
307 if (offset >= 0x100 && offset < 0x120) {
308 m5206_timer_write(s->timer[0], offset - 0x100, value);
309 return;
310 } else if (offset >= 0x120 && offset < 0x140) {
311 m5206_timer_write(s->timer[1], offset - 0x120, value);
312 return;
313 } else if (offset >= 0x140 && offset < 0x160) {
aa6e4986 314 mcf_uart_write(s->uart[0], offset - 0x140, value, size);
0633879f
PB
315 return;
316 } else if (offset >= 0x180 && offset < 0x1a0) {
aa6e4986 317 mcf_uart_write(s->uart[1], offset - 0x180, value, size);
0633879f
PB
318 return;
319 }
320 switch (offset) {
321 case 0x03:
322 s->scr = value;
323 break;
324 case 0x14 ... 0x20:
325 s->icr[offset - 0x13] = value;
326 m5206_mbar_update(s);
327 break;
328 case 0x36:
329 s->imr = value;
330 m5206_mbar_update(s);
331 break;
332 case 0x40:
333 s->rsr &= ~value;
334 break;
335 case 0x41:
336 /* TODO: implement watchdog. */
337 break;
338 case 0x42:
339 s->swivr = value;
340 break;
341 case 0xcb:
342 s->par = value;
343 break;
344 case 0x170:
345 s->uivr[0] = value;
346 break;
347 case 0x178: case 0x17c: case 0x1c8: case 0x1bc:
348 /* Not implemented: UART Output port bits. */
349 break;
350 case 0x1b0:
351 s->uivr[1] = value;
352 break;
353 default:
2ac71179 354 hw_error("Bad MBAR write offset 0x%x", (int)offset);
0633879f
PB
355 break;
356 }
357}
358
359/* Internal peripherals use a variety of register widths.
360 This lookup table allows a single routine to handle all of them. */
5fafdf24 361static const int m5206_mbar_width[] =
0633879f
PB
362{
363 /* 000-040 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
364 /* 040-080 */ 1, 2, 2, 2, 4, 1, 2, 4, 1, 2, 4, 2, 2, 4, 2, 2,
365 /* 080-0c0 */ 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4,
366 /* 0c0-100 */ 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
367 /* 100-140 */ 2, 2, 2, 2, 1, 0, 0, 0, 2, 2, 2, 2, 1, 0, 0, 0,
368 /* 140-180 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
369 /* 180-1c0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
370 /* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
371};
372
c227f099
AL
373static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset);
374static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset);
0633879f 375
c227f099 376static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
0633879f
PB
377{
378 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
379 offset &= 0x3ff;
380 if (offset > 0x200) {
2ac71179 381 hw_error("Bad MBAR read offset 0x%x", (int)offset);
0633879f
PB
382 }
383 if (m5206_mbar_width[offset >> 2] > 1) {
384 uint16_t val;
385 val = m5206_mbar_readw(opaque, offset & ~1);
386 if ((offset & 1) == 0) {
387 val >>= 8;
388 }
389 return val & 0xff;
390 }
aa6e4986 391 return m5206_mbar_read(s, offset, 1);
0633879f
PB
392}
393
c227f099 394static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
0633879f
PB
395{
396 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
397 int width;
398 offset &= 0x3ff;
399 if (offset > 0x200) {
2ac71179 400 hw_error("Bad MBAR read offset 0x%x", (int)offset);
0633879f
PB
401 }
402 width = m5206_mbar_width[offset >> 2];
403 if (width > 2) {
404 uint32_t val;
405 val = m5206_mbar_readl(opaque, offset & ~3);
406 if ((offset & 3) == 0)
407 val >>= 16;
408 return val & 0xffff;
409 } else if (width < 2) {
410 uint16_t val;
411 val = m5206_mbar_readb(opaque, offset) << 8;
412 val |= m5206_mbar_readb(opaque, offset + 1);
413 return val;
414 }
aa6e4986 415 return m5206_mbar_read(s, offset, 2);
0633879f
PB
416}
417
c227f099 418static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
0633879f
PB
419{
420 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
421 int width;
422 offset &= 0x3ff;
423 if (offset > 0x200) {
2ac71179 424 hw_error("Bad MBAR read offset 0x%x", (int)offset);
0633879f
PB
425 }
426 width = m5206_mbar_width[offset >> 2];
427 if (width < 4) {
428 uint32_t val;
429 val = m5206_mbar_readw(opaque, offset) << 16;
430 val |= m5206_mbar_readw(opaque, offset + 2);
431 return val;
432 }
aa6e4986 433 return m5206_mbar_read(s, offset, 4);
0633879f
PB
434}
435
c227f099 436static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
0633879f 437 uint32_t value);
c227f099 438static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
0633879f
PB
439 uint32_t value);
440
c227f099 441static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
0633879f
PB
442 uint32_t value)
443{
444 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
445 int width;
446 offset &= 0x3ff;
447 if (offset > 0x200) {
2ac71179 448 hw_error("Bad MBAR write offset 0x%x", (int)offset);
0633879f
PB
449 }
450 width = m5206_mbar_width[offset >> 2];
451 if (width > 1) {
452 uint32_t tmp;
453 tmp = m5206_mbar_readw(opaque, offset & ~1);
454 if (offset & 1) {
455 tmp = (tmp & 0xff00) | value;
456 } else {
457 tmp = (tmp & 0x00ff) | (value << 8);
458 }
459 m5206_mbar_writew(opaque, offset & ~1, tmp);
460 return;
461 }
aa6e4986 462 m5206_mbar_write(s, offset, value, 1);
0633879f
PB
463}
464
c227f099 465static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
0633879f
PB
466 uint32_t value)
467{
468 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
469 int width;
470 offset &= 0x3ff;
471 if (offset > 0x200) {
2ac71179 472 hw_error("Bad MBAR write offset 0x%x", (int)offset);
0633879f
PB
473 }
474 width = m5206_mbar_width[offset >> 2];
475 if (width > 2) {
476 uint32_t tmp;
477 tmp = m5206_mbar_readl(opaque, offset & ~3);
478 if (offset & 3) {
479 tmp = (tmp & 0xffff0000) | value;
480 } else {
481 tmp = (tmp & 0x0000ffff) | (value << 16);
482 }
483 m5206_mbar_writel(opaque, offset & ~3, tmp);
484 return;
485 } else if (width < 2) {
486 m5206_mbar_writeb(opaque, offset, value >> 8);
487 m5206_mbar_writeb(opaque, offset + 1, value & 0xff);
488 return;
489 }
aa6e4986 490 m5206_mbar_write(s, offset, value, 2);
0633879f
PB
491}
492
c227f099 493static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
0633879f
PB
494 uint32_t value)
495{
496 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
497 int width;
498 offset &= 0x3ff;
499 if (offset > 0x200) {
2ac71179 500 hw_error("Bad MBAR write offset 0x%x", (int)offset);
0633879f
PB
501 }
502 width = m5206_mbar_width[offset >> 2];
503 if (width < 4) {
504 m5206_mbar_writew(opaque, offset, value >> 16);
505 m5206_mbar_writew(opaque, offset + 2, value & 0xffff);
506 return;
507 }
aa6e4986 508 m5206_mbar_write(s, offset, value, 4);
0633879f
PB
509}
510
653fa85c
BC
511static const MemoryRegionOps m5206_mbar_ops = {
512 .old_mmio = {
513 .read = {
514 m5206_mbar_readb,
515 m5206_mbar_readw,
516 m5206_mbar_readl,
517 },
518 .write = {
519 m5206_mbar_writeb,
520 m5206_mbar_writew,
521 m5206_mbar_writel,
522 },
523 },
524 .endianness = DEVICE_NATIVE_ENDIAN,
0633879f
PB
525};
526
653fa85c 527qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, CPUState *env)
0633879f
PB
528{
529 m5206_mbar_state *s;
530 qemu_irq *pic;
0633879f 531
7267c094 532 s = (m5206_mbar_state *)g_malloc0(sizeof(m5206_mbar_state));
653fa85c
BC
533
534 memory_region_init_io(&s->iomem, &m5206_mbar_ops, s,
535 "mbar", 0x00001000);
536 memory_region_add_subregion(sysmem, base, &s->iomem);
0633879f
PB
537
538 pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);
539 s->timer[0] = m5206_timer_init(pic[9]);
540 s->timer[1] = m5206_timer_init(pic[10]);
20dcee94
PB
541 s->uart[0] = mcf_uart_init(pic[12], serial_hds[0]);
542 s->uart[1] = mcf_uart_init(pic[13], serial_hds[1]);
0633879f
PB
543 s->env = env;
544
545 m5206_mbar_reset(s);
546 return pic;
547}