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df1d8a1f PB |
1 | /* |
2 | * MIPS Boston development board emulation. | |
3 | * | |
4 | * Copyright (c) 2016 Imagination Technologies | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
fc6b3cf9 | 21 | #include "qemu/units.h" |
df1d8a1f PB |
22 | |
23 | #include "exec/address-spaces.h" | |
24 | #include "hw/boards.h" | |
25 | #include "hw/char/serial.h" | |
df1d8a1f PB |
26 | #include "hw/ide/pci.h" |
27 | #include "hw/ide/ahci.h" | |
28 | #include "hw/loader.h" | |
29 | #include "hw/loader-fit.h" | |
30 | #include "hw/mips/cps.h" | |
31 | #include "hw/mips/cpudevs.h" | |
32 | #include "hw/pci-host/xilinx-pcie.h" | |
6b290b41 | 33 | #include "hw/qdev-clock.h" |
a27bd6c7 | 34 | #include "hw/qdev-properties.h" |
df1d8a1f | 35 | #include "qapi/error.h" |
df1d8a1f PB |
36 | #include "qemu/error-report.h" |
37 | #include "qemu/log.h" | |
8228e353 | 38 | #include "chardev/char.h" |
df1d8a1f PB |
39 | #include "sysemu/device_tree.h" |
40 | #include "sysemu/sysemu.h" | |
41 | #include "sysemu/qtest.h" | |
54d31236 | 42 | #include "sysemu/runstate.h" |
df1d8a1f PB |
43 | |
44 | #include <libfdt.h> | |
db1015e9 | 45 | #include "qom/object.h" |
df1d8a1f | 46 | |
27cf0896 | 47 | #define TYPE_BOSTON "mips-boston" |
db1015e9 | 48 | typedef struct BostonState BostonState; |
8110fa1d | 49 | DECLARE_INSTANCE_CHECKER(BostonState, BOSTON, |
27cf0896 | 50 | TYPE_BOSTON) |
df1d8a1f | 51 | |
db1015e9 | 52 | struct BostonState { |
df1d8a1f PB |
53 | SysBusDevice parent_obj; |
54 | ||
55 | MachineState *mach; | |
2d5fac80 | 56 | MIPSCPSState cps; |
490a9d9b | 57 | SerialMM *uart; |
6b290b41 | 58 | Clock *cpuclk; |
df1d8a1f PB |
59 | |
60 | CharBackend lcd_display; | |
61 | char lcd_content[8]; | |
62 | bool lcd_inited; | |
63 | ||
64 | hwaddr kernel_entry; | |
65 | hwaddr fdt_base; | |
db1015e9 | 66 | }; |
df1d8a1f PB |
67 | |
68 | enum boston_plat_reg { | |
69 | PLAT_FPGA_BUILD = 0x00, | |
70 | PLAT_CORE_CL = 0x04, | |
71 | PLAT_WRAPPER_CL = 0x08, | |
72 | PLAT_SYSCLK_STATUS = 0x0c, | |
73 | PLAT_SOFTRST_CTL = 0x10, | |
74 | #define PLAT_SOFTRST_CTL_SYSRESET (1 << 4) | |
75 | PLAT_DDR3_STATUS = 0x14, | |
76 | #define PLAT_DDR3_STATUS_LOCKED (1 << 0) | |
77 | #define PLAT_DDR3_STATUS_CALIBRATED (1 << 2) | |
78 | PLAT_PCIE_STATUS = 0x18, | |
79 | #define PLAT_PCIE_STATUS_PCIE0_LOCKED (1 << 0) | |
80 | #define PLAT_PCIE_STATUS_PCIE1_LOCKED (1 << 8) | |
81 | #define PLAT_PCIE_STATUS_PCIE2_LOCKED (1 << 16) | |
82 | PLAT_FLASH_CTL = 0x1c, | |
83 | PLAT_SPARE0 = 0x20, | |
84 | PLAT_SPARE1 = 0x24, | |
85 | PLAT_SPARE2 = 0x28, | |
86 | PLAT_SPARE3 = 0x2c, | |
87 | PLAT_MMCM_DIV = 0x30, | |
88 | #define PLAT_MMCM_DIV_CLK0DIV_SHIFT 0 | |
89 | #define PLAT_MMCM_DIV_INPUT_SHIFT 8 | |
90 | #define PLAT_MMCM_DIV_MUL_SHIFT 16 | |
91 | #define PLAT_MMCM_DIV_CLK1DIV_SHIFT 24 | |
92 | PLAT_BUILD_CFG = 0x34, | |
93 | #define PLAT_BUILD_CFG_IOCU_EN (1 << 0) | |
94 | #define PLAT_BUILD_CFG_PCIE0_EN (1 << 1) | |
95 | #define PLAT_BUILD_CFG_PCIE1_EN (1 << 2) | |
96 | #define PLAT_BUILD_CFG_PCIE2_EN (1 << 3) | |
97 | PLAT_DDR_CFG = 0x38, | |
98 | #define PLAT_DDR_CFG_SIZE (0xf << 0) | |
99 | #define PLAT_DDR_CFG_MHZ (0xfff << 4) | |
100 | PLAT_NOC_PCIE0_ADDR = 0x3c, | |
101 | PLAT_NOC_PCIE1_ADDR = 0x40, | |
102 | PLAT_NOC_PCIE2_ADDR = 0x44, | |
103 | PLAT_SYS_CTL = 0x48, | |
104 | }; | |
105 | ||
083b266f | 106 | static void boston_lcd_event(void *opaque, QEMUChrEvent event) |
df1d8a1f PB |
107 | { |
108 | BostonState *s = opaque; | |
109 | if (event == CHR_EVENT_OPENED && !s->lcd_inited) { | |
110 | qemu_chr_fe_printf(&s->lcd_display, " "); | |
111 | s->lcd_inited = true; | |
112 | } | |
113 | } | |
114 | ||
115 | static uint64_t boston_lcd_read(void *opaque, hwaddr addr, | |
116 | unsigned size) | |
117 | { | |
118 | BostonState *s = opaque; | |
119 | uint64_t val = 0; | |
120 | ||
121 | switch (size) { | |
122 | case 8: | |
123 | val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56; | |
124 | val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48; | |
125 | val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40; | |
126 | val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32; | |
127 | /* fall through */ | |
128 | case 4: | |
129 | val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24; | |
130 | val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16; | |
131 | /* fall through */ | |
132 | case 2: | |
133 | val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8; | |
134 | /* fall through */ | |
135 | case 1: | |
136 | val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7]; | |
137 | break; | |
138 | } | |
139 | ||
140 | return val; | |
141 | } | |
142 | ||
143 | static void boston_lcd_write(void *opaque, hwaddr addr, | |
144 | uint64_t val, unsigned size) | |
145 | { | |
146 | BostonState *s = opaque; | |
147 | ||
148 | switch (size) { | |
149 | case 8: | |
150 | s->lcd_content[(addr + 7) & 0x7] = val >> 56; | |
151 | s->lcd_content[(addr + 6) & 0x7] = val >> 48; | |
152 | s->lcd_content[(addr + 5) & 0x7] = val >> 40; | |
153 | s->lcd_content[(addr + 4) & 0x7] = val >> 32; | |
154 | /* fall through */ | |
155 | case 4: | |
156 | s->lcd_content[(addr + 3) & 0x7] = val >> 24; | |
157 | s->lcd_content[(addr + 2) & 0x7] = val >> 16; | |
158 | /* fall through */ | |
159 | case 2: | |
160 | s->lcd_content[(addr + 1) & 0x7] = val >> 8; | |
161 | /* fall through */ | |
162 | case 1: | |
163 | s->lcd_content[(addr + 0) & 0x7] = val; | |
164 | break; | |
165 | } | |
166 | ||
167 | qemu_chr_fe_printf(&s->lcd_display, | |
168 | "\r%-8.8s", s->lcd_content); | |
169 | } | |
170 | ||
171 | static const MemoryRegionOps boston_lcd_ops = { | |
172 | .read = boston_lcd_read, | |
173 | .write = boston_lcd_write, | |
174 | .endianness = DEVICE_NATIVE_ENDIAN, | |
175 | }; | |
176 | ||
177 | static uint64_t boston_platreg_read(void *opaque, hwaddr addr, | |
178 | unsigned size) | |
179 | { | |
180 | BostonState *s = opaque; | |
181 | uint32_t gic_freq, val; | |
182 | ||
183 | if (size != 4) { | |
c4c98835 | 184 | qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size); |
df1d8a1f PB |
185 | return 0; |
186 | } | |
187 | ||
188 | switch (addr & 0xffff) { | |
189 | case PLAT_FPGA_BUILD: | |
190 | case PLAT_CORE_CL: | |
191 | case PLAT_WRAPPER_CL: | |
192 | return 0; | |
193 | case PLAT_DDR3_STATUS: | |
194 | return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED; | |
195 | case PLAT_MMCM_DIV: | |
2d5fac80 | 196 | gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000; |
df1d8a1f PB |
197 | val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT; |
198 | val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT; | |
199 | val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT; | |
200 | val |= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT; | |
201 | return val; | |
202 | case PLAT_BUILD_CFG: | |
203 | val = PLAT_BUILD_CFG_PCIE0_EN; | |
204 | val |= PLAT_BUILD_CFG_PCIE1_EN; | |
205 | val |= PLAT_BUILD_CFG_PCIE2_EN; | |
206 | return val; | |
207 | case PLAT_DDR_CFG: | |
d23b6caa | 208 | val = s->mach->ram_size / GiB; |
df1d8a1f PB |
209 | assert(!(val & ~PLAT_DDR_CFG_SIZE)); |
210 | val |= PLAT_DDR_CFG_MHZ; | |
211 | return val; | |
212 | default: | |
c4c98835 | 213 | qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n", |
df1d8a1f PB |
214 | addr & 0xffff); |
215 | return 0; | |
216 | } | |
217 | } | |
218 | ||
219 | static void boston_platreg_write(void *opaque, hwaddr addr, | |
220 | uint64_t val, unsigned size) | |
221 | { | |
222 | if (size != 4) { | |
c4c98835 | 223 | qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size); |
df1d8a1f PB |
224 | return; |
225 | } | |
226 | ||
227 | switch (addr & 0xffff) { | |
228 | case PLAT_FPGA_BUILD: | |
229 | case PLAT_CORE_CL: | |
230 | case PLAT_WRAPPER_CL: | |
231 | case PLAT_DDR3_STATUS: | |
232 | case PLAT_PCIE_STATUS: | |
233 | case PLAT_MMCM_DIV: | |
234 | case PLAT_BUILD_CFG: | |
235 | case PLAT_DDR_CFG: | |
236 | /* read only */ | |
237 | break; | |
238 | case PLAT_SOFTRST_CTL: | |
239 | if (val & PLAT_SOFTRST_CTL_SYSRESET) { | |
cf83f140 | 240 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
df1d8a1f PB |
241 | } |
242 | break; | |
243 | default: | |
244 | qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx | |
c4c98835 | 245 | " = 0x%" PRIx64 "\n", addr & 0xffff, val); |
df1d8a1f PB |
246 | break; |
247 | } | |
248 | } | |
249 | ||
250 | static const MemoryRegionOps boston_platreg_ops = { | |
251 | .read = boston_platreg_read, | |
252 | .write = boston_platreg_write, | |
253 | .endianness = DEVICE_NATIVE_ENDIAN, | |
254 | }; | |
255 | ||
6b290b41 PMD |
256 | static void mips_boston_instance_init(Object *obj) |
257 | { | |
258 | BostonState *s = BOSTON(obj); | |
259 | ||
260 | s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); | |
261 | clock_set_hz(s->cpuclk, 1000000000); /* 1 GHz */ | |
262 | } | |
263 | ||
df1d8a1f | 264 | static const TypeInfo boston_device = { |
27cf0896 | 265 | .name = TYPE_BOSTON, |
df1d8a1f PB |
266 | .parent = TYPE_SYS_BUS_DEVICE, |
267 | .instance_size = sizeof(BostonState), | |
6b290b41 | 268 | .instance_init = mips_boston_instance_init, |
df1d8a1f PB |
269 | }; |
270 | ||
271 | static void boston_register_types(void) | |
272 | { | |
273 | type_register_static(&boston_device); | |
274 | } | |
275 | type_init(boston_register_types) | |
276 | ||
277 | static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr, | |
278 | bool is_64b) | |
279 | { | |
280 | const uint32_t cm_base = 0x16100000; | |
281 | const uint32_t gic_base = 0x16120000; | |
282 | const uint32_t cpc_base = 0x16200000; | |
283 | ||
284 | /* Move CM GCRs */ | |
285 | if (is_64b) { | |
286 | stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */ | |
287 | stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */ | |
288 | } else { | |
289 | stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */ | |
290 | stl_p(p++, 0x00084100); /* sll $8, $8, 4 */ | |
291 | } | |
292 | stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */ | |
293 | stl_p(p++, 0x01094025); /* or $8, $9 */ | |
294 | stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */ | |
295 | if (is_64b) { | |
296 | stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */ | |
297 | } else { | |
298 | stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */ | |
299 | } | |
300 | stl_p(p++, 0x012a4025); /* or $8, $10 */ | |
301 | ||
302 | /* Move & enable GIC GCRs */ | |
303 | stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */ | |
304 | stl_p(p++, 0x35290001); /* ori $9, 0x1 */ | |
305 | if (is_64b) { | |
306 | stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */ | |
307 | } else { | |
308 | stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */ | |
309 | } | |
310 | ||
311 | /* Move & enable CPC GCRs */ | |
312 | stl_p(p++, 0x3c090000 | (cpc_base >> 16)); /* lui $9, cpc_base >> 16 */ | |
313 | stl_p(p++, 0x35290001); /* ori $9, 0x1 */ | |
314 | if (is_64b) { | |
315 | stl_p(p++, 0xfd090088); /* sd $9, 0x88($8) */ | |
316 | } else { | |
317 | stl_p(p++, 0xad090088); /* sw $9, 0x88($8) */ | |
318 | } | |
319 | ||
320 | /* | |
321 | * Setup argument registers to follow the UHI boot protocol: | |
322 | * | |
323 | * a0/$4 = -2 | |
324 | * a1/$5 = virtual address of FDT | |
325 | * a2/$6 = 0 | |
326 | * a3/$7 = 0 | |
327 | */ | |
328 | stl_p(p++, 0x2404fffe); /* li $4, -2 */ | |
329 | /* lui $5, hi(fdt_addr) */ | |
330 | stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff)); | |
331 | if (fdt_addr & 0xffff) { /* ori $5, lo(fdt_addr) */ | |
332 | stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff)); | |
333 | } | |
334 | stl_p(p++, 0x34060000); /* li $6, 0 */ | |
335 | stl_p(p++, 0x34070000); /* li $7, 0 */ | |
336 | ||
337 | /* Load kernel entry address & jump to it */ | |
338 | /* lui $25, hi(kernel_entry) */ | |
339 | stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff)); | |
340 | /* ori $25, lo(kernel_entry) */ | |
341 | stl_p(p++, 0x37390000 | (kernel_entry & 0xffff)); | |
342 | stl_p(p++, 0x03200009); /* jr $25 */ | |
343 | } | |
344 | ||
345 | static const void *boston_fdt_filter(void *opaque, const void *fdt_orig, | |
346 | const void *match_data, hwaddr *load_addr) | |
347 | { | |
348 | BostonState *s = BOSTON(opaque); | |
349 | MachineState *machine = s->mach; | |
350 | const char *cmdline; | |
351 | int err; | |
352 | void *fdt; | |
353 | size_t fdt_sz, ram_low_sz, ram_high_sz; | |
354 | ||
355 | fdt_sz = fdt_totalsize(fdt_orig) * 2; | |
356 | fdt = g_malloc0(fdt_sz); | |
357 | ||
358 | err = fdt_open_into(fdt_orig, fdt, fdt_sz); | |
359 | if (err) { | |
360 | fprintf(stderr, "unable to open FDT\n"); | |
361 | return NULL; | |
362 | } | |
363 | ||
364 | cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0]) | |
365 | ? machine->kernel_cmdline : " "; | |
366 | err = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | |
367 | if (err < 0) { | |
368 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
369 | return NULL; | |
370 | } | |
371 | ||
d23b6caa | 372 | ram_low_sz = MIN(256 * MiB, machine->ram_size); |
df1d8a1f PB |
373 | ram_high_sz = machine->ram_size - ram_low_sz; |
374 | qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg", | |
375 | 1, 0x00000000, 1, ram_low_sz, | |
376 | 1, 0x90000000, 1, ram_high_sz); | |
377 | ||
378 | fdt = g_realloc(fdt, fdt_totalsize(fdt)); | |
379 | qemu_fdt_dumpdtb(fdt, fdt_sz); | |
380 | ||
381 | s->fdt_base = *load_addr; | |
382 | ||
383 | return fdt; | |
384 | } | |
385 | ||
386 | static const void *boston_kernel_filter(void *opaque, const void *kernel, | |
387 | hwaddr *load_addr, hwaddr *entry_addr) | |
388 | { | |
389 | BostonState *s = BOSTON(opaque); | |
390 | ||
391 | s->kernel_entry = *entry_addr; | |
392 | ||
393 | return kernel; | |
394 | } | |
395 | ||
396 | static const struct fit_loader_match boston_matches[] = { | |
397 | { "img,boston" }, | |
398 | { NULL }, | |
399 | }; | |
400 | ||
401 | static const struct fit_loader boston_fit_loader = { | |
402 | .matches = boston_matches, | |
403 | .addr_to_phys = cpu_mips_kseg0_to_phys, | |
404 | .fdt_filter = boston_fdt_filter, | |
405 | .kernel_filter = boston_kernel_filter, | |
406 | }; | |
407 | ||
408 | static inline XilinxPCIEHost * | |
409 | xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, | |
410 | hwaddr cfg_base, uint64_t cfg_size, | |
411 | hwaddr mmio_base, uint64_t mmio_size, | |
412 | qemu_irq irq, bool link_up) | |
413 | { | |
414 | DeviceState *dev; | |
415 | MemoryRegion *cfg, *mmio; | |
416 | ||
3e80f690 | 417 | dev = qdev_new(TYPE_XILINX_PCIE_HOST); |
df1d8a1f PB |
418 | |
419 | qdev_prop_set_uint32(dev, "bus_nr", bus_nr); | |
420 | qdev_prop_set_uint64(dev, "cfg_base", cfg_base); | |
421 | qdev_prop_set_uint64(dev, "cfg_size", cfg_size); | |
422 | qdev_prop_set_uint64(dev, "mmio_base", mmio_base); | |
423 | qdev_prop_set_uint64(dev, "mmio_size", mmio_size); | |
424 | qdev_prop_set_bit(dev, "link_up", link_up); | |
425 | ||
3c6ef471 | 426 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
df1d8a1f PB |
427 | |
428 | cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
429 | memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); | |
430 | ||
431 | mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
432 | memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0); | |
433 | ||
434 | qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq); | |
435 | ||
436 | return XILINX_PCIE_HOST(dev); | |
437 | } | |
438 | ||
439 | static void boston_mach_init(MachineState *machine) | |
440 | { | |
441 | DeviceState *dev; | |
442 | BostonState *s; | |
9389d6ce | 443 | MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg; |
df1d8a1f PB |
444 | MemoryRegion *sys_mem = get_system_memory(); |
445 | XilinxPCIEHost *pcie2; | |
446 | PCIDevice *ahci; | |
447 | DriveInfo *hd[6]; | |
448 | Chardev *chr; | |
449 | int fw_size, fit_err; | |
450 | bool is_64b; | |
451 | ||
d23b6caa PMD |
452 | if ((machine->ram_size % GiB) || |
453 | (machine->ram_size > (2 * GiB))) { | |
df1d8a1f PB |
454 | error_report("Memory size must be 1GB or 2GB"); |
455 | exit(1); | |
456 | } | |
457 | ||
27cf0896 | 458 | dev = qdev_new(TYPE_BOSTON); |
3c6ef471 | 459 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
df1d8a1f PB |
460 | |
461 | s = BOSTON(dev); | |
462 | s->mach = machine; | |
df1d8a1f | 463 | |
a7519f2b | 464 | if (!cpu_supports_cps_smp(machine->cpu_type)) { |
df1d8a1f PB |
465 | error_report("Boston requires CPUs which support CPS"); |
466 | exit(1); | |
467 | } | |
468 | ||
a7519f2b | 469 | is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64); |
df1d8a1f | 470 | |
0074fce6 | 471 | object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); |
5325cc34 | 472 | object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, |
932d3a65 | 473 | &error_fatal); |
5325cc34 | 474 | object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus, |
932d3a65 | 475 | &error_fatal); |
6b290b41 PMD |
476 | qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", |
477 | qdev_get_clock_out(dev, "cpu-refclk")); | |
0074fce6 | 478 | sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); |
df1d8a1f | 479 | |
2d5fac80 | 480 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); |
df1d8a1f PB |
481 | |
482 | flash = g_new(MemoryRegion, 1); | |
3e1df4cc MA |
483 | memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, |
484 | &error_fatal); | |
df1d8a1f PB |
485 | memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); |
486 | ||
9389d6ce | 487 | memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0); |
df1d8a1f PB |
488 | |
489 | ddr_low_alias = g_new(MemoryRegion, 1); | |
490 | memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", | |
9389d6ce IM |
491 | machine->ram, 0, |
492 | MIN(machine->ram_size, (256 * MiB))); | |
df1d8a1f PB |
493 | memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); |
494 | ||
495 | xilinx_pcie_init(sys_mem, 0, | |
d23b6caa PMD |
496 | 0x10000000, 32 * MiB, |
497 | 0x40000000, 1 * GiB, | |
2d5fac80 | 498 | get_cps_irq(&s->cps, 2), false); |
df1d8a1f PB |
499 | |
500 | xilinx_pcie_init(sys_mem, 1, | |
d23b6caa PMD |
501 | 0x12000000, 32 * MiB, |
502 | 0x20000000, 512 * MiB, | |
2d5fac80 | 503 | get_cps_irq(&s->cps, 1), false); |
df1d8a1f PB |
504 | |
505 | pcie2 = xilinx_pcie_init(sys_mem, 2, | |
d23b6caa PMD |
506 | 0x14000000, 32 * MiB, |
507 | 0x16000000, 1 * MiB, | |
2d5fac80 | 508 | get_cps_irq(&s->cps, 0), true); |
df1d8a1f PB |
509 | |
510 | platreg = g_new(MemoryRegion, 1); | |
511 | memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, | |
512 | "boston-platregs", 0x1000); | |
513 | memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); | |
514 | ||
df1d8a1f | 515 | s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2, |
2d5fac80 | 516 | get_cps_irq(&s->cps, 3), 10000000, |
9bca0edb | 517 | serial_hd(0), DEVICE_NATIVE_ENDIAN); |
df1d8a1f PB |
518 | |
519 | lcd = g_new(MemoryRegion, 1); | |
520 | memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); | |
521 | memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0); | |
522 | ||
4ad6f6cb | 523 | chr = qemu_chr_new("lcd", "vc:320x240", NULL); |
df1d8a1f PB |
524 | qemu_chr_fe_init(&s->lcd_display, chr, NULL); |
525 | qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, | |
81517ba3 | 526 | boston_lcd_event, NULL, s, NULL, true); |
df1d8a1f PB |
527 | |
528 | ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, | |
529 | PCI_DEVFN(0, 0), | |
530 | true, TYPE_ICH9_AHCI); | |
bbe3179a JS |
531 | g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci)); |
532 | ide_drive_get(hd, ahci_get_num_ports(ahci)); | |
df1d8a1f PB |
533 | ahci_ide_create_devs(ahci, hd); |
534 | ||
535 | if (machine->firmware) { | |
536 | fw_size = load_image_targphys(machine->firmware, | |
d23b6caa | 537 | 0x1fc00000, 4 * MiB); |
df1d8a1f | 538 | if (fw_size == -1) { |
036a2604 | 539 | error_report("unable to load firmware image '%s'", |
df1d8a1f PB |
540 | machine->firmware); |
541 | exit(1); | |
542 | } | |
543 | } else if (machine->kernel_filename) { | |
544 | fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s); | |
545 | if (fit_err) { | |
036a2604 | 546 | error_report("unable to load FIT image"); |
df1d8a1f PB |
547 | exit(1); |
548 | } | |
549 | ||
550 | gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, | |
551 | s->kernel_entry, s->fdt_base, is_64b); | |
552 | } else if (!qtest_enabled()) { | |
036a2604 | 553 | error_report("Please provide either a -kernel or -bios argument"); |
df1d8a1f PB |
554 | exit(1); |
555 | } | |
556 | } | |
557 | ||
558 | static void boston_mach_class_init(MachineClass *mc) | |
559 | { | |
560 | mc->desc = "MIPS Boston"; | |
561 | mc->init = boston_mach_init; | |
562 | mc->block_default_type = IF_IDE; | |
d23b6caa | 563 | mc->default_ram_size = 1 * GiB; |
9389d6ce | 564 | mc->default_ram_id = "boston.ddr"; |
df1d8a1f | 565 | mc->max_cpus = 16; |
a7519f2b | 566 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400"); |
df1d8a1f PB |
567 | } |
568 | ||
569 | DEFINE_MACHINE("boston", boston_mach_class_init) |