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df1d8a1f PB |
1 | /* |
2 | * MIPS Boston development board emulation. | |
3 | * | |
4 | * Copyright (c) 2016 Imagination Technologies | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
fc6b3cf9 | 21 | #include "qemu/units.h" |
df1d8a1f PB |
22 | |
23 | #include "exec/address-spaces.h" | |
24 | #include "hw/boards.h" | |
25 | #include "hw/char/serial.h" | |
df1d8a1f PB |
26 | #include "hw/ide/pci.h" |
27 | #include "hw/ide/ahci.h" | |
28 | #include "hw/loader.h" | |
29 | #include "hw/loader-fit.h" | |
30 | #include "hw/mips/cps.h" | |
31 | #include "hw/mips/cpudevs.h" | |
32 | #include "hw/pci-host/xilinx-pcie.h" | |
33 | #include "qapi/error.h" | |
df1d8a1f PB |
34 | #include "qemu/error-report.h" |
35 | #include "qemu/log.h" | |
8228e353 | 36 | #include "chardev/char.h" |
df1d8a1f PB |
37 | #include "sysemu/device_tree.h" |
38 | #include "sysemu/sysemu.h" | |
39 | #include "sysemu/qtest.h" | |
40 | ||
41 | #include <libfdt.h> | |
42 | ||
43 | #define TYPE_MIPS_BOSTON "mips-boston" | |
44 | #define BOSTON(obj) OBJECT_CHECK(BostonState, (obj), TYPE_MIPS_BOSTON) | |
45 | ||
46 | typedef struct { | |
47 | SysBusDevice parent_obj; | |
48 | ||
49 | MachineState *mach; | |
2d5fac80 | 50 | MIPSCPSState cps; |
df1d8a1f PB |
51 | SerialState *uart; |
52 | ||
53 | CharBackend lcd_display; | |
54 | char lcd_content[8]; | |
55 | bool lcd_inited; | |
56 | ||
57 | hwaddr kernel_entry; | |
58 | hwaddr fdt_base; | |
59 | } BostonState; | |
60 | ||
61 | enum boston_plat_reg { | |
62 | PLAT_FPGA_BUILD = 0x00, | |
63 | PLAT_CORE_CL = 0x04, | |
64 | PLAT_WRAPPER_CL = 0x08, | |
65 | PLAT_SYSCLK_STATUS = 0x0c, | |
66 | PLAT_SOFTRST_CTL = 0x10, | |
67 | #define PLAT_SOFTRST_CTL_SYSRESET (1 << 4) | |
68 | PLAT_DDR3_STATUS = 0x14, | |
69 | #define PLAT_DDR3_STATUS_LOCKED (1 << 0) | |
70 | #define PLAT_DDR3_STATUS_CALIBRATED (1 << 2) | |
71 | PLAT_PCIE_STATUS = 0x18, | |
72 | #define PLAT_PCIE_STATUS_PCIE0_LOCKED (1 << 0) | |
73 | #define PLAT_PCIE_STATUS_PCIE1_LOCKED (1 << 8) | |
74 | #define PLAT_PCIE_STATUS_PCIE2_LOCKED (1 << 16) | |
75 | PLAT_FLASH_CTL = 0x1c, | |
76 | PLAT_SPARE0 = 0x20, | |
77 | PLAT_SPARE1 = 0x24, | |
78 | PLAT_SPARE2 = 0x28, | |
79 | PLAT_SPARE3 = 0x2c, | |
80 | PLAT_MMCM_DIV = 0x30, | |
81 | #define PLAT_MMCM_DIV_CLK0DIV_SHIFT 0 | |
82 | #define PLAT_MMCM_DIV_INPUT_SHIFT 8 | |
83 | #define PLAT_MMCM_DIV_MUL_SHIFT 16 | |
84 | #define PLAT_MMCM_DIV_CLK1DIV_SHIFT 24 | |
85 | PLAT_BUILD_CFG = 0x34, | |
86 | #define PLAT_BUILD_CFG_IOCU_EN (1 << 0) | |
87 | #define PLAT_BUILD_CFG_PCIE0_EN (1 << 1) | |
88 | #define PLAT_BUILD_CFG_PCIE1_EN (1 << 2) | |
89 | #define PLAT_BUILD_CFG_PCIE2_EN (1 << 3) | |
90 | PLAT_DDR_CFG = 0x38, | |
91 | #define PLAT_DDR_CFG_SIZE (0xf << 0) | |
92 | #define PLAT_DDR_CFG_MHZ (0xfff << 4) | |
93 | PLAT_NOC_PCIE0_ADDR = 0x3c, | |
94 | PLAT_NOC_PCIE1_ADDR = 0x40, | |
95 | PLAT_NOC_PCIE2_ADDR = 0x44, | |
96 | PLAT_SYS_CTL = 0x48, | |
97 | }; | |
98 | ||
99 | static void boston_lcd_event(void *opaque, int event) | |
100 | { | |
101 | BostonState *s = opaque; | |
102 | if (event == CHR_EVENT_OPENED && !s->lcd_inited) { | |
103 | qemu_chr_fe_printf(&s->lcd_display, " "); | |
104 | s->lcd_inited = true; | |
105 | } | |
106 | } | |
107 | ||
108 | static uint64_t boston_lcd_read(void *opaque, hwaddr addr, | |
109 | unsigned size) | |
110 | { | |
111 | BostonState *s = opaque; | |
112 | uint64_t val = 0; | |
113 | ||
114 | switch (size) { | |
115 | case 8: | |
116 | val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56; | |
117 | val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48; | |
118 | val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40; | |
119 | val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32; | |
120 | /* fall through */ | |
121 | case 4: | |
122 | val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24; | |
123 | val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16; | |
124 | /* fall through */ | |
125 | case 2: | |
126 | val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8; | |
127 | /* fall through */ | |
128 | case 1: | |
129 | val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7]; | |
130 | break; | |
131 | } | |
132 | ||
133 | return val; | |
134 | } | |
135 | ||
136 | static void boston_lcd_write(void *opaque, hwaddr addr, | |
137 | uint64_t val, unsigned size) | |
138 | { | |
139 | BostonState *s = opaque; | |
140 | ||
141 | switch (size) { | |
142 | case 8: | |
143 | s->lcd_content[(addr + 7) & 0x7] = val >> 56; | |
144 | s->lcd_content[(addr + 6) & 0x7] = val >> 48; | |
145 | s->lcd_content[(addr + 5) & 0x7] = val >> 40; | |
146 | s->lcd_content[(addr + 4) & 0x7] = val >> 32; | |
147 | /* fall through */ | |
148 | case 4: | |
149 | s->lcd_content[(addr + 3) & 0x7] = val >> 24; | |
150 | s->lcd_content[(addr + 2) & 0x7] = val >> 16; | |
151 | /* fall through */ | |
152 | case 2: | |
153 | s->lcd_content[(addr + 1) & 0x7] = val >> 8; | |
154 | /* fall through */ | |
155 | case 1: | |
156 | s->lcd_content[(addr + 0) & 0x7] = val; | |
157 | break; | |
158 | } | |
159 | ||
160 | qemu_chr_fe_printf(&s->lcd_display, | |
161 | "\r%-8.8s", s->lcd_content); | |
162 | } | |
163 | ||
164 | static const MemoryRegionOps boston_lcd_ops = { | |
165 | .read = boston_lcd_read, | |
166 | .write = boston_lcd_write, | |
167 | .endianness = DEVICE_NATIVE_ENDIAN, | |
168 | }; | |
169 | ||
170 | static uint64_t boston_platreg_read(void *opaque, hwaddr addr, | |
171 | unsigned size) | |
172 | { | |
173 | BostonState *s = opaque; | |
174 | uint32_t gic_freq, val; | |
175 | ||
176 | if (size != 4) { | |
c4c98835 | 177 | qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size); |
df1d8a1f PB |
178 | return 0; |
179 | } | |
180 | ||
181 | switch (addr & 0xffff) { | |
182 | case PLAT_FPGA_BUILD: | |
183 | case PLAT_CORE_CL: | |
184 | case PLAT_WRAPPER_CL: | |
185 | return 0; | |
186 | case PLAT_DDR3_STATUS: | |
187 | return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED; | |
188 | case PLAT_MMCM_DIV: | |
2d5fac80 | 189 | gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000; |
df1d8a1f PB |
190 | val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT; |
191 | val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT; | |
192 | val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT; | |
193 | val |= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT; | |
194 | return val; | |
195 | case PLAT_BUILD_CFG: | |
196 | val = PLAT_BUILD_CFG_PCIE0_EN; | |
197 | val |= PLAT_BUILD_CFG_PCIE1_EN; | |
198 | val |= PLAT_BUILD_CFG_PCIE2_EN; | |
199 | return val; | |
200 | case PLAT_DDR_CFG: | |
d23b6caa | 201 | val = s->mach->ram_size / GiB; |
df1d8a1f PB |
202 | assert(!(val & ~PLAT_DDR_CFG_SIZE)); |
203 | val |= PLAT_DDR_CFG_MHZ; | |
204 | return val; | |
205 | default: | |
c4c98835 | 206 | qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n", |
df1d8a1f PB |
207 | addr & 0xffff); |
208 | return 0; | |
209 | } | |
210 | } | |
211 | ||
212 | static void boston_platreg_write(void *opaque, hwaddr addr, | |
213 | uint64_t val, unsigned size) | |
214 | { | |
215 | if (size != 4) { | |
c4c98835 | 216 | qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size); |
df1d8a1f PB |
217 | return; |
218 | } | |
219 | ||
220 | switch (addr & 0xffff) { | |
221 | case PLAT_FPGA_BUILD: | |
222 | case PLAT_CORE_CL: | |
223 | case PLAT_WRAPPER_CL: | |
224 | case PLAT_DDR3_STATUS: | |
225 | case PLAT_PCIE_STATUS: | |
226 | case PLAT_MMCM_DIV: | |
227 | case PLAT_BUILD_CFG: | |
228 | case PLAT_DDR_CFG: | |
229 | /* read only */ | |
230 | break; | |
231 | case PLAT_SOFTRST_CTL: | |
232 | if (val & PLAT_SOFTRST_CTL_SYSRESET) { | |
cf83f140 | 233 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
df1d8a1f PB |
234 | } |
235 | break; | |
236 | default: | |
237 | qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx | |
c4c98835 | 238 | " = 0x%" PRIx64 "\n", addr & 0xffff, val); |
df1d8a1f PB |
239 | break; |
240 | } | |
241 | } | |
242 | ||
243 | static const MemoryRegionOps boston_platreg_ops = { | |
244 | .read = boston_platreg_read, | |
245 | .write = boston_platreg_write, | |
246 | .endianness = DEVICE_NATIVE_ENDIAN, | |
247 | }; | |
248 | ||
df1d8a1f PB |
249 | static const TypeInfo boston_device = { |
250 | .name = TYPE_MIPS_BOSTON, | |
251 | .parent = TYPE_SYS_BUS_DEVICE, | |
252 | .instance_size = sizeof(BostonState), | |
253 | }; | |
254 | ||
255 | static void boston_register_types(void) | |
256 | { | |
257 | type_register_static(&boston_device); | |
258 | } | |
259 | type_init(boston_register_types) | |
260 | ||
261 | static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr, | |
262 | bool is_64b) | |
263 | { | |
264 | const uint32_t cm_base = 0x16100000; | |
265 | const uint32_t gic_base = 0x16120000; | |
266 | const uint32_t cpc_base = 0x16200000; | |
267 | ||
268 | /* Move CM GCRs */ | |
269 | if (is_64b) { | |
270 | stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */ | |
271 | stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */ | |
272 | } else { | |
273 | stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */ | |
274 | stl_p(p++, 0x00084100); /* sll $8, $8, 4 */ | |
275 | } | |
276 | stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */ | |
277 | stl_p(p++, 0x01094025); /* or $8, $9 */ | |
278 | stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */ | |
279 | if (is_64b) { | |
280 | stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */ | |
281 | } else { | |
282 | stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */ | |
283 | } | |
284 | stl_p(p++, 0x012a4025); /* or $8, $10 */ | |
285 | ||
286 | /* Move & enable GIC GCRs */ | |
287 | stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */ | |
288 | stl_p(p++, 0x35290001); /* ori $9, 0x1 */ | |
289 | if (is_64b) { | |
290 | stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */ | |
291 | } else { | |
292 | stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */ | |
293 | } | |
294 | ||
295 | /* Move & enable CPC GCRs */ | |
296 | stl_p(p++, 0x3c090000 | (cpc_base >> 16)); /* lui $9, cpc_base >> 16 */ | |
297 | stl_p(p++, 0x35290001); /* ori $9, 0x1 */ | |
298 | if (is_64b) { | |
299 | stl_p(p++, 0xfd090088); /* sd $9, 0x88($8) */ | |
300 | } else { | |
301 | stl_p(p++, 0xad090088); /* sw $9, 0x88($8) */ | |
302 | } | |
303 | ||
304 | /* | |
305 | * Setup argument registers to follow the UHI boot protocol: | |
306 | * | |
307 | * a0/$4 = -2 | |
308 | * a1/$5 = virtual address of FDT | |
309 | * a2/$6 = 0 | |
310 | * a3/$7 = 0 | |
311 | */ | |
312 | stl_p(p++, 0x2404fffe); /* li $4, -2 */ | |
313 | /* lui $5, hi(fdt_addr) */ | |
314 | stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff)); | |
315 | if (fdt_addr & 0xffff) { /* ori $5, lo(fdt_addr) */ | |
316 | stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff)); | |
317 | } | |
318 | stl_p(p++, 0x34060000); /* li $6, 0 */ | |
319 | stl_p(p++, 0x34070000); /* li $7, 0 */ | |
320 | ||
321 | /* Load kernel entry address & jump to it */ | |
322 | /* lui $25, hi(kernel_entry) */ | |
323 | stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff)); | |
324 | /* ori $25, lo(kernel_entry) */ | |
325 | stl_p(p++, 0x37390000 | (kernel_entry & 0xffff)); | |
326 | stl_p(p++, 0x03200009); /* jr $25 */ | |
327 | } | |
328 | ||
329 | static const void *boston_fdt_filter(void *opaque, const void *fdt_orig, | |
330 | const void *match_data, hwaddr *load_addr) | |
331 | { | |
332 | BostonState *s = BOSTON(opaque); | |
333 | MachineState *machine = s->mach; | |
334 | const char *cmdline; | |
335 | int err; | |
336 | void *fdt; | |
337 | size_t fdt_sz, ram_low_sz, ram_high_sz; | |
338 | ||
339 | fdt_sz = fdt_totalsize(fdt_orig) * 2; | |
340 | fdt = g_malloc0(fdt_sz); | |
341 | ||
342 | err = fdt_open_into(fdt_orig, fdt, fdt_sz); | |
343 | if (err) { | |
344 | fprintf(stderr, "unable to open FDT\n"); | |
345 | return NULL; | |
346 | } | |
347 | ||
348 | cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0]) | |
349 | ? machine->kernel_cmdline : " "; | |
350 | err = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | |
351 | if (err < 0) { | |
352 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
353 | return NULL; | |
354 | } | |
355 | ||
d23b6caa | 356 | ram_low_sz = MIN(256 * MiB, machine->ram_size); |
df1d8a1f PB |
357 | ram_high_sz = machine->ram_size - ram_low_sz; |
358 | qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg", | |
359 | 1, 0x00000000, 1, ram_low_sz, | |
360 | 1, 0x90000000, 1, ram_high_sz); | |
361 | ||
362 | fdt = g_realloc(fdt, fdt_totalsize(fdt)); | |
363 | qemu_fdt_dumpdtb(fdt, fdt_sz); | |
364 | ||
365 | s->fdt_base = *load_addr; | |
366 | ||
367 | return fdt; | |
368 | } | |
369 | ||
370 | static const void *boston_kernel_filter(void *opaque, const void *kernel, | |
371 | hwaddr *load_addr, hwaddr *entry_addr) | |
372 | { | |
373 | BostonState *s = BOSTON(opaque); | |
374 | ||
375 | s->kernel_entry = *entry_addr; | |
376 | ||
377 | return kernel; | |
378 | } | |
379 | ||
380 | static const struct fit_loader_match boston_matches[] = { | |
381 | { "img,boston" }, | |
382 | { NULL }, | |
383 | }; | |
384 | ||
385 | static const struct fit_loader boston_fit_loader = { | |
386 | .matches = boston_matches, | |
387 | .addr_to_phys = cpu_mips_kseg0_to_phys, | |
388 | .fdt_filter = boston_fdt_filter, | |
389 | .kernel_filter = boston_kernel_filter, | |
390 | }; | |
391 | ||
392 | static inline XilinxPCIEHost * | |
393 | xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, | |
394 | hwaddr cfg_base, uint64_t cfg_size, | |
395 | hwaddr mmio_base, uint64_t mmio_size, | |
396 | qemu_irq irq, bool link_up) | |
397 | { | |
398 | DeviceState *dev; | |
399 | MemoryRegion *cfg, *mmio; | |
400 | ||
401 | dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST); | |
402 | ||
403 | qdev_prop_set_uint32(dev, "bus_nr", bus_nr); | |
404 | qdev_prop_set_uint64(dev, "cfg_base", cfg_base); | |
405 | qdev_prop_set_uint64(dev, "cfg_size", cfg_size); | |
406 | qdev_prop_set_uint64(dev, "mmio_base", mmio_base); | |
407 | qdev_prop_set_uint64(dev, "mmio_size", mmio_size); | |
408 | qdev_prop_set_bit(dev, "link_up", link_up); | |
409 | ||
410 | qdev_init_nofail(dev); | |
411 | ||
412 | cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
413 | memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); | |
414 | ||
415 | mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
416 | memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0); | |
417 | ||
418 | qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq); | |
419 | ||
420 | return XILINX_PCIE_HOST(dev); | |
421 | } | |
422 | ||
423 | static void boston_mach_init(MachineState *machine) | |
424 | { | |
425 | DeviceState *dev; | |
426 | BostonState *s; | |
427 | Error *err = NULL; | |
df1d8a1f PB |
428 | MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg; |
429 | MemoryRegion *sys_mem = get_system_memory(); | |
430 | XilinxPCIEHost *pcie2; | |
431 | PCIDevice *ahci; | |
432 | DriveInfo *hd[6]; | |
433 | Chardev *chr; | |
434 | int fw_size, fit_err; | |
435 | bool is_64b; | |
436 | ||
d23b6caa PMD |
437 | if ((machine->ram_size % GiB) || |
438 | (machine->ram_size > (2 * GiB))) { | |
df1d8a1f PB |
439 | error_report("Memory size must be 1GB or 2GB"); |
440 | exit(1); | |
441 | } | |
442 | ||
df1d8a1f PB |
443 | dev = qdev_create(NULL, TYPE_MIPS_BOSTON); |
444 | qdev_init_nofail(dev); | |
445 | ||
446 | s = BOSTON(dev); | |
447 | s->mach = machine; | |
df1d8a1f | 448 | |
a7519f2b | 449 | if (!cpu_supports_cps_smp(machine->cpu_type)) { |
df1d8a1f PB |
450 | error_report("Boston requires CPUs which support CPS"); |
451 | exit(1); | |
452 | } | |
453 | ||
a7519f2b | 454 | is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64); |
df1d8a1f | 455 | |
4626548b PMD |
456 | sysbus_init_child_obj(OBJECT(machine), "cps", OBJECT(&s->cps), |
457 | sizeof(s->cps), TYPE_MIPS_CPS); | |
2d5fac80 | 458 | object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type", |
a7519f2b | 459 | &err); |
33decbd2 | 460 | object_property_set_int(OBJECT(&s->cps), machine->smp.cpus, "num-vp", &err); |
2d5fac80 | 461 | object_property_set_bool(OBJECT(&s->cps), true, "realized", &err); |
df1d8a1f PB |
462 | |
463 | if (err != NULL) { | |
464 | error_report("%s", error_get_pretty(err)); | |
465 | exit(1); | |
466 | } | |
467 | ||
2d5fac80 | 468 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); |
df1d8a1f PB |
469 | |
470 | flash = g_new(MemoryRegion, 1); | |
d23b6caa | 471 | memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err); |
df1d8a1f PB |
472 | memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); |
473 | ||
474 | ddr = g_new(MemoryRegion, 1); | |
475 | memory_region_allocate_system_memory(ddr, NULL, "boston.ddr", | |
476 | machine->ram_size); | |
477 | memory_region_add_subregion_overlap(sys_mem, 0x80000000, ddr, 0); | |
478 | ||
479 | ddr_low_alias = g_new(MemoryRegion, 1); | |
480 | memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", | |
d23b6caa | 481 | ddr, 0, MIN(machine->ram_size, (256 * MiB))); |
df1d8a1f PB |
482 | memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); |
483 | ||
484 | xilinx_pcie_init(sys_mem, 0, | |
d23b6caa PMD |
485 | 0x10000000, 32 * MiB, |
486 | 0x40000000, 1 * GiB, | |
2d5fac80 | 487 | get_cps_irq(&s->cps, 2), false); |
df1d8a1f PB |
488 | |
489 | xilinx_pcie_init(sys_mem, 1, | |
d23b6caa PMD |
490 | 0x12000000, 32 * MiB, |
491 | 0x20000000, 512 * MiB, | |
2d5fac80 | 492 | get_cps_irq(&s->cps, 1), false); |
df1d8a1f PB |
493 | |
494 | pcie2 = xilinx_pcie_init(sys_mem, 2, | |
d23b6caa PMD |
495 | 0x14000000, 32 * MiB, |
496 | 0x16000000, 1 * MiB, | |
2d5fac80 | 497 | get_cps_irq(&s->cps, 0), true); |
df1d8a1f PB |
498 | |
499 | platreg = g_new(MemoryRegion, 1); | |
500 | memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, | |
501 | "boston-platregs", 0x1000); | |
502 | memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); | |
503 | ||
df1d8a1f | 504 | s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2, |
2d5fac80 | 505 | get_cps_irq(&s->cps, 3), 10000000, |
9bca0edb | 506 | serial_hd(0), DEVICE_NATIVE_ENDIAN); |
df1d8a1f PB |
507 | |
508 | lcd = g_new(MemoryRegion, 1); | |
509 | memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); | |
510 | memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0); | |
511 | ||
4ad6f6cb | 512 | chr = qemu_chr_new("lcd", "vc:320x240", NULL); |
df1d8a1f PB |
513 | qemu_chr_fe_init(&s->lcd_display, chr, NULL); |
514 | qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, | |
81517ba3 | 515 | boston_lcd_event, NULL, s, NULL, true); |
df1d8a1f PB |
516 | |
517 | ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, | |
518 | PCI_DEVFN(0, 0), | |
519 | true, TYPE_ICH9_AHCI); | |
bbe3179a JS |
520 | g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci)); |
521 | ide_drive_get(hd, ahci_get_num_ports(ahci)); | |
df1d8a1f PB |
522 | ahci_ide_create_devs(ahci, hd); |
523 | ||
524 | if (machine->firmware) { | |
525 | fw_size = load_image_targphys(machine->firmware, | |
d23b6caa | 526 | 0x1fc00000, 4 * MiB); |
df1d8a1f | 527 | if (fw_size == -1) { |
036a2604 | 528 | error_report("unable to load firmware image '%s'", |
df1d8a1f PB |
529 | machine->firmware); |
530 | exit(1); | |
531 | } | |
532 | } else if (machine->kernel_filename) { | |
533 | fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s); | |
534 | if (fit_err) { | |
036a2604 | 535 | error_report("unable to load FIT image"); |
df1d8a1f PB |
536 | exit(1); |
537 | } | |
538 | ||
539 | gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, | |
540 | s->kernel_entry, s->fdt_base, is_64b); | |
541 | } else if (!qtest_enabled()) { | |
036a2604 | 542 | error_report("Please provide either a -kernel or -bios argument"); |
df1d8a1f PB |
543 | exit(1); |
544 | } | |
545 | } | |
546 | ||
547 | static void boston_mach_class_init(MachineClass *mc) | |
548 | { | |
549 | mc->desc = "MIPS Boston"; | |
550 | mc->init = boston_mach_init; | |
551 | mc->block_default_type = IF_IDE; | |
d23b6caa | 552 | mc->default_ram_size = 1 * GiB; |
df1d8a1f | 553 | mc->max_cpus = 16; |
a7519f2b | 554 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400"); |
df1d8a1f PB |
555 | } |
556 | ||
557 | DEFINE_MACHINE("boston", boston_mach_class_init) |