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Commit | Line | Data |
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fde7d5bd TS |
1 | /* |
2 | * QEMU GT64120 PCI host | |
3 | * | |
4de9b249 | 4 | * Copyright (c) 2006,2007 Aurelien Jarno |
5fafdf24 | 5 | * |
fde7d5bd TS |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
c684822a | 25 | #include "qemu/osdep.h" |
8110b2bf | 26 | #include "qemu/units.h" |
641ca2bf | 27 | #include "qemu/log.h" |
83c9f4ca | 28 | #include "hw/hw.h" |
0d09e41a | 29 | #include "hw/mips/mips.h" |
83c9f4ca PB |
30 | #include "hw/pci/pci.h" |
31 | #include "hw/pci/pci_host.h" | |
d6454270 | 32 | #include "migration/vmstate.h" |
0d09e41a | 33 | #include "hw/i386/pc.h" |
64552b6b | 34 | #include "hw/irq.h" |
022c62cb | 35 | #include "exec/address-spaces.h" |
ab6bff42 | 36 | #include "trace.h" |
05b4ff43 | 37 | |
91ce82b2 | 38 | #define GT_REGS (0x1000 >> 2) |
fde7d5bd TS |
39 | |
40 | /* CPU Configuration */ | |
91ce82b2 PMD |
41 | #define GT_CPU (0x000 >> 2) |
42 | #define GT_MULTI (0x120 >> 2) | |
fde7d5bd TS |
43 | |
44 | /* CPU Address Decode */ | |
91ce82b2 PMD |
45 | #define GT_SCS10LD (0x008 >> 2) |
46 | #define GT_SCS10HD (0x010 >> 2) | |
47 | #define GT_SCS32LD (0x018 >> 2) | |
48 | #define GT_SCS32HD (0x020 >> 2) | |
49 | #define GT_CS20LD (0x028 >> 2) | |
50 | #define GT_CS20HD (0x030 >> 2) | |
51 | #define GT_CS3BOOTLD (0x038 >> 2) | |
52 | #define GT_CS3BOOTHD (0x040 >> 2) | |
53 | #define GT_PCI0IOLD (0x048 >> 2) | |
54 | #define GT_PCI0IOHD (0x050 >> 2) | |
55 | #define GT_PCI0M0LD (0x058 >> 2) | |
56 | #define GT_PCI0M0HD (0x060 >> 2) | |
57 | #define GT_PCI0M1LD (0x080 >> 2) | |
58 | #define GT_PCI0M1HD (0x088 >> 2) | |
59 | #define GT_PCI1IOLD (0x090 >> 2) | |
60 | #define GT_PCI1IOHD (0x098 >> 2) | |
61 | #define GT_PCI1M0LD (0x0a0 >> 2) | |
62 | #define GT_PCI1M0HD (0x0a8 >> 2) | |
63 | #define GT_PCI1M1LD (0x0b0 >> 2) | |
64 | #define GT_PCI1M1HD (0x0b8 >> 2) | |
65 | #define GT_ISD (0x068 >> 2) | |
66 | ||
67 | #define GT_SCS10AR (0x0d0 >> 2) | |
68 | #define GT_SCS32AR (0x0d8 >> 2) | |
69 | #define GT_CS20R (0x0e0 >> 2) | |
70 | #define GT_CS3BOOTR (0x0e8 >> 2) | |
71 | ||
72 | #define GT_PCI0IOREMAP (0x0f0 >> 2) | |
73 | #define GT_PCI0M0REMAP (0x0f8 >> 2) | |
74 | #define GT_PCI0M1REMAP (0x100 >> 2) | |
75 | #define GT_PCI1IOREMAP (0x108 >> 2) | |
76 | #define GT_PCI1M0REMAP (0x110 >> 2) | |
77 | #define GT_PCI1M1REMAP (0x118 >> 2) | |
fde7d5bd TS |
78 | |
79 | /* CPU Error Report */ | |
91ce82b2 PMD |
80 | #define GT_CPUERR_ADDRLO (0x070 >> 2) |
81 | #define GT_CPUERR_ADDRHI (0x078 >> 2) | |
82 | #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ | |
83 | #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ | |
84 | #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ | |
fde7d5bd TS |
85 | |
86 | /* CPU Sync Barrier */ | |
91ce82b2 PMD |
87 | #define GT_PCI0SYNC (0x0c0 >> 2) |
88 | #define GT_PCI1SYNC (0x0c8 >> 2) | |
fde7d5bd TS |
89 | |
90 | /* SDRAM and Device Address Decode */ | |
91ce82b2 PMD |
91 | #define GT_SCS0LD (0x400 >> 2) |
92 | #define GT_SCS0HD (0x404 >> 2) | |
93 | #define GT_SCS1LD (0x408 >> 2) | |
94 | #define GT_SCS1HD (0x40c >> 2) | |
95 | #define GT_SCS2LD (0x410 >> 2) | |
96 | #define GT_SCS2HD (0x414 >> 2) | |
97 | #define GT_SCS3LD (0x418 >> 2) | |
98 | #define GT_SCS3HD (0x41c >> 2) | |
99 | #define GT_CS0LD (0x420 >> 2) | |
100 | #define GT_CS0HD (0x424 >> 2) | |
101 | #define GT_CS1LD (0x428 >> 2) | |
102 | #define GT_CS1HD (0x42c >> 2) | |
103 | #define GT_CS2LD (0x430 >> 2) | |
104 | #define GT_CS2HD (0x434 >> 2) | |
105 | #define GT_CS3LD (0x438 >> 2) | |
106 | #define GT_CS3HD (0x43c >> 2) | |
107 | #define GT_BOOTLD (0x440 >> 2) | |
108 | #define GT_BOOTHD (0x444 >> 2) | |
109 | #define GT_ADERR (0x470 >> 2) | |
fde7d5bd TS |
110 | |
111 | /* SDRAM Configuration */ | |
91ce82b2 PMD |
112 | #define GT_SDRAM_CFG (0x448 >> 2) |
113 | #define GT_SDRAM_OPMODE (0x474 >> 2) | |
114 | #define GT_SDRAM_BM (0x478 >> 2) | |
115 | #define GT_SDRAM_ADDRDECODE (0x47c >> 2) | |
fde7d5bd TS |
116 | |
117 | /* SDRAM Parameters */ | |
91ce82b2 PMD |
118 | #define GT_SDRAM_B0 (0x44c >> 2) |
119 | #define GT_SDRAM_B1 (0x450 >> 2) | |
120 | #define GT_SDRAM_B2 (0x454 >> 2) | |
121 | #define GT_SDRAM_B3 (0x458 >> 2) | |
fde7d5bd TS |
122 | |
123 | /* Device Parameters */ | |
91ce82b2 PMD |
124 | #define GT_DEV_B0 (0x45c >> 2) |
125 | #define GT_DEV_B1 (0x460 >> 2) | |
126 | #define GT_DEV_B2 (0x464 >> 2) | |
127 | #define GT_DEV_B3 (0x468 >> 2) | |
128 | #define GT_DEV_BOOT (0x46c >> 2) | |
fde7d5bd TS |
129 | |
130 | /* ECC */ | |
91ce82b2 PMD |
131 | #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ |
132 | #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ | |
133 | #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ | |
134 | #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ | |
135 | #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ | |
fde7d5bd TS |
136 | |
137 | /* DMA Record */ | |
91ce82b2 PMD |
138 | #define GT_DMA0_CNT (0x800 >> 2) |
139 | #define GT_DMA1_CNT (0x804 >> 2) | |
140 | #define GT_DMA2_CNT (0x808 >> 2) | |
141 | #define GT_DMA3_CNT (0x80c >> 2) | |
142 | #define GT_DMA0_SA (0x810 >> 2) | |
143 | #define GT_DMA1_SA (0x814 >> 2) | |
144 | #define GT_DMA2_SA (0x818 >> 2) | |
145 | #define GT_DMA3_SA (0x81c >> 2) | |
146 | #define GT_DMA0_DA (0x820 >> 2) | |
147 | #define GT_DMA1_DA (0x824 >> 2) | |
148 | #define GT_DMA2_DA (0x828 >> 2) | |
149 | #define GT_DMA3_DA (0x82c >> 2) | |
150 | #define GT_DMA0_NEXT (0x830 >> 2) | |
151 | #define GT_DMA1_NEXT (0x834 >> 2) | |
152 | #define GT_DMA2_NEXT (0x838 >> 2) | |
153 | #define GT_DMA3_NEXT (0x83c >> 2) | |
154 | #define GT_DMA0_CUR (0x870 >> 2) | |
155 | #define GT_DMA1_CUR (0x874 >> 2) | |
156 | #define GT_DMA2_CUR (0x878 >> 2) | |
157 | #define GT_DMA3_CUR (0x87c >> 2) | |
fde7d5bd TS |
158 | |
159 | /* DMA Channel Control */ | |
91ce82b2 PMD |
160 | #define GT_DMA0_CTRL (0x840 >> 2) |
161 | #define GT_DMA1_CTRL (0x844 >> 2) | |
162 | #define GT_DMA2_CTRL (0x848 >> 2) | |
163 | #define GT_DMA3_CTRL (0x84c >> 2) | |
fde7d5bd TS |
164 | |
165 | /* DMA Arbiter */ | |
91ce82b2 | 166 | #define GT_DMA_ARB (0x860 >> 2) |
fde7d5bd TS |
167 | |
168 | /* Timer/Counter */ | |
91ce82b2 PMD |
169 | #define GT_TC0 (0x850 >> 2) |
170 | #define GT_TC1 (0x854 >> 2) | |
171 | #define GT_TC2 (0x858 >> 2) | |
172 | #define GT_TC3 (0x85c >> 2) | |
173 | #define GT_TC_CONTROL (0x864 >> 2) | |
fde7d5bd TS |
174 | |
175 | /* PCI Internal */ | |
91ce82b2 PMD |
176 | #define GT_PCI0_CMD (0xc00 >> 2) |
177 | #define GT_PCI0_TOR (0xc04 >> 2) | |
178 | #define GT_PCI0_BS_SCS10 (0xc08 >> 2) | |
179 | #define GT_PCI0_BS_SCS32 (0xc0c >> 2) | |
180 | #define GT_PCI0_BS_CS20 (0xc10 >> 2) | |
181 | #define GT_PCI0_BS_CS3BT (0xc14 >> 2) | |
182 | #define GT_PCI1_IACK (0xc30 >> 2) | |
183 | #define GT_PCI0_IACK (0xc34 >> 2) | |
184 | #define GT_PCI0_BARE (0xc3c >> 2) | |
185 | #define GT_PCI0_PREFMBR (0xc40 >> 2) | |
186 | #define GT_PCI0_SCS10_BAR (0xc48 >> 2) | |
187 | #define GT_PCI0_SCS32_BAR (0xc4c >> 2) | |
188 | #define GT_PCI0_CS20_BAR (0xc50 >> 2) | |
189 | #define GT_PCI0_CS3BT_BAR (0xc54 >> 2) | |
190 | #define GT_PCI0_SSCS10_BAR (0xc58 >> 2) | |
191 | #define GT_PCI0_SSCS32_BAR (0xc5c >> 2) | |
192 | #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) | |
193 | #define GT_PCI1_CMD (0xc80 >> 2) | |
194 | #define GT_PCI1_TOR (0xc84 >> 2) | |
195 | #define GT_PCI1_BS_SCS10 (0xc88 >> 2) | |
196 | #define GT_PCI1_BS_SCS32 (0xc8c >> 2) | |
197 | #define GT_PCI1_BS_CS20 (0xc90 >> 2) | |
198 | #define GT_PCI1_BS_CS3BT (0xc94 >> 2) | |
199 | #define GT_PCI1_BARE (0xcbc >> 2) | |
200 | #define GT_PCI1_PREFMBR (0xcc0 >> 2) | |
201 | #define GT_PCI1_SCS10_BAR (0xcc8 >> 2) | |
202 | #define GT_PCI1_SCS32_BAR (0xccc >> 2) | |
203 | #define GT_PCI1_CS20_BAR (0xcd0 >> 2) | |
204 | #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) | |
205 | #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) | |
206 | #define GT_PCI1_SSCS32_BAR (0xcdc >> 2) | |
207 | #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) | |
208 | #define GT_PCI1_CFGADDR (0xcf0 >> 2) | |
209 | #define GT_PCI1_CFGDATA (0xcf4 >> 2) | |
210 | #define GT_PCI0_CFGADDR (0xcf8 >> 2) | |
211 | #define GT_PCI0_CFGDATA (0xcfc >> 2) | |
fde7d5bd TS |
212 | |
213 | /* Interrupts */ | |
91ce82b2 PMD |
214 | #define GT_INTRCAUSE (0xc18 >> 2) |
215 | #define GT_INTRMASK (0xc1c >> 2) | |
216 | #define GT_PCI0_ICMASK (0xc24 >> 2) | |
217 | #define GT_PCI0_SERR0MASK (0xc28 >> 2) | |
218 | #define GT_CPU_INTSEL (0xc70 >> 2) | |
219 | #define GT_PCI0_INTSEL (0xc74 >> 2) | |
220 | #define GT_HINTRCAUSE (0xc98 >> 2) | |
221 | #define GT_HINTRMASK (0xc9c >> 2) | |
222 | #define GT_PCI0_HICMASK (0xca4 >> 2) | |
223 | #define GT_PCI1_SERR1MASK (0xca8 >> 2) | |
fde7d5bd | 224 | |
a0a8793e | 225 | #define PCI_MAPPING_ENTRY(regname) \ |
a8170e5e AK |
226 | hwaddr regname ##_start; \ |
227 | hwaddr regname ##_length; \ | |
fc2bf449 | 228 | MemoryRegion regname ##_mem |
a0a8793e | 229 | |
8d43d7e5 AF |
230 | #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120" |
231 | ||
232 | #define GT64120_PCI_HOST_BRIDGE(obj) \ | |
233 | OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE) | |
234 | ||
fde7d5bd | 235 | typedef struct GT64120State { |
67c332fd | 236 | PCIHostState parent_obj; |
8d43d7e5 | 237 | |
fde7d5bd | 238 | uint32_t regs[GT_REGS]; |
a0a8793e | 239 | PCI_MAPPING_ENTRY(PCI0IO); |
f720f203 HP |
240 | PCI_MAPPING_ENTRY(PCI0M0); |
241 | PCI_MAPPING_ENTRY(PCI0M1); | |
a0a8793e | 242 | PCI_MAPPING_ENTRY(ISD); |
f720f203 HP |
243 | MemoryRegion pci0_mem; |
244 | AddressSpace pci0_mem_as; | |
fde7d5bd TS |
245 | } GT64120State; |
246 | ||
a0a8793e | 247 | /* Adjust range to avoid touching space which isn't mappable via PCI */ |
c47aee35 PMD |
248 | /* |
249 | * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 | |
250 | * 0x1fc00000 - 0x1fd00000 | |
251 | */ | |
252 | static void check_reserved_space(hwaddr *start, hwaddr *length) | |
a0a8793e | 253 | { |
a8170e5e AK |
254 | hwaddr begin = *start; |
255 | hwaddr end = *start + *length; | |
a0a8793e | 256 | |
53539655 | 257 | if (end >= 0x1e000000LL && end < 0x1f100000LL) { |
a0a8793e | 258 | end = 0x1e000000LL; |
53539655 PMD |
259 | } |
260 | if (begin >= 0x1e000000LL && begin < 0x1f100000LL) { | |
a0a8793e | 261 | begin = 0x1f100000LL; |
53539655 PMD |
262 | } |
263 | if (end >= 0x1fc00000LL && end < 0x1fd00000LL) { | |
a0a8793e | 264 | end = 0x1fc00000LL; |
53539655 PMD |
265 | } |
266 | if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) { | |
a0a8793e | 267 | begin = 0x1fd00000LL; |
53539655 | 268 | } |
a0a8793e | 269 | /* XXX: This is broken when a reserved range splits the requested range */ |
53539655 | 270 | if (end >= 0x1f100000LL && begin < 0x1e000000LL) { |
a0a8793e | 271 | end = 0x1e000000LL; |
53539655 PMD |
272 | } |
273 | if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) { | |
a0a8793e | 274 | end = 0x1fc00000LL; |
53539655 | 275 | } |
a0a8793e TS |
276 | |
277 | *start = begin; | |
278 | *length = end - begin; | |
279 | } | |
280 | ||
281 | static void gt64120_isd_mapping(GT64120State *s) | |
282 | { | |
63fc7375 PB |
283 | /* Bits 14:0 of ISD map to bits 35:21 of the start address. */ |
284 | hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull; | |
a8170e5e | 285 | hwaddr length = 0x1000; |
a0a8793e | 286 | |
fc2bf449 AK |
287 | if (s->ISD_length) { |
288 | memory_region_del_subregion(get_system_memory(), &s->ISD_mem); | |
289 | } | |
a0a8793e TS |
290 | check_reserved_space(&start, &length); |
291 | length = 0x1000; | |
292 | /* Map new address */ | |
ab6bff42 | 293 | trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start); |
a0a8793e TS |
294 | s->ISD_start = start; |
295 | s->ISD_length = length; | |
fc2bf449 | 296 | memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem); |
a0a8793e TS |
297 | } |
298 | ||
9414cc6f | 299 | static void gt64120_pci_mapping(GT64120State *s) |
2a1086d9 | 300 | { |
f720f203 HP |
301 | /* Update PCI0IO mapping */ |
302 | if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) { | |
303 | /* Unmap old IO address */ | |
304 | if (s->PCI0IO_length) { | |
305 | memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem); | |
306 | object_unparent(OBJECT(&s->PCI0IO_mem)); | |
307 | } | |
308 | /* Map new IO address */ | |
309 | s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; | |
310 | s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - | |
311 | (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; | |
312 | if (s->PCI0IO_length) { | |
313 | memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io", | |
314 | get_system_io(), 0, s->PCI0IO_length); | |
315 | memory_region_add_subregion(get_system_memory(), s->PCI0IO_start, | |
316 | &s->PCI0IO_mem); | |
317 | } | |
318 | } | |
319 | ||
320 | /* Update PCI0M0 mapping */ | |
321 | if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) { | |
322 | /* Unmap old MEM address */ | |
323 | if (s->PCI0M0_length) { | |
324 | memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem); | |
325 | object_unparent(OBJECT(&s->PCI0M0_mem)); | |
326 | } | |
327 | /* Map new mem address */ | |
328 | s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21; | |
329 | s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) - | |
330 | (s->regs[GT_PCI0M0LD] & 0x7f)) << 21; | |
331 | if (s->PCI0M0_length) { | |
332 | memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0", | |
333 | &s->pci0_mem, s->PCI0M0_start, | |
334 | s->PCI0M0_length); | |
335 | memory_region_add_subregion(get_system_memory(), s->PCI0M0_start, | |
336 | &s->PCI0M0_mem); | |
337 | } | |
338 | } | |
339 | ||
340 | /* Update PCI0M1 mapping */ | |
341 | if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) { | |
342 | /* Unmap old MEM address */ | |
343 | if (s->PCI0M1_length) { | |
344 | memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem); | |
345 | object_unparent(OBJECT(&s->PCI0M1_mem)); | |
346 | } | |
347 | /* Map new mem address */ | |
348 | s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21; | |
349 | s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) - | |
350 | (s->regs[GT_PCI0M1LD] & 0x7f)) << 21; | |
351 | if (s->PCI0M1_length) { | |
352 | memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1", | |
353 | &s->pci0_mem, s->PCI0M1_start, | |
354 | s->PCI0M1_length); | |
355 | memory_region_add_subregion(get_system_memory(), s->PCI0M1_start, | |
356 | &s->PCI0M1_mem); | |
357 | } | |
9414cc6f | 358 | } |
2a1086d9 TS |
359 | } |
360 | ||
427e1750 SL |
361 | static int gt64120_post_load(void *opaque, int version_id) |
362 | { | |
363 | GT64120State *s = opaque; | |
364 | ||
365 | gt64120_isd_mapping(s); | |
366 | gt64120_pci_mapping(s); | |
367 | ||
368 | return 0; | |
369 | } | |
370 | ||
371 | static const VMStateDescription vmstate_gt64120 = { | |
372 | .name = "gt64120", | |
373 | .version_id = 1, | |
374 | .minimum_version_id = 1, | |
375 | .post_load = gt64120_post_load, | |
376 | .fields = (VMStateField[]) { | |
377 | VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS), | |
378 | VMSTATE_END_OF_LIST() | |
379 | } | |
380 | }; | |
381 | ||
b61104b2 PMD |
382 | static void gt64120_writel(void *opaque, hwaddr addr, |
383 | uint64_t val, unsigned size) | |
fde7d5bd TS |
384 | { |
385 | GT64120State *s = opaque; | |
67c332fd | 386 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
fde7d5bd TS |
387 | uint32_t saddr; |
388 | ||
53539655 | 389 | if (!(s->regs[GT_CPU] & 0x00001000)) { |
1931e260 | 390 | val = bswap32(val); |
53539655 | 391 | } |
0da75eb1 | 392 | |
fde7d5bd TS |
393 | saddr = (addr & 0xfff) >> 2; |
394 | switch (saddr) { | |
0da75eb1 TS |
395 | |
396 | /* CPU Configuration */ | |
fde7d5bd TS |
397 | case GT_CPU: |
398 | s->regs[GT_CPU] = val; | |
fde7d5bd TS |
399 | break; |
400 | case GT_MULTI: | |
7d37435b | 401 | /* Read-only register as only one GT64xxx is present on the CPU bus */ |
fde7d5bd TS |
402 | break; |
403 | ||
404 | /* CPU Address Decode */ | |
405 | case GT_PCI0IOLD: | |
406 | s->regs[GT_PCI0IOLD] = val & 0x00007fff; | |
407 | s->regs[GT_PCI0IOREMAP] = val & 0x000007ff; | |
9414cc6f | 408 | gt64120_pci_mapping(s); |
fde7d5bd TS |
409 | break; |
410 | case GT_PCI0M0LD: | |
411 | s->regs[GT_PCI0M0LD] = val & 0x00007fff; | |
412 | s->regs[GT_PCI0M0REMAP] = val & 0x000007ff; | |
f720f203 | 413 | gt64120_pci_mapping(s); |
fde7d5bd TS |
414 | break; |
415 | case GT_PCI0M1LD: | |
416 | s->regs[GT_PCI0M1LD] = val & 0x00007fff; | |
417 | s->regs[GT_PCI0M1REMAP] = val & 0x000007ff; | |
f720f203 | 418 | gt64120_pci_mapping(s); |
fde7d5bd TS |
419 | break; |
420 | case GT_PCI1IOLD: | |
421 | s->regs[GT_PCI1IOLD] = val & 0x00007fff; | |
422 | s->regs[GT_PCI1IOREMAP] = val & 0x000007ff; | |
fde7d5bd TS |
423 | break; |
424 | case GT_PCI1M0LD: | |
425 | s->regs[GT_PCI1M0LD] = val & 0x00007fff; | |
426 | s->regs[GT_PCI1M0REMAP] = val & 0x000007ff; | |
fde7d5bd TS |
427 | break; |
428 | case GT_PCI1M1LD: | |
429 | s->regs[GT_PCI1M1LD] = val & 0x00007fff; | |
430 | s->regs[GT_PCI1M1REMAP] = val & 0x000007ff; | |
fde7d5bd | 431 | break; |
f720f203 HP |
432 | case GT_PCI0M0HD: |
433 | case GT_PCI0M1HD: | |
fde7d5bd | 434 | case GT_PCI0IOHD: |
bb433bef TS |
435 | s->regs[saddr] = val & 0x0000007f; |
436 | gt64120_pci_mapping(s); | |
437 | break; | |
fde7d5bd TS |
438 | case GT_PCI1IOHD: |
439 | case GT_PCI1M0HD: | |
440 | case GT_PCI1M1HD: | |
441 | s->regs[saddr] = val & 0x0000007f; | |
fde7d5bd | 442 | break; |
a0a8793e TS |
443 | case GT_ISD: |
444 | s->regs[saddr] = val & 0x00007fff; | |
445 | gt64120_isd_mapping(s); | |
446 | break; | |
447 | ||
fde7d5bd TS |
448 | case GT_PCI0IOREMAP: |
449 | case GT_PCI0M0REMAP: | |
450 | case GT_PCI0M1REMAP: | |
451 | case GT_PCI1IOREMAP: | |
452 | case GT_PCI1M0REMAP: | |
453 | case GT_PCI1M1REMAP: | |
454 | s->regs[saddr] = val & 0x000007ff; | |
fde7d5bd TS |
455 | break; |
456 | ||
457 | /* CPU Error Report */ | |
458 | case GT_CPUERR_ADDRLO: | |
459 | case GT_CPUERR_ADDRHI: | |
460 | case GT_CPUERR_DATALO: | |
461 | case GT_CPUERR_DATAHI: | |
462 | case GT_CPUERR_PARITY: | |
7d37435b | 463 | /* Read-only registers, do nothing */ |
641ca2bf PMD |
464 | qemu_log_mask(LOG_GUEST_ERROR, |
465 | "gt64120: Read-only register write " | |
466 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
467 | saddr << 2, size, size << 1, val); | |
0da75eb1 TS |
468 | break; |
469 | ||
470 | /* CPU Sync Barrier */ | |
471 | case GT_PCI0SYNC: | |
472 | case GT_PCI1SYNC: | |
7d37435b | 473 | /* Read-only registers, do nothing */ |
641ca2bf PMD |
474 | qemu_log_mask(LOG_GUEST_ERROR, |
475 | "gt64120: Read-only register write " | |
476 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
477 | saddr << 2, size, size << 1, val); | |
fde7d5bd TS |
478 | break; |
479 | ||
05b4ff43 TS |
480 | /* SDRAM and Device Address Decode */ |
481 | case GT_SCS0LD: | |
482 | case GT_SCS0HD: | |
483 | case GT_SCS1LD: | |
484 | case GT_SCS1HD: | |
485 | case GT_SCS2LD: | |
486 | case GT_SCS2HD: | |
487 | case GT_SCS3LD: | |
488 | case GT_SCS3HD: | |
489 | case GT_CS0LD: | |
490 | case GT_CS0HD: | |
491 | case GT_CS1LD: | |
492 | case GT_CS1HD: | |
493 | case GT_CS2LD: | |
494 | case GT_CS2HD: | |
495 | case GT_CS3LD: | |
496 | case GT_CS3HD: | |
497 | case GT_BOOTLD: | |
498 | case GT_BOOTHD: | |
499 | case GT_ADERR: | |
500 | /* SDRAM Configuration */ | |
501 | case GT_SDRAM_CFG: | |
502 | case GT_SDRAM_OPMODE: | |
503 | case GT_SDRAM_BM: | |
504 | case GT_SDRAM_ADDRDECODE: | |
505 | /* Accept and ignore SDRAM interleave configuration */ | |
506 | s->regs[saddr] = val; | |
507 | break; | |
508 | ||
509 | /* Device Parameters */ | |
510 | case GT_DEV_B0: | |
511 | case GT_DEV_B1: | |
512 | case GT_DEV_B2: | |
513 | case GT_DEV_B3: | |
514 | case GT_DEV_BOOT: | |
515 | /* Not implemented */ | |
641ca2bf PMD |
516 | qemu_log_mask(LOG_UNIMP, |
517 | "gt64120: Unimplemented device register write " | |
518 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
519 | saddr << 2, size, size << 1, val); | |
05b4ff43 TS |
520 | break; |
521 | ||
fde7d5bd TS |
522 | /* ECC */ |
523 | case GT_ECC_ERRDATALO: | |
524 | case GT_ECC_ERRDATAHI: | |
525 | case GT_ECC_MEM: | |
526 | case GT_ECC_CALC: | |
527 | case GT_ECC_ERRADDR: | |
0da75eb1 | 528 | /* Read-only registers, do nothing */ |
641ca2bf PMD |
529 | qemu_log_mask(LOG_GUEST_ERROR, |
530 | "gt64120: Read-only register write " | |
531 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
532 | saddr << 2, size, size << 1, val); | |
fde7d5bd TS |
533 | break; |
534 | ||
05b4ff43 TS |
535 | /* DMA Record */ |
536 | case GT_DMA0_CNT: | |
537 | case GT_DMA1_CNT: | |
538 | case GT_DMA2_CNT: | |
539 | case GT_DMA3_CNT: | |
540 | case GT_DMA0_SA: | |
541 | case GT_DMA1_SA: | |
542 | case GT_DMA2_SA: | |
543 | case GT_DMA3_SA: | |
544 | case GT_DMA0_DA: | |
545 | case GT_DMA1_DA: | |
546 | case GT_DMA2_DA: | |
547 | case GT_DMA3_DA: | |
548 | case GT_DMA0_NEXT: | |
549 | case GT_DMA1_NEXT: | |
550 | case GT_DMA2_NEXT: | |
551 | case GT_DMA3_NEXT: | |
552 | case GT_DMA0_CUR: | |
553 | case GT_DMA1_CUR: | |
554 | case GT_DMA2_CUR: | |
555 | case GT_DMA3_CUR: | |
05b4ff43 TS |
556 | |
557 | /* DMA Channel Control */ | |
558 | case GT_DMA0_CTRL: | |
559 | case GT_DMA1_CTRL: | |
560 | case GT_DMA2_CTRL: | |
561 | case GT_DMA3_CTRL: | |
05b4ff43 TS |
562 | |
563 | /* DMA Arbiter */ | |
564 | case GT_DMA_ARB: | |
565 | /* Not implemented */ | |
641ca2bf PMD |
566 | qemu_log_mask(LOG_UNIMP, |
567 | "gt64120: Unimplemented DMA register write " | |
568 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
569 | saddr << 2, size, size << 1, val); | |
05b4ff43 TS |
570 | break; |
571 | ||
572 | /* Timer/Counter */ | |
573 | case GT_TC0: | |
574 | case GT_TC1: | |
575 | case GT_TC2: | |
576 | case GT_TC3: | |
577 | case GT_TC_CONTROL: | |
578 | /* Not implemented */ | |
641ca2bf PMD |
579 | qemu_log_mask(LOG_UNIMP, |
580 | "gt64120: Unimplemented timer register write " | |
581 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
582 | saddr << 2, size, size << 1, val); | |
05b4ff43 TS |
583 | break; |
584 | ||
fde7d5bd TS |
585 | /* PCI Internal */ |
586 | case GT_PCI0_CMD: | |
587 | case GT_PCI1_CMD: | |
588 | s->regs[saddr] = val & 0x0401fc0f; | |
589 | break; | |
05b4ff43 TS |
590 | case GT_PCI0_TOR: |
591 | case GT_PCI0_BS_SCS10: | |
592 | case GT_PCI0_BS_SCS32: | |
593 | case GT_PCI0_BS_CS20: | |
594 | case GT_PCI0_BS_CS3BT: | |
595 | case GT_PCI1_IACK: | |
596 | case GT_PCI0_IACK: | |
597 | case GT_PCI0_BARE: | |
598 | case GT_PCI0_PREFMBR: | |
599 | case GT_PCI0_SCS10_BAR: | |
600 | case GT_PCI0_SCS32_BAR: | |
601 | case GT_PCI0_CS20_BAR: | |
602 | case GT_PCI0_CS3BT_BAR: | |
603 | case GT_PCI0_SSCS10_BAR: | |
604 | case GT_PCI0_SSCS32_BAR: | |
605 | case GT_PCI0_SCS3BT_BAR: | |
606 | case GT_PCI1_TOR: | |
607 | case GT_PCI1_BS_SCS10: | |
608 | case GT_PCI1_BS_SCS32: | |
609 | case GT_PCI1_BS_CS20: | |
610 | case GT_PCI1_BS_CS3BT: | |
611 | case GT_PCI1_BARE: | |
612 | case GT_PCI1_PREFMBR: | |
613 | case GT_PCI1_SCS10_BAR: | |
614 | case GT_PCI1_SCS32_BAR: | |
615 | case GT_PCI1_CS20_BAR: | |
616 | case GT_PCI1_CS3BT_BAR: | |
617 | case GT_PCI1_SSCS10_BAR: | |
618 | case GT_PCI1_SSCS32_BAR: | |
619 | case GT_PCI1_SCS3BT_BAR: | |
620 | case GT_PCI1_CFGADDR: | |
621 | case GT_PCI1_CFGDATA: | |
622 | /* not implemented */ | |
641ca2bf PMD |
623 | qemu_log_mask(LOG_UNIMP, |
624 | "gt64120: Unimplemented timer register write " | |
625 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
626 | saddr << 2, size, size << 1, val); | |
05b4ff43 | 627 | break; |
fde7d5bd | 628 | case GT_PCI0_CFGADDR: |
67c332fd | 629 | phb->config_reg = val & 0x80fffffc; |
fde7d5bd TS |
630 | break; |
631 | case GT_PCI0_CFGDATA: | |
67c332fd | 632 | if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { |
c6c99c3f | 633 | val = bswap32(val); |
67c332fd AF |
634 | } |
635 | if (phb->config_reg & (1u << 31)) { | |
636 | pci_data_write(phb->bus, phb->config_reg, val, 4); | |
637 | } | |
05b4ff43 TS |
638 | break; |
639 | ||
640 | /* Interrupts */ | |
641 | case GT_INTRCAUSE: | |
642 | /* not really implemented */ | |
643 | s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); | |
644 | s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); | |
ab6bff42 | 645 | trace_gt64120_write("INTRCAUSE", size << 1, val); |
05b4ff43 TS |
646 | break; |
647 | case GT_INTRMASK: | |
648 | s->regs[saddr] = val & 0x3c3ffffe; | |
ab6bff42 | 649 | trace_gt64120_write("INTRMASK", size << 1, val); |
05b4ff43 TS |
650 | break; |
651 | case GT_PCI0_ICMASK: | |
652 | s->regs[saddr] = val & 0x03fffffe; | |
ab6bff42 | 653 | trace_gt64120_write("ICMASK", size << 1, val); |
05b4ff43 TS |
654 | break; |
655 | case GT_PCI0_SERR0MASK: | |
656 | s->regs[saddr] = val & 0x0000003f; | |
ab6bff42 | 657 | trace_gt64120_write("SERR0MASK", size << 1, val); |
05b4ff43 TS |
658 | break; |
659 | ||
660 | /* Reserved when only PCI_0 is configured. */ | |
661 | case GT_HINTRCAUSE: | |
662 | case GT_CPU_INTSEL: | |
663 | case GT_PCI0_INTSEL: | |
664 | case GT_HINTRMASK: | |
665 | case GT_PCI0_HICMASK: | |
666 | case GT_PCI1_SERR1MASK: | |
667 | /* not implemented */ | |
fde7d5bd TS |
668 | break; |
669 | ||
0da75eb1 TS |
670 | /* SDRAM Parameters */ |
671 | case GT_SDRAM_B0: | |
672 | case GT_SDRAM_B1: | |
673 | case GT_SDRAM_B2: | |
674 | case GT_SDRAM_B3: | |
c47aee35 PMD |
675 | /* |
676 | * We don't simulate electrical parameters of the SDRAM. | |
677 | * Accept, but ignore the values. | |
678 | */ | |
0da75eb1 TS |
679 | s->regs[saddr] = val; |
680 | break; | |
681 | ||
fde7d5bd | 682 | default: |
641ca2bf PMD |
683 | qemu_log_mask(LOG_GUEST_ERROR, |
684 | "gt64120: Illegal register write " | |
685 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
686 | saddr << 2, size, size << 1, val); | |
fde7d5bd TS |
687 | break; |
688 | } | |
689 | } | |
690 | ||
b61104b2 PMD |
691 | static uint64_t gt64120_readl(void *opaque, |
692 | hwaddr addr, unsigned size) | |
fde7d5bd TS |
693 | { |
694 | GT64120State *s = opaque; | |
67c332fd | 695 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
fde7d5bd TS |
696 | uint32_t val; |
697 | uint32_t saddr; | |
698 | ||
fde7d5bd | 699 | saddr = (addr & 0xfff) >> 2; |
fde7d5bd TS |
700 | switch (saddr) { |
701 | ||
0da75eb1 TS |
702 | /* CPU Configuration */ |
703 | case GT_MULTI: | |
c47aee35 PMD |
704 | /* |
705 | * Only one GT64xxx is present on the CPU bus, return | |
706 | * the initial value. | |
707 | */ | |
0da75eb1 TS |
708 | val = s->regs[saddr]; |
709 | break; | |
710 | ||
fde7d5bd TS |
711 | /* CPU Error Report */ |
712 | case GT_CPUERR_ADDRLO: | |
713 | case GT_CPUERR_ADDRHI: | |
714 | case GT_CPUERR_DATALO: | |
715 | case GT_CPUERR_DATAHI: | |
716 | case GT_CPUERR_PARITY: | |
c47aee35 | 717 | /* Emulated memory has no error, always return the initial values. */ |
0da75eb1 TS |
718 | val = s->regs[saddr]; |
719 | break; | |
720 | ||
721 | /* CPU Sync Barrier */ | |
722 | case GT_PCI0SYNC: | |
723 | case GT_PCI1SYNC: | |
c47aee35 PMD |
724 | /* |
725 | * Reading those register should empty all FIFO on the PCI | |
726 | * bus, which are not emulated. The return value should be | |
727 | * a random value that should be ignored. | |
728 | */ | |
5fafdf24 | 729 | val = 0xc000ffee; |
fde7d5bd TS |
730 | break; |
731 | ||
732 | /* ECC */ | |
733 | case GT_ECC_ERRDATALO: | |
734 | case GT_ECC_ERRDATAHI: | |
735 | case GT_ECC_MEM: | |
736 | case GT_ECC_CALC: | |
737 | case GT_ECC_ERRADDR: | |
c47aee35 | 738 | /* Emulated memory has no error, always return the initial values. */ |
0da75eb1 | 739 | val = s->regs[saddr]; |
fde7d5bd TS |
740 | break; |
741 | ||
742 | case GT_CPU: | |
05b4ff43 TS |
743 | case GT_SCS10LD: |
744 | case GT_SCS10HD: | |
745 | case GT_SCS32LD: | |
746 | case GT_SCS32HD: | |
747 | case GT_CS20LD: | |
748 | case GT_CS20HD: | |
749 | case GT_CS3BOOTLD: | |
750 | case GT_CS3BOOTHD: | |
751 | case GT_SCS10AR: | |
752 | case GT_SCS32AR: | |
753 | case GT_CS20R: | |
754 | case GT_CS3BOOTR: | |
fde7d5bd TS |
755 | case GT_PCI0IOLD: |
756 | case GT_PCI0M0LD: | |
757 | case GT_PCI0M1LD: | |
758 | case GT_PCI1IOLD: | |
759 | case GT_PCI1M0LD: | |
760 | case GT_PCI1M1LD: | |
761 | case GT_PCI0IOHD: | |
762 | case GT_PCI0M0HD: | |
763 | case GT_PCI0M1HD: | |
764 | case GT_PCI1IOHD: | |
765 | case GT_PCI1M0HD: | |
766 | case GT_PCI1M1HD: | |
fde7d5bd TS |
767 | case GT_PCI0IOREMAP: |
768 | case GT_PCI0M0REMAP: | |
769 | case GT_PCI0M1REMAP: | |
770 | case GT_PCI1IOREMAP: | |
771 | case GT_PCI1M0REMAP: | |
772 | case GT_PCI1M1REMAP: | |
05b4ff43 | 773 | case GT_ISD: |
fde7d5bd TS |
774 | val = s->regs[saddr]; |
775 | break; | |
776 | case GT_PCI0_IACK: | |
5fafdf24 | 777 | /* Read the IRQ number */ |
4de9b249 | 778 | val = pic_read_irq(isa_pic); |
fde7d5bd TS |
779 | break; |
780 | ||
05b4ff43 TS |
781 | /* SDRAM and Device Address Decode */ |
782 | case GT_SCS0LD: | |
783 | case GT_SCS0HD: | |
784 | case GT_SCS1LD: | |
785 | case GT_SCS1HD: | |
786 | case GT_SCS2LD: | |
787 | case GT_SCS2HD: | |
788 | case GT_SCS3LD: | |
789 | case GT_SCS3HD: | |
790 | case GT_CS0LD: | |
791 | case GT_CS0HD: | |
792 | case GT_CS1LD: | |
793 | case GT_CS1HD: | |
794 | case GT_CS2LD: | |
795 | case GT_CS2HD: | |
796 | case GT_CS3LD: | |
797 | case GT_CS3HD: | |
798 | case GT_BOOTLD: | |
799 | case GT_BOOTHD: | |
800 | case GT_ADERR: | |
801 | val = s->regs[saddr]; | |
802 | break; | |
803 | ||
804 | /* SDRAM Configuration */ | |
805 | case GT_SDRAM_CFG: | |
806 | case GT_SDRAM_OPMODE: | |
807 | case GT_SDRAM_BM: | |
808 | case GT_SDRAM_ADDRDECODE: | |
809 | val = s->regs[saddr]; | |
810 | break; | |
811 | ||
0da75eb1 TS |
812 | /* SDRAM Parameters */ |
813 | case GT_SDRAM_B0: | |
814 | case GT_SDRAM_B1: | |
815 | case GT_SDRAM_B2: | |
816 | case GT_SDRAM_B3: | |
c47aee35 PMD |
817 | /* |
818 | * We don't simulate electrical parameters of the SDRAM. | |
819 | * Just return the last written value. | |
820 | */ | |
0da75eb1 TS |
821 | val = s->regs[saddr]; |
822 | break; | |
823 | ||
05b4ff43 TS |
824 | /* Device Parameters */ |
825 | case GT_DEV_B0: | |
826 | case GT_DEV_B1: | |
827 | case GT_DEV_B2: | |
828 | case GT_DEV_B3: | |
829 | case GT_DEV_BOOT: | |
830 | val = s->regs[saddr]; | |
831 | break; | |
832 | ||
833 | /* DMA Record */ | |
834 | case GT_DMA0_CNT: | |
835 | case GT_DMA1_CNT: | |
836 | case GT_DMA2_CNT: | |
837 | case GT_DMA3_CNT: | |
838 | case GT_DMA0_SA: | |
839 | case GT_DMA1_SA: | |
840 | case GT_DMA2_SA: | |
841 | case GT_DMA3_SA: | |
842 | case GT_DMA0_DA: | |
843 | case GT_DMA1_DA: | |
844 | case GT_DMA2_DA: | |
845 | case GT_DMA3_DA: | |
846 | case GT_DMA0_NEXT: | |
847 | case GT_DMA1_NEXT: | |
848 | case GT_DMA2_NEXT: | |
849 | case GT_DMA3_NEXT: | |
850 | case GT_DMA0_CUR: | |
851 | case GT_DMA1_CUR: | |
852 | case GT_DMA2_CUR: | |
853 | case GT_DMA3_CUR: | |
854 | val = s->regs[saddr]; | |
855 | break; | |
856 | ||
857 | /* DMA Channel Control */ | |
858 | case GT_DMA0_CTRL: | |
859 | case GT_DMA1_CTRL: | |
860 | case GT_DMA2_CTRL: | |
861 | case GT_DMA3_CTRL: | |
862 | val = s->regs[saddr]; | |
863 | break; | |
864 | ||
865 | /* DMA Arbiter */ | |
866 | case GT_DMA_ARB: | |
867 | val = s->regs[saddr]; | |
868 | break; | |
869 | ||
870 | /* Timer/Counter */ | |
871 | case GT_TC0: | |
872 | case GT_TC1: | |
873 | case GT_TC2: | |
874 | case GT_TC3: | |
875 | case GT_TC_CONTROL: | |
876 | val = s->regs[saddr]; | |
877 | break; | |
878 | ||
fde7d5bd TS |
879 | /* PCI Internal */ |
880 | case GT_PCI0_CFGADDR: | |
67c332fd | 881 | val = phb->config_reg; |
fde7d5bd TS |
882 | break; |
883 | case GT_PCI0_CFGDATA: | |
67c332fd | 884 | if (!(phb->config_reg & (1 << 31))) { |
c6c99c3f | 885 | val = 0xffffffff; |
67c332fd AF |
886 | } else { |
887 | val = pci_data_read(phb->bus, phb->config_reg, 4); | |
888 | } | |
889 | if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { | |
c6c99c3f | 890 | val = bswap32(val); |
67c332fd | 891 | } |
05b4ff43 TS |
892 | break; |
893 | ||
894 | case GT_PCI0_CMD: | |
895 | case GT_PCI0_TOR: | |
896 | case GT_PCI0_BS_SCS10: | |
897 | case GT_PCI0_BS_SCS32: | |
898 | case GT_PCI0_BS_CS20: | |
899 | case GT_PCI0_BS_CS3BT: | |
900 | case GT_PCI1_IACK: | |
901 | case GT_PCI0_BARE: | |
902 | case GT_PCI0_PREFMBR: | |
903 | case GT_PCI0_SCS10_BAR: | |
904 | case GT_PCI0_SCS32_BAR: | |
905 | case GT_PCI0_CS20_BAR: | |
906 | case GT_PCI0_CS3BT_BAR: | |
907 | case GT_PCI0_SSCS10_BAR: | |
908 | case GT_PCI0_SSCS32_BAR: | |
909 | case GT_PCI0_SCS3BT_BAR: | |
910 | case GT_PCI1_CMD: | |
911 | case GT_PCI1_TOR: | |
912 | case GT_PCI1_BS_SCS10: | |
913 | case GT_PCI1_BS_SCS32: | |
914 | case GT_PCI1_BS_CS20: | |
915 | case GT_PCI1_BS_CS3BT: | |
916 | case GT_PCI1_BARE: | |
917 | case GT_PCI1_PREFMBR: | |
918 | case GT_PCI1_SCS10_BAR: | |
919 | case GT_PCI1_SCS32_BAR: | |
920 | case GT_PCI1_CS20_BAR: | |
921 | case GT_PCI1_CS3BT_BAR: | |
922 | case GT_PCI1_SSCS10_BAR: | |
923 | case GT_PCI1_SSCS32_BAR: | |
924 | case GT_PCI1_SCS3BT_BAR: | |
925 | case GT_PCI1_CFGADDR: | |
926 | case GT_PCI1_CFGDATA: | |
927 | val = s->regs[saddr]; | |
928 | break; | |
929 | ||
930 | /* Interrupts */ | |
931 | case GT_INTRCAUSE: | |
932 | val = s->regs[saddr]; | |
ab6bff42 | 933 | trace_gt64120_read("INTRCAUSE", size << 1, val); |
05b4ff43 TS |
934 | break; |
935 | case GT_INTRMASK: | |
936 | val = s->regs[saddr]; | |
ab6bff42 | 937 | trace_gt64120_read("INTRMASK", size << 1, val); |
05b4ff43 TS |
938 | break; |
939 | case GT_PCI0_ICMASK: | |
940 | val = s->regs[saddr]; | |
ab6bff42 | 941 | trace_gt64120_read("ICMASK", size << 1, val); |
05b4ff43 TS |
942 | break; |
943 | case GT_PCI0_SERR0MASK: | |
944 | val = s->regs[saddr]; | |
ab6bff42 | 945 | trace_gt64120_read("SERR0MASK", size << 1, val); |
05b4ff43 TS |
946 | break; |
947 | ||
948 | /* Reserved when only PCI_0 is configured. */ | |
949 | case GT_HINTRCAUSE: | |
950 | case GT_CPU_INTSEL: | |
951 | case GT_PCI0_INTSEL: | |
952 | case GT_HINTRMASK: | |
953 | case GT_PCI0_HICMASK: | |
954 | case GT_PCI1_SERR1MASK: | |
955 | val = s->regs[saddr]; | |
fde7d5bd TS |
956 | break; |
957 | ||
958 | default: | |
959 | val = s->regs[saddr]; | |
641ca2bf PMD |
960 | qemu_log_mask(LOG_GUEST_ERROR, |
961 | "gt64120: Illegal register read " | |
962 | "reg:0x03%x size:%u value:0x%0*x\n", | |
963 | saddr << 2, size, size << 1, val); | |
fde7d5bd TS |
964 | break; |
965 | } | |
966 | ||
53539655 | 967 | if (!(s->regs[GT_CPU] & 0x00001000)) { |
1931e260 | 968 | val = bswap32(val); |
53539655 | 969 | } |
1931e260 | 970 | |
05b4ff43 | 971 | return val; |
fde7d5bd TS |
972 | } |
973 | ||
fc2bf449 AK |
974 | static const MemoryRegionOps isd_mem_ops = { |
975 | .read = gt64120_readl, | |
976 | .write = gt64120_writel, | |
977 | .endianness = DEVICE_NATIVE_ENDIAN, | |
fde7d5bd TS |
978 | }; |
979 | ||
c2dd2a23 | 980 | static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
fde7d5bd TS |
981 | { |
982 | int slot; | |
983 | ||
984 | slot = (pci_dev->devfn >> 3); | |
985 | ||
986 | switch (slot) { | |
c47aee35 PMD |
987 | /* PIIX4 USB */ |
988 | case 10: | |
fde7d5bd | 989 | return 3; |
c47aee35 PMD |
990 | /* AMD 79C973 Ethernet */ |
991 | case 11: | |
d4a4d056 | 992 | return 1; |
c47aee35 PMD |
993 | /* Crystal 4281 Sound */ |
994 | case 12: | |
d4a4d056 | 995 | return 2; |
c47aee35 PMD |
996 | /* PCI slot 1 to 4 */ |
997 | case 18 ... 21: | |
fde7d5bd | 998 | return ((slot - 18) + irq_num) & 0x03; |
c47aee35 PMD |
999 | /* Unknown device, don't do any translation */ |
1000 | default: | |
fde7d5bd TS |
1001 | return irq_num; |
1002 | } | |
1003 | } | |
1004 | ||
fde7d5bd TS |
1005 | static int pci_irq_levels[4]; |
1006 | ||
c2dd2a23 | 1007 | static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) |
fde7d5bd TS |
1008 | { |
1009 | int i, pic_irq, pic_level; | |
5d4e84c8 | 1010 | qemu_irq *pic = opaque; |
fde7d5bd TS |
1011 | |
1012 | pci_irq_levels[irq_num] = level; | |
1013 | ||
1014 | /* now we change the pic irq level according to the piix irq mappings */ | |
1015 | /* XXX: optimize */ | |
1016 | pic_irq = piix4_dev->config[0x60 + irq_num]; | |
1017 | if (pic_irq < 16) { | |
c47aee35 | 1018 | /* The pic level is the logical OR of all the PCI irqs mapped to it. */ |
fde7d5bd TS |
1019 | pic_level = 0; |
1020 | for (i = 0; i < 4; i++) { | |
53539655 | 1021 | if (pic_irq == piix4_dev->config[0x60 + i]) { |
fde7d5bd | 1022 | pic_level |= pci_irq_levels[i]; |
53539655 | 1023 | } |
fde7d5bd | 1024 | } |
d537cf6c | 1025 | qemu_set_irq(pic[pic_irq], pic_level); |
fde7d5bd TS |
1026 | } |
1027 | } | |
1028 | ||
1029 | ||
43fd7bbf | 1030 | static void gt64120_reset(DeviceState *dev) |
fde7d5bd | 1031 | { |
43fd7bbf | 1032 | GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); |
fde7d5bd | 1033 | |
30b6f3a8 TS |
1034 | /* FIXME: Malta specific hw assumptions ahead */ |
1035 | ||
fde7d5bd TS |
1036 | /* CPU Configuration */ |
1037 | #ifdef TARGET_WORDS_BIGENDIAN | |
1038 | s->regs[GT_CPU] = 0x00000000; | |
1039 | #else | |
bc687ec9 | 1040 | s->regs[GT_CPU] = 0x00001000; |
fde7d5bd | 1041 | #endif |
30b6f3a8 TS |
1042 | s->regs[GT_MULTI] = 0x00000003; |
1043 | ||
1044 | /* CPU Address decode */ | |
1045 | s->regs[GT_SCS10LD] = 0x00000000; | |
1046 | s->regs[GT_SCS10HD] = 0x00000007; | |
1047 | s->regs[GT_SCS32LD] = 0x00000008; | |
1048 | s->regs[GT_SCS32HD] = 0x0000000f; | |
1049 | s->regs[GT_CS20LD] = 0x000000e0; | |
1050 | s->regs[GT_CS20HD] = 0x00000070; | |
1051 | s->regs[GT_CS3BOOTLD] = 0x000000f8; | |
1052 | s->regs[GT_CS3BOOTHD] = 0x0000007f; | |
fde7d5bd | 1053 | |
fde7d5bd TS |
1054 | s->regs[GT_PCI0IOLD] = 0x00000080; |
1055 | s->regs[GT_PCI0IOHD] = 0x0000000f; | |
1056 | s->regs[GT_PCI0M0LD] = 0x00000090; | |
1057 | s->regs[GT_PCI0M0HD] = 0x0000001f; | |
30b6f3a8 | 1058 | s->regs[GT_ISD] = 0x000000a0; |
fde7d5bd TS |
1059 | s->regs[GT_PCI0M1LD] = 0x00000790; |
1060 | s->regs[GT_PCI0M1HD] = 0x0000001f; | |
1061 | s->regs[GT_PCI1IOLD] = 0x00000100; | |
1062 | s->regs[GT_PCI1IOHD] = 0x0000000f; | |
1063 | s->regs[GT_PCI1M0LD] = 0x00000110; | |
1064 | s->regs[GT_PCI1M0HD] = 0x0000001f; | |
1065 | s->regs[GT_PCI1M1LD] = 0x00000120; | |
1066 | s->regs[GT_PCI1M1HD] = 0x0000002f; | |
30b6f3a8 TS |
1067 | |
1068 | s->regs[GT_SCS10AR] = 0x00000000; | |
1069 | s->regs[GT_SCS32AR] = 0x00000008; | |
1070 | s->regs[GT_CS20R] = 0x000000e0; | |
1071 | s->regs[GT_CS3BOOTR] = 0x000000f8; | |
1072 | ||
fde7d5bd TS |
1073 | s->regs[GT_PCI0IOREMAP] = 0x00000080; |
1074 | s->regs[GT_PCI0M0REMAP] = 0x00000090; | |
1075 | s->regs[GT_PCI0M1REMAP] = 0x00000790; | |
1076 | s->regs[GT_PCI1IOREMAP] = 0x00000100; | |
1077 | s->regs[GT_PCI1M0REMAP] = 0x00000110; | |
1078 | s->regs[GT_PCI1M1REMAP] = 0x00000120; | |
1079 | ||
1080 | /* CPU Error Report */ | |
1081 | s->regs[GT_CPUERR_ADDRLO] = 0x00000000; | |
1082 | s->regs[GT_CPUERR_ADDRHI] = 0x00000000; | |
1083 | s->regs[GT_CPUERR_DATALO] = 0xffffffff; | |
1084 | s->regs[GT_CPUERR_DATAHI] = 0xffffffff; | |
1085 | s->regs[GT_CPUERR_PARITY] = 0x000000ff; | |
1086 | ||
30b6f3a8 TS |
1087 | /* CPU Sync Barrier */ |
1088 | s->regs[GT_PCI0SYNC] = 0x00000000; | |
1089 | s->regs[GT_PCI1SYNC] = 0x00000000; | |
1090 | ||
1091 | /* SDRAM and Device Address Decode */ | |
1092 | s->regs[GT_SCS0LD] = 0x00000000; | |
1093 | s->regs[GT_SCS0HD] = 0x00000007; | |
1094 | s->regs[GT_SCS1LD] = 0x00000008; | |
1095 | s->regs[GT_SCS1HD] = 0x0000000f; | |
1096 | s->regs[GT_SCS2LD] = 0x00000010; | |
1097 | s->regs[GT_SCS2HD] = 0x00000017; | |
1098 | s->regs[GT_SCS3LD] = 0x00000018; | |
1099 | s->regs[GT_SCS3HD] = 0x0000001f; | |
1100 | s->regs[GT_CS0LD] = 0x000000c0; | |
1101 | s->regs[GT_CS0HD] = 0x000000c7; | |
1102 | s->regs[GT_CS1LD] = 0x000000c8; | |
1103 | s->regs[GT_CS1HD] = 0x000000cf; | |
1104 | s->regs[GT_CS2LD] = 0x000000d0; | |
1105 | s->regs[GT_CS2HD] = 0x000000df; | |
1106 | s->regs[GT_CS3LD] = 0x000000f0; | |
1107 | s->regs[GT_CS3HD] = 0x000000fb; | |
1108 | s->regs[GT_BOOTLD] = 0x000000fc; | |
1109 | s->regs[GT_BOOTHD] = 0x000000ff; | |
1110 | s->regs[GT_ADERR] = 0xffffffff; | |
1111 | ||
1112 | /* SDRAM Configuration */ | |
1113 | s->regs[GT_SDRAM_CFG] = 0x00000200; | |
1114 | s->regs[GT_SDRAM_OPMODE] = 0x00000000; | |
1115 | s->regs[GT_SDRAM_BM] = 0x00000007; | |
1116 | s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002; | |
1117 | ||
1118 | /* SDRAM Parameters */ | |
1119 | s->regs[GT_SDRAM_B0] = 0x00000005; | |
1120 | s->regs[GT_SDRAM_B1] = 0x00000005; | |
1121 | s->regs[GT_SDRAM_B2] = 0x00000005; | |
1122 | s->regs[GT_SDRAM_B3] = 0x00000005; | |
1123 | ||
fde7d5bd TS |
1124 | /* ECC */ |
1125 | s->regs[GT_ECC_ERRDATALO] = 0x00000000; | |
1126 | s->regs[GT_ECC_ERRDATAHI] = 0x00000000; | |
1127 | s->regs[GT_ECC_MEM] = 0x00000000; | |
1128 | s->regs[GT_ECC_CALC] = 0x00000000; | |
1129 | s->regs[GT_ECC_ERRADDR] = 0x00000000; | |
1130 | ||
30b6f3a8 TS |
1131 | /* Device Parameters */ |
1132 | s->regs[GT_DEV_B0] = 0x386fffff; | |
1133 | s->regs[GT_DEV_B1] = 0x386fffff; | |
1134 | s->regs[GT_DEV_B2] = 0x386fffff; | |
1135 | s->regs[GT_DEV_B3] = 0x386fffff; | |
1136 | s->regs[GT_DEV_BOOT] = 0x146fffff; | |
0da75eb1 | 1137 | |
30b6f3a8 TS |
1138 | /* DMA registers are all zeroed at reset */ |
1139 | ||
1140 | /* Timer/Counter */ | |
1141 | s->regs[GT_TC0] = 0xffffffff; | |
1142 | s->regs[GT_TC1] = 0x00ffffff; | |
1143 | s->regs[GT_TC2] = 0x00ffffff; | |
1144 | s->regs[GT_TC3] = 0x00ffffff; | |
1145 | s->regs[GT_TC_CONTROL] = 0x00000000; | |
1146 | ||
1147 | /* PCI Internal */ | |
fde7d5bd TS |
1148 | #ifdef TARGET_WORDS_BIGENDIAN |
1149 | s->regs[GT_PCI0_CMD] = 0x00000000; | |
fde7d5bd TS |
1150 | #else |
1151 | s->regs[GT_PCI0_CMD] = 0x00010001; | |
fde7d5bd | 1152 | #endif |
30b6f3a8 TS |
1153 | s->regs[GT_PCI0_TOR] = 0x0000070f; |
1154 | s->regs[GT_PCI0_BS_SCS10] = 0x00fff000; | |
1155 | s->regs[GT_PCI0_BS_SCS32] = 0x00fff000; | |
1156 | s->regs[GT_PCI0_BS_CS20] = 0x01fff000; | |
1157 | s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000; | |
fde7d5bd | 1158 | s->regs[GT_PCI1_IACK] = 0x00000000; |
30b6f3a8 TS |
1159 | s->regs[GT_PCI0_IACK] = 0x00000000; |
1160 | s->regs[GT_PCI0_BARE] = 0x0000000f; | |
1161 | s->regs[GT_PCI0_PREFMBR] = 0x00000040; | |
1162 | s->regs[GT_PCI0_SCS10_BAR] = 0x00000000; | |
1163 | s->regs[GT_PCI0_SCS32_BAR] = 0x01000000; | |
1164 | s->regs[GT_PCI0_CS20_BAR] = 0x1c000000; | |
1165 | s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000; | |
1166 | s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000; | |
1167 | s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000; | |
1168 | s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000; | |
1169 | #ifdef TARGET_WORDS_BIGENDIAN | |
1170 | s->regs[GT_PCI1_CMD] = 0x00000000; | |
1171 | #else | |
1172 | s->regs[GT_PCI1_CMD] = 0x00010001; | |
1173 | #endif | |
1174 | s->regs[GT_PCI1_TOR] = 0x0000070f; | |
1175 | s->regs[GT_PCI1_BS_SCS10] = 0x00fff000; | |
1176 | s->regs[GT_PCI1_BS_SCS32] = 0x00fff000; | |
1177 | s->regs[GT_PCI1_BS_CS20] = 0x01fff000; | |
1178 | s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000; | |
1179 | s->regs[GT_PCI1_BARE] = 0x0000000f; | |
1180 | s->regs[GT_PCI1_PREFMBR] = 0x00000040; | |
1181 | s->regs[GT_PCI1_SCS10_BAR] = 0x00000000; | |
1182 | s->regs[GT_PCI1_SCS32_BAR] = 0x01000000; | |
1183 | s->regs[GT_PCI1_CS20_BAR] = 0x1c000000; | |
1184 | s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000; | |
1185 | s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000; | |
1186 | s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000; | |
1187 | s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000; | |
1188 | s->regs[GT_PCI1_CFGADDR] = 0x00000000; | |
1189 | s->regs[GT_PCI1_CFGDATA] = 0x00000000; | |
1190 | s->regs[GT_PCI0_CFGADDR] = 0x00000000; | |
30b6f3a8 TS |
1191 | |
1192 | /* Interrupt registers are all zeroed at reset */ | |
fde7d5bd | 1193 | |
a0a8793e | 1194 | gt64120_isd_mapping(s); |
9414cc6f | 1195 | gt64120_pci_mapping(s); |
fde7d5bd TS |
1196 | } |
1197 | ||
c2dd2a23 AJ |
1198 | PCIBus *gt64120_register(qemu_irq *pic) |
1199 | { | |
c2dd2a23 | 1200 | GT64120State *d; |
8d43d7e5 | 1201 | PCIHostState *phb; |
c2dd2a23 AJ |
1202 | DeviceState *dev; |
1203 | ||
8d43d7e5 | 1204 | dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE); |
8d43d7e5 | 1205 | d = GT64120_PCI_HOST_BRIDGE(dev); |
8558d942 | 1206 | phb = PCI_HOST_BRIDGE(dev); |
8110b2bf | 1207 | memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB); |
f720f203 | 1208 | address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem"); |
1115ff6d DG |
1209 | phb->bus = pci_register_root_bus(dev, "pci", |
1210 | gt64120_pci_set_irq, gt64120_pci_map_irq, | |
1211 | pic, | |
1212 | &d->pci0_mem, | |
1213 | get_system_io(), | |
1214 | PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); | |
a8c1a753 | 1215 | qdev_init_nofail(dev); |
b61104b2 PMD |
1216 | memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, |
1217 | "isd-mem", 0x1000); | |
c2dd2a23 | 1218 | |
8d43d7e5 AF |
1219 | pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); |
1220 | return phb->bus; | |
c2dd2a23 AJ |
1221 | } |
1222 | ||
b429d363 | 1223 | static void gt64120_pci_realize(PCIDevice *d, Error **errp) |
c2dd2a23 | 1224 | { |
0f78cf0c | 1225 | /* FIXME: Malta specific hw assumptions ahead */ |
c2dd2a23 AJ |
1226 | pci_set_word(d->config + PCI_COMMAND, 0); |
1227 | pci_set_word(d->config + PCI_STATUS, | |
1228 | PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); | |
c2dd2a23 | 1229 | pci_config_set_prog_interface(d->config, 0); |
c2dd2a23 AJ |
1230 | pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); |
1231 | pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); | |
1232 | pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); | |
1233 | pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); | |
1234 | pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); | |
1235 | pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); | |
1236 | pci_set_byte(d->config + 0x3d, 0x01); | |
c2dd2a23 | 1237 | } |
a0a8793e | 1238 | |
40021f08 AL |
1239 | static void gt64120_pci_class_init(ObjectClass *klass, void *data) |
1240 | { | |
1241 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 1242 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 1243 | |
b429d363 | 1244 | k->realize = gt64120_pci_realize; |
40021f08 AL |
1245 | k->vendor_id = PCI_VENDOR_ID_MARVELL; |
1246 | k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; | |
1247 | k->revision = 0x10; | |
1248 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
1249 | /* |
1250 | * PCI-facing part of the host bridge, not usable without the | |
1251 | * host-facing part, which can't be device_add'ed, yet. | |
1252 | */ | |
e90f2a8c | 1253 | dc->user_creatable = false; |
40021f08 AL |
1254 | } |
1255 | ||
4240abff | 1256 | static const TypeInfo gt64120_pci_info = { |
39bffca2 AL |
1257 | .name = "gt64120_pci", |
1258 | .parent = TYPE_PCI_DEVICE, | |
1259 | .instance_size = sizeof(PCIDevice), | |
1260 | .class_init = gt64120_pci_class_init, | |
fd3b02c8 EH |
1261 | .interfaces = (InterfaceInfo[]) { |
1262 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
1263 | { }, | |
1264 | }, | |
c2dd2a23 | 1265 | }; |
1823082c | 1266 | |
999e12bb AL |
1267 | static void gt64120_class_init(ObjectClass *klass, void *data) |
1268 | { | |
427e1750 | 1269 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1270 | |
d1268699 | 1271 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
43fd7bbf | 1272 | dc->reset = gt64120_reset; |
427e1750 | 1273 | dc->vmsd = &vmstate_gt64120; |
999e12bb AL |
1274 | } |
1275 | ||
4240abff | 1276 | static const TypeInfo gt64120_info = { |
8d43d7e5 | 1277 | .name = TYPE_GT64120_PCI_HOST_BRIDGE, |
8558d942 | 1278 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 AL |
1279 | .instance_size = sizeof(GT64120State), |
1280 | .class_init = gt64120_class_init, | |
999e12bb AL |
1281 | }; |
1282 | ||
83f7d43a | 1283 | static void gt64120_pci_register_types(void) |
c2dd2a23 | 1284 | { |
39bffca2 AL |
1285 | type_register_static(>64120_info); |
1286 | type_register_static(>64120_pci_info); | |
fde7d5bd | 1287 | } |
c2dd2a23 | 1288 | |
83f7d43a | 1289 | type_init(gt64120_pci_register_types) |