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Commit | Line | Data |
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fde7d5bd TS |
1 | /* |
2 | * QEMU GT64120 PCI host | |
3 | * | |
4de9b249 | 4 | * Copyright (c) 2006,2007 Aurelien Jarno |
5fafdf24 | 5 | * |
fde7d5bd TS |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
c684822a | 25 | #include "qemu/osdep.h" |
3e80f690 | 26 | #include "qapi/error.h" |
8110b2bf | 27 | #include "qemu/units.h" |
641ca2bf | 28 | #include "qemu/log.h" |
0d09e41a | 29 | #include "hw/mips/mips.h" |
83c9f4ca PB |
30 | #include "hw/pci/pci.h" |
31 | #include "hw/pci/pci_host.h" | |
e29f2379 | 32 | #include "hw/southbridge/piix.h" |
d6454270 | 33 | #include "migration/vmstate.h" |
852c27e2 | 34 | #include "hw/intc/i8259.h" |
64552b6b | 35 | #include "hw/irq.h" |
022c62cb | 36 | #include "exec/address-spaces.h" |
ab6bff42 | 37 | #include "trace.h" |
db1015e9 | 38 | #include "qom/object.h" |
05b4ff43 | 39 | |
91ce82b2 | 40 | #define GT_REGS (0x1000 >> 2) |
fde7d5bd TS |
41 | |
42 | /* CPU Configuration */ | |
91ce82b2 PMD |
43 | #define GT_CPU (0x000 >> 2) |
44 | #define GT_MULTI (0x120 >> 2) | |
fde7d5bd TS |
45 | |
46 | /* CPU Address Decode */ | |
91ce82b2 PMD |
47 | #define GT_SCS10LD (0x008 >> 2) |
48 | #define GT_SCS10HD (0x010 >> 2) | |
49 | #define GT_SCS32LD (0x018 >> 2) | |
50 | #define GT_SCS32HD (0x020 >> 2) | |
51 | #define GT_CS20LD (0x028 >> 2) | |
52 | #define GT_CS20HD (0x030 >> 2) | |
53 | #define GT_CS3BOOTLD (0x038 >> 2) | |
54 | #define GT_CS3BOOTHD (0x040 >> 2) | |
55 | #define GT_PCI0IOLD (0x048 >> 2) | |
56 | #define GT_PCI0IOHD (0x050 >> 2) | |
57 | #define GT_PCI0M0LD (0x058 >> 2) | |
58 | #define GT_PCI0M0HD (0x060 >> 2) | |
59 | #define GT_PCI0M1LD (0x080 >> 2) | |
60 | #define GT_PCI0M1HD (0x088 >> 2) | |
61 | #define GT_PCI1IOLD (0x090 >> 2) | |
62 | #define GT_PCI1IOHD (0x098 >> 2) | |
63 | #define GT_PCI1M0LD (0x0a0 >> 2) | |
64 | #define GT_PCI1M0HD (0x0a8 >> 2) | |
65 | #define GT_PCI1M1LD (0x0b0 >> 2) | |
66 | #define GT_PCI1M1HD (0x0b8 >> 2) | |
67 | #define GT_ISD (0x068 >> 2) | |
68 | ||
69 | #define GT_SCS10AR (0x0d0 >> 2) | |
70 | #define GT_SCS32AR (0x0d8 >> 2) | |
71 | #define GT_CS20R (0x0e0 >> 2) | |
72 | #define GT_CS3BOOTR (0x0e8 >> 2) | |
73 | ||
74 | #define GT_PCI0IOREMAP (0x0f0 >> 2) | |
75 | #define GT_PCI0M0REMAP (0x0f8 >> 2) | |
76 | #define GT_PCI0M1REMAP (0x100 >> 2) | |
77 | #define GT_PCI1IOREMAP (0x108 >> 2) | |
78 | #define GT_PCI1M0REMAP (0x110 >> 2) | |
79 | #define GT_PCI1M1REMAP (0x118 >> 2) | |
fde7d5bd TS |
80 | |
81 | /* CPU Error Report */ | |
91ce82b2 PMD |
82 | #define GT_CPUERR_ADDRLO (0x070 >> 2) |
83 | #define GT_CPUERR_ADDRHI (0x078 >> 2) | |
84 | #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ | |
85 | #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ | |
86 | #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ | |
fde7d5bd TS |
87 | |
88 | /* CPU Sync Barrier */ | |
91ce82b2 PMD |
89 | #define GT_PCI0SYNC (0x0c0 >> 2) |
90 | #define GT_PCI1SYNC (0x0c8 >> 2) | |
fde7d5bd TS |
91 | |
92 | /* SDRAM and Device Address Decode */ | |
91ce82b2 PMD |
93 | #define GT_SCS0LD (0x400 >> 2) |
94 | #define GT_SCS0HD (0x404 >> 2) | |
95 | #define GT_SCS1LD (0x408 >> 2) | |
96 | #define GT_SCS1HD (0x40c >> 2) | |
97 | #define GT_SCS2LD (0x410 >> 2) | |
98 | #define GT_SCS2HD (0x414 >> 2) | |
99 | #define GT_SCS3LD (0x418 >> 2) | |
100 | #define GT_SCS3HD (0x41c >> 2) | |
101 | #define GT_CS0LD (0x420 >> 2) | |
102 | #define GT_CS0HD (0x424 >> 2) | |
103 | #define GT_CS1LD (0x428 >> 2) | |
104 | #define GT_CS1HD (0x42c >> 2) | |
105 | #define GT_CS2LD (0x430 >> 2) | |
106 | #define GT_CS2HD (0x434 >> 2) | |
107 | #define GT_CS3LD (0x438 >> 2) | |
108 | #define GT_CS3HD (0x43c >> 2) | |
109 | #define GT_BOOTLD (0x440 >> 2) | |
110 | #define GT_BOOTHD (0x444 >> 2) | |
111 | #define GT_ADERR (0x470 >> 2) | |
fde7d5bd TS |
112 | |
113 | /* SDRAM Configuration */ | |
91ce82b2 PMD |
114 | #define GT_SDRAM_CFG (0x448 >> 2) |
115 | #define GT_SDRAM_OPMODE (0x474 >> 2) | |
116 | #define GT_SDRAM_BM (0x478 >> 2) | |
117 | #define GT_SDRAM_ADDRDECODE (0x47c >> 2) | |
fde7d5bd TS |
118 | |
119 | /* SDRAM Parameters */ | |
91ce82b2 PMD |
120 | #define GT_SDRAM_B0 (0x44c >> 2) |
121 | #define GT_SDRAM_B1 (0x450 >> 2) | |
122 | #define GT_SDRAM_B2 (0x454 >> 2) | |
123 | #define GT_SDRAM_B3 (0x458 >> 2) | |
fde7d5bd TS |
124 | |
125 | /* Device Parameters */ | |
91ce82b2 PMD |
126 | #define GT_DEV_B0 (0x45c >> 2) |
127 | #define GT_DEV_B1 (0x460 >> 2) | |
128 | #define GT_DEV_B2 (0x464 >> 2) | |
129 | #define GT_DEV_B3 (0x468 >> 2) | |
130 | #define GT_DEV_BOOT (0x46c >> 2) | |
fde7d5bd TS |
131 | |
132 | /* ECC */ | |
91ce82b2 PMD |
133 | #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ |
134 | #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ | |
135 | #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ | |
136 | #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ | |
137 | #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ | |
fde7d5bd TS |
138 | |
139 | /* DMA Record */ | |
91ce82b2 PMD |
140 | #define GT_DMA0_CNT (0x800 >> 2) |
141 | #define GT_DMA1_CNT (0x804 >> 2) | |
142 | #define GT_DMA2_CNT (0x808 >> 2) | |
143 | #define GT_DMA3_CNT (0x80c >> 2) | |
144 | #define GT_DMA0_SA (0x810 >> 2) | |
145 | #define GT_DMA1_SA (0x814 >> 2) | |
146 | #define GT_DMA2_SA (0x818 >> 2) | |
147 | #define GT_DMA3_SA (0x81c >> 2) | |
148 | #define GT_DMA0_DA (0x820 >> 2) | |
149 | #define GT_DMA1_DA (0x824 >> 2) | |
150 | #define GT_DMA2_DA (0x828 >> 2) | |
151 | #define GT_DMA3_DA (0x82c >> 2) | |
152 | #define GT_DMA0_NEXT (0x830 >> 2) | |
153 | #define GT_DMA1_NEXT (0x834 >> 2) | |
154 | #define GT_DMA2_NEXT (0x838 >> 2) | |
155 | #define GT_DMA3_NEXT (0x83c >> 2) | |
156 | #define GT_DMA0_CUR (0x870 >> 2) | |
157 | #define GT_DMA1_CUR (0x874 >> 2) | |
158 | #define GT_DMA2_CUR (0x878 >> 2) | |
159 | #define GT_DMA3_CUR (0x87c >> 2) | |
fde7d5bd TS |
160 | |
161 | /* DMA Channel Control */ | |
91ce82b2 PMD |
162 | #define GT_DMA0_CTRL (0x840 >> 2) |
163 | #define GT_DMA1_CTRL (0x844 >> 2) | |
164 | #define GT_DMA2_CTRL (0x848 >> 2) | |
165 | #define GT_DMA3_CTRL (0x84c >> 2) | |
fde7d5bd TS |
166 | |
167 | /* DMA Arbiter */ | |
91ce82b2 | 168 | #define GT_DMA_ARB (0x860 >> 2) |
fde7d5bd TS |
169 | |
170 | /* Timer/Counter */ | |
91ce82b2 PMD |
171 | #define GT_TC0 (0x850 >> 2) |
172 | #define GT_TC1 (0x854 >> 2) | |
173 | #define GT_TC2 (0x858 >> 2) | |
174 | #define GT_TC3 (0x85c >> 2) | |
175 | #define GT_TC_CONTROL (0x864 >> 2) | |
fde7d5bd TS |
176 | |
177 | /* PCI Internal */ | |
91ce82b2 PMD |
178 | #define GT_PCI0_CMD (0xc00 >> 2) |
179 | #define GT_PCI0_TOR (0xc04 >> 2) | |
180 | #define GT_PCI0_BS_SCS10 (0xc08 >> 2) | |
181 | #define GT_PCI0_BS_SCS32 (0xc0c >> 2) | |
182 | #define GT_PCI0_BS_CS20 (0xc10 >> 2) | |
183 | #define GT_PCI0_BS_CS3BT (0xc14 >> 2) | |
184 | #define GT_PCI1_IACK (0xc30 >> 2) | |
185 | #define GT_PCI0_IACK (0xc34 >> 2) | |
186 | #define GT_PCI0_BARE (0xc3c >> 2) | |
187 | #define GT_PCI0_PREFMBR (0xc40 >> 2) | |
188 | #define GT_PCI0_SCS10_BAR (0xc48 >> 2) | |
189 | #define GT_PCI0_SCS32_BAR (0xc4c >> 2) | |
190 | #define GT_PCI0_CS20_BAR (0xc50 >> 2) | |
191 | #define GT_PCI0_CS3BT_BAR (0xc54 >> 2) | |
192 | #define GT_PCI0_SSCS10_BAR (0xc58 >> 2) | |
193 | #define GT_PCI0_SSCS32_BAR (0xc5c >> 2) | |
194 | #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) | |
195 | #define GT_PCI1_CMD (0xc80 >> 2) | |
196 | #define GT_PCI1_TOR (0xc84 >> 2) | |
197 | #define GT_PCI1_BS_SCS10 (0xc88 >> 2) | |
198 | #define GT_PCI1_BS_SCS32 (0xc8c >> 2) | |
199 | #define GT_PCI1_BS_CS20 (0xc90 >> 2) | |
200 | #define GT_PCI1_BS_CS3BT (0xc94 >> 2) | |
201 | #define GT_PCI1_BARE (0xcbc >> 2) | |
202 | #define GT_PCI1_PREFMBR (0xcc0 >> 2) | |
203 | #define GT_PCI1_SCS10_BAR (0xcc8 >> 2) | |
204 | #define GT_PCI1_SCS32_BAR (0xccc >> 2) | |
205 | #define GT_PCI1_CS20_BAR (0xcd0 >> 2) | |
206 | #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) | |
207 | #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) | |
208 | #define GT_PCI1_SSCS32_BAR (0xcdc >> 2) | |
209 | #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) | |
210 | #define GT_PCI1_CFGADDR (0xcf0 >> 2) | |
211 | #define GT_PCI1_CFGDATA (0xcf4 >> 2) | |
212 | #define GT_PCI0_CFGADDR (0xcf8 >> 2) | |
213 | #define GT_PCI0_CFGDATA (0xcfc >> 2) | |
fde7d5bd TS |
214 | |
215 | /* Interrupts */ | |
91ce82b2 PMD |
216 | #define GT_INTRCAUSE (0xc18 >> 2) |
217 | #define GT_INTRMASK (0xc1c >> 2) | |
218 | #define GT_PCI0_ICMASK (0xc24 >> 2) | |
219 | #define GT_PCI0_SERR0MASK (0xc28 >> 2) | |
220 | #define GT_CPU_INTSEL (0xc70 >> 2) | |
221 | #define GT_PCI0_INTSEL (0xc74 >> 2) | |
222 | #define GT_HINTRCAUSE (0xc98 >> 2) | |
223 | #define GT_HINTRMASK (0xc9c >> 2) | |
224 | #define GT_PCI0_HICMASK (0xca4 >> 2) | |
225 | #define GT_PCI1_SERR1MASK (0xca8 >> 2) | |
fde7d5bd | 226 | |
a0a8793e | 227 | #define PCI_MAPPING_ENTRY(regname) \ |
a8170e5e AK |
228 | hwaddr regname ##_start; \ |
229 | hwaddr regname ##_length; \ | |
fc2bf449 | 230 | MemoryRegion regname ##_mem |
a0a8793e | 231 | |
8d43d7e5 AF |
232 | #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120" |
233 | ||
db1015e9 | 234 | typedef struct GT64120State GT64120State; |
8d43d7e5 AF |
235 | #define GT64120_PCI_HOST_BRIDGE(obj) \ |
236 | OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE) | |
237 | ||
db1015e9 | 238 | struct GT64120State { |
67c332fd | 239 | PCIHostState parent_obj; |
8d43d7e5 | 240 | |
fde7d5bd | 241 | uint32_t regs[GT_REGS]; |
a0a8793e | 242 | PCI_MAPPING_ENTRY(PCI0IO); |
f720f203 HP |
243 | PCI_MAPPING_ENTRY(PCI0M0); |
244 | PCI_MAPPING_ENTRY(PCI0M1); | |
a0a8793e | 245 | PCI_MAPPING_ENTRY(ISD); |
f720f203 HP |
246 | MemoryRegion pci0_mem; |
247 | AddressSpace pci0_mem_as; | |
db1015e9 | 248 | }; |
fde7d5bd | 249 | |
a0a8793e | 250 | /* Adjust range to avoid touching space which isn't mappable via PCI */ |
c47aee35 PMD |
251 | /* |
252 | * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 | |
253 | * 0x1fc00000 - 0x1fd00000 | |
254 | */ | |
255 | static void check_reserved_space(hwaddr *start, hwaddr *length) | |
a0a8793e | 256 | { |
a8170e5e AK |
257 | hwaddr begin = *start; |
258 | hwaddr end = *start + *length; | |
a0a8793e | 259 | |
53539655 | 260 | if (end >= 0x1e000000LL && end < 0x1f100000LL) { |
a0a8793e | 261 | end = 0x1e000000LL; |
53539655 PMD |
262 | } |
263 | if (begin >= 0x1e000000LL && begin < 0x1f100000LL) { | |
a0a8793e | 264 | begin = 0x1f100000LL; |
53539655 PMD |
265 | } |
266 | if (end >= 0x1fc00000LL && end < 0x1fd00000LL) { | |
a0a8793e | 267 | end = 0x1fc00000LL; |
53539655 PMD |
268 | } |
269 | if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) { | |
a0a8793e | 270 | begin = 0x1fd00000LL; |
53539655 | 271 | } |
a0a8793e | 272 | /* XXX: This is broken when a reserved range splits the requested range */ |
53539655 | 273 | if (end >= 0x1f100000LL && begin < 0x1e000000LL) { |
a0a8793e | 274 | end = 0x1e000000LL; |
53539655 PMD |
275 | } |
276 | if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) { | |
a0a8793e | 277 | end = 0x1fc00000LL; |
53539655 | 278 | } |
a0a8793e TS |
279 | |
280 | *start = begin; | |
281 | *length = end - begin; | |
282 | } | |
283 | ||
284 | static void gt64120_isd_mapping(GT64120State *s) | |
285 | { | |
63fc7375 PB |
286 | /* Bits 14:0 of ISD map to bits 35:21 of the start address. */ |
287 | hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull; | |
a8170e5e | 288 | hwaddr length = 0x1000; |
a0a8793e | 289 | |
fc2bf449 AK |
290 | if (s->ISD_length) { |
291 | memory_region_del_subregion(get_system_memory(), &s->ISD_mem); | |
292 | } | |
a0a8793e TS |
293 | check_reserved_space(&start, &length); |
294 | length = 0x1000; | |
295 | /* Map new address */ | |
ab6bff42 | 296 | trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start); |
a0a8793e TS |
297 | s->ISD_start = start; |
298 | s->ISD_length = length; | |
fc2bf449 | 299 | memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem); |
a0a8793e TS |
300 | } |
301 | ||
9414cc6f | 302 | static void gt64120_pci_mapping(GT64120State *s) |
2a1086d9 | 303 | { |
f720f203 HP |
304 | /* Update PCI0IO mapping */ |
305 | if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) { | |
306 | /* Unmap old IO address */ | |
307 | if (s->PCI0IO_length) { | |
308 | memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem); | |
309 | object_unparent(OBJECT(&s->PCI0IO_mem)); | |
310 | } | |
311 | /* Map new IO address */ | |
312 | s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; | |
313 | s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - | |
314 | (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; | |
315 | if (s->PCI0IO_length) { | |
316 | memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io", | |
317 | get_system_io(), 0, s->PCI0IO_length); | |
318 | memory_region_add_subregion(get_system_memory(), s->PCI0IO_start, | |
319 | &s->PCI0IO_mem); | |
320 | } | |
321 | } | |
322 | ||
323 | /* Update PCI0M0 mapping */ | |
324 | if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) { | |
325 | /* Unmap old MEM address */ | |
326 | if (s->PCI0M0_length) { | |
327 | memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem); | |
328 | object_unparent(OBJECT(&s->PCI0M0_mem)); | |
329 | } | |
330 | /* Map new mem address */ | |
331 | s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21; | |
332 | s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) - | |
333 | (s->regs[GT_PCI0M0LD] & 0x7f)) << 21; | |
334 | if (s->PCI0M0_length) { | |
335 | memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0", | |
336 | &s->pci0_mem, s->PCI0M0_start, | |
337 | s->PCI0M0_length); | |
338 | memory_region_add_subregion(get_system_memory(), s->PCI0M0_start, | |
339 | &s->PCI0M0_mem); | |
340 | } | |
341 | } | |
342 | ||
343 | /* Update PCI0M1 mapping */ | |
344 | if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) { | |
345 | /* Unmap old MEM address */ | |
346 | if (s->PCI0M1_length) { | |
347 | memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem); | |
348 | object_unparent(OBJECT(&s->PCI0M1_mem)); | |
349 | } | |
350 | /* Map new mem address */ | |
351 | s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21; | |
352 | s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) - | |
353 | (s->regs[GT_PCI0M1LD] & 0x7f)) << 21; | |
354 | if (s->PCI0M1_length) { | |
355 | memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1", | |
356 | &s->pci0_mem, s->PCI0M1_start, | |
357 | s->PCI0M1_length); | |
358 | memory_region_add_subregion(get_system_memory(), s->PCI0M1_start, | |
359 | &s->PCI0M1_mem); | |
360 | } | |
9414cc6f | 361 | } |
2a1086d9 TS |
362 | } |
363 | ||
427e1750 SL |
364 | static int gt64120_post_load(void *opaque, int version_id) |
365 | { | |
366 | GT64120State *s = opaque; | |
367 | ||
368 | gt64120_isd_mapping(s); | |
369 | gt64120_pci_mapping(s); | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | static const VMStateDescription vmstate_gt64120 = { | |
375 | .name = "gt64120", | |
376 | .version_id = 1, | |
377 | .minimum_version_id = 1, | |
378 | .post_load = gt64120_post_load, | |
379 | .fields = (VMStateField[]) { | |
380 | VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS), | |
381 | VMSTATE_END_OF_LIST() | |
382 | } | |
383 | }; | |
384 | ||
b61104b2 PMD |
385 | static void gt64120_writel(void *opaque, hwaddr addr, |
386 | uint64_t val, unsigned size) | |
fde7d5bd TS |
387 | { |
388 | GT64120State *s = opaque; | |
67c332fd | 389 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
fde7d5bd TS |
390 | uint32_t saddr; |
391 | ||
53539655 | 392 | if (!(s->regs[GT_CPU] & 0x00001000)) { |
1931e260 | 393 | val = bswap32(val); |
53539655 | 394 | } |
0da75eb1 | 395 | |
fde7d5bd TS |
396 | saddr = (addr & 0xfff) >> 2; |
397 | switch (saddr) { | |
0da75eb1 TS |
398 | |
399 | /* CPU Configuration */ | |
fde7d5bd TS |
400 | case GT_CPU: |
401 | s->regs[GT_CPU] = val; | |
fde7d5bd TS |
402 | break; |
403 | case GT_MULTI: | |
7d37435b | 404 | /* Read-only register as only one GT64xxx is present on the CPU bus */ |
fde7d5bd TS |
405 | break; |
406 | ||
407 | /* CPU Address Decode */ | |
408 | case GT_PCI0IOLD: | |
409 | s->regs[GT_PCI0IOLD] = val & 0x00007fff; | |
410 | s->regs[GT_PCI0IOREMAP] = val & 0x000007ff; | |
9414cc6f | 411 | gt64120_pci_mapping(s); |
fde7d5bd TS |
412 | break; |
413 | case GT_PCI0M0LD: | |
414 | s->regs[GT_PCI0M0LD] = val & 0x00007fff; | |
415 | s->regs[GT_PCI0M0REMAP] = val & 0x000007ff; | |
f720f203 | 416 | gt64120_pci_mapping(s); |
fde7d5bd TS |
417 | break; |
418 | case GT_PCI0M1LD: | |
419 | s->regs[GT_PCI0M1LD] = val & 0x00007fff; | |
420 | s->regs[GT_PCI0M1REMAP] = val & 0x000007ff; | |
f720f203 | 421 | gt64120_pci_mapping(s); |
fde7d5bd TS |
422 | break; |
423 | case GT_PCI1IOLD: | |
424 | s->regs[GT_PCI1IOLD] = val & 0x00007fff; | |
425 | s->regs[GT_PCI1IOREMAP] = val & 0x000007ff; | |
fde7d5bd TS |
426 | break; |
427 | case GT_PCI1M0LD: | |
428 | s->regs[GT_PCI1M0LD] = val & 0x00007fff; | |
429 | s->regs[GT_PCI1M0REMAP] = val & 0x000007ff; | |
fde7d5bd TS |
430 | break; |
431 | case GT_PCI1M1LD: | |
432 | s->regs[GT_PCI1M1LD] = val & 0x00007fff; | |
433 | s->regs[GT_PCI1M1REMAP] = val & 0x000007ff; | |
fde7d5bd | 434 | break; |
f720f203 HP |
435 | case GT_PCI0M0HD: |
436 | case GT_PCI0M1HD: | |
fde7d5bd | 437 | case GT_PCI0IOHD: |
bb433bef TS |
438 | s->regs[saddr] = val & 0x0000007f; |
439 | gt64120_pci_mapping(s); | |
440 | break; | |
fde7d5bd TS |
441 | case GT_PCI1IOHD: |
442 | case GT_PCI1M0HD: | |
443 | case GT_PCI1M1HD: | |
444 | s->regs[saddr] = val & 0x0000007f; | |
fde7d5bd | 445 | break; |
a0a8793e TS |
446 | case GT_ISD: |
447 | s->regs[saddr] = val & 0x00007fff; | |
448 | gt64120_isd_mapping(s); | |
449 | break; | |
450 | ||
fde7d5bd TS |
451 | case GT_PCI0IOREMAP: |
452 | case GT_PCI0M0REMAP: | |
453 | case GT_PCI0M1REMAP: | |
454 | case GT_PCI1IOREMAP: | |
455 | case GT_PCI1M0REMAP: | |
456 | case GT_PCI1M1REMAP: | |
457 | s->regs[saddr] = val & 0x000007ff; | |
fde7d5bd TS |
458 | break; |
459 | ||
460 | /* CPU Error Report */ | |
461 | case GT_CPUERR_ADDRLO: | |
462 | case GT_CPUERR_ADDRHI: | |
463 | case GT_CPUERR_DATALO: | |
464 | case GT_CPUERR_DATAHI: | |
465 | case GT_CPUERR_PARITY: | |
7d37435b | 466 | /* Read-only registers, do nothing */ |
641ca2bf PMD |
467 | qemu_log_mask(LOG_GUEST_ERROR, |
468 | "gt64120: Read-only register write " | |
469 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
470 | saddr << 2, size, size << 1, val); | |
0da75eb1 TS |
471 | break; |
472 | ||
473 | /* CPU Sync Barrier */ | |
474 | case GT_PCI0SYNC: | |
475 | case GT_PCI1SYNC: | |
7d37435b | 476 | /* Read-only registers, do nothing */ |
641ca2bf PMD |
477 | qemu_log_mask(LOG_GUEST_ERROR, |
478 | "gt64120: Read-only register write " | |
479 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
480 | saddr << 2, size, size << 1, val); | |
fde7d5bd TS |
481 | break; |
482 | ||
05b4ff43 TS |
483 | /* SDRAM and Device Address Decode */ |
484 | case GT_SCS0LD: | |
485 | case GT_SCS0HD: | |
486 | case GT_SCS1LD: | |
487 | case GT_SCS1HD: | |
488 | case GT_SCS2LD: | |
489 | case GT_SCS2HD: | |
490 | case GT_SCS3LD: | |
491 | case GT_SCS3HD: | |
492 | case GT_CS0LD: | |
493 | case GT_CS0HD: | |
494 | case GT_CS1LD: | |
495 | case GT_CS1HD: | |
496 | case GT_CS2LD: | |
497 | case GT_CS2HD: | |
498 | case GT_CS3LD: | |
499 | case GT_CS3HD: | |
500 | case GT_BOOTLD: | |
501 | case GT_BOOTHD: | |
502 | case GT_ADERR: | |
503 | /* SDRAM Configuration */ | |
504 | case GT_SDRAM_CFG: | |
505 | case GT_SDRAM_OPMODE: | |
506 | case GT_SDRAM_BM: | |
507 | case GT_SDRAM_ADDRDECODE: | |
508 | /* Accept and ignore SDRAM interleave configuration */ | |
509 | s->regs[saddr] = val; | |
510 | break; | |
511 | ||
512 | /* Device Parameters */ | |
513 | case GT_DEV_B0: | |
514 | case GT_DEV_B1: | |
515 | case GT_DEV_B2: | |
516 | case GT_DEV_B3: | |
517 | case GT_DEV_BOOT: | |
518 | /* Not implemented */ | |
641ca2bf PMD |
519 | qemu_log_mask(LOG_UNIMP, |
520 | "gt64120: Unimplemented device register write " | |
521 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
522 | saddr << 2, size, size << 1, val); | |
05b4ff43 TS |
523 | break; |
524 | ||
fde7d5bd TS |
525 | /* ECC */ |
526 | case GT_ECC_ERRDATALO: | |
527 | case GT_ECC_ERRDATAHI: | |
528 | case GT_ECC_MEM: | |
529 | case GT_ECC_CALC: | |
530 | case GT_ECC_ERRADDR: | |
0da75eb1 | 531 | /* Read-only registers, do nothing */ |
641ca2bf PMD |
532 | qemu_log_mask(LOG_GUEST_ERROR, |
533 | "gt64120: Read-only register write " | |
534 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
535 | saddr << 2, size, size << 1, val); | |
fde7d5bd TS |
536 | break; |
537 | ||
05b4ff43 TS |
538 | /* DMA Record */ |
539 | case GT_DMA0_CNT: | |
540 | case GT_DMA1_CNT: | |
541 | case GT_DMA2_CNT: | |
542 | case GT_DMA3_CNT: | |
543 | case GT_DMA0_SA: | |
544 | case GT_DMA1_SA: | |
545 | case GT_DMA2_SA: | |
546 | case GT_DMA3_SA: | |
547 | case GT_DMA0_DA: | |
548 | case GT_DMA1_DA: | |
549 | case GT_DMA2_DA: | |
550 | case GT_DMA3_DA: | |
551 | case GT_DMA0_NEXT: | |
552 | case GT_DMA1_NEXT: | |
553 | case GT_DMA2_NEXT: | |
554 | case GT_DMA3_NEXT: | |
555 | case GT_DMA0_CUR: | |
556 | case GT_DMA1_CUR: | |
557 | case GT_DMA2_CUR: | |
558 | case GT_DMA3_CUR: | |
05b4ff43 TS |
559 | |
560 | /* DMA Channel Control */ | |
561 | case GT_DMA0_CTRL: | |
562 | case GT_DMA1_CTRL: | |
563 | case GT_DMA2_CTRL: | |
564 | case GT_DMA3_CTRL: | |
05b4ff43 TS |
565 | |
566 | /* DMA Arbiter */ | |
567 | case GT_DMA_ARB: | |
568 | /* Not implemented */ | |
641ca2bf PMD |
569 | qemu_log_mask(LOG_UNIMP, |
570 | "gt64120: Unimplemented DMA register write " | |
571 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
572 | saddr << 2, size, size << 1, val); | |
05b4ff43 TS |
573 | break; |
574 | ||
575 | /* Timer/Counter */ | |
576 | case GT_TC0: | |
577 | case GT_TC1: | |
578 | case GT_TC2: | |
579 | case GT_TC3: | |
580 | case GT_TC_CONTROL: | |
581 | /* Not implemented */ | |
641ca2bf PMD |
582 | qemu_log_mask(LOG_UNIMP, |
583 | "gt64120: Unimplemented timer register write " | |
584 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
585 | saddr << 2, size, size << 1, val); | |
05b4ff43 TS |
586 | break; |
587 | ||
fde7d5bd TS |
588 | /* PCI Internal */ |
589 | case GT_PCI0_CMD: | |
590 | case GT_PCI1_CMD: | |
591 | s->regs[saddr] = val & 0x0401fc0f; | |
592 | break; | |
05b4ff43 TS |
593 | case GT_PCI0_TOR: |
594 | case GT_PCI0_BS_SCS10: | |
595 | case GT_PCI0_BS_SCS32: | |
596 | case GT_PCI0_BS_CS20: | |
597 | case GT_PCI0_BS_CS3BT: | |
598 | case GT_PCI1_IACK: | |
599 | case GT_PCI0_IACK: | |
600 | case GT_PCI0_BARE: | |
601 | case GT_PCI0_PREFMBR: | |
602 | case GT_PCI0_SCS10_BAR: | |
603 | case GT_PCI0_SCS32_BAR: | |
604 | case GT_PCI0_CS20_BAR: | |
605 | case GT_PCI0_CS3BT_BAR: | |
606 | case GT_PCI0_SSCS10_BAR: | |
607 | case GT_PCI0_SSCS32_BAR: | |
608 | case GT_PCI0_SCS3BT_BAR: | |
609 | case GT_PCI1_TOR: | |
610 | case GT_PCI1_BS_SCS10: | |
611 | case GT_PCI1_BS_SCS32: | |
612 | case GT_PCI1_BS_CS20: | |
613 | case GT_PCI1_BS_CS3BT: | |
614 | case GT_PCI1_BARE: | |
615 | case GT_PCI1_PREFMBR: | |
616 | case GT_PCI1_SCS10_BAR: | |
617 | case GT_PCI1_SCS32_BAR: | |
618 | case GT_PCI1_CS20_BAR: | |
619 | case GT_PCI1_CS3BT_BAR: | |
620 | case GT_PCI1_SSCS10_BAR: | |
621 | case GT_PCI1_SSCS32_BAR: | |
622 | case GT_PCI1_SCS3BT_BAR: | |
623 | case GT_PCI1_CFGADDR: | |
624 | case GT_PCI1_CFGDATA: | |
625 | /* not implemented */ | |
641ca2bf PMD |
626 | qemu_log_mask(LOG_UNIMP, |
627 | "gt64120: Unimplemented timer register write " | |
628 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
629 | saddr << 2, size, size << 1, val); | |
05b4ff43 | 630 | break; |
fde7d5bd | 631 | case GT_PCI0_CFGADDR: |
67c332fd | 632 | phb->config_reg = val & 0x80fffffc; |
fde7d5bd TS |
633 | break; |
634 | case GT_PCI0_CFGDATA: | |
67c332fd | 635 | if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { |
c6c99c3f | 636 | val = bswap32(val); |
67c332fd AF |
637 | } |
638 | if (phb->config_reg & (1u << 31)) { | |
639 | pci_data_write(phb->bus, phb->config_reg, val, 4); | |
640 | } | |
05b4ff43 TS |
641 | break; |
642 | ||
643 | /* Interrupts */ | |
644 | case GT_INTRCAUSE: | |
645 | /* not really implemented */ | |
646 | s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); | |
647 | s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); | |
abc7cf36 | 648 | trace_gt64120_write("INTRCAUSE", size, val); |
05b4ff43 TS |
649 | break; |
650 | case GT_INTRMASK: | |
651 | s->regs[saddr] = val & 0x3c3ffffe; | |
abc7cf36 | 652 | trace_gt64120_write("INTRMASK", size, val); |
05b4ff43 TS |
653 | break; |
654 | case GT_PCI0_ICMASK: | |
655 | s->regs[saddr] = val & 0x03fffffe; | |
abc7cf36 | 656 | trace_gt64120_write("ICMASK", size, val); |
05b4ff43 TS |
657 | break; |
658 | case GT_PCI0_SERR0MASK: | |
659 | s->regs[saddr] = val & 0x0000003f; | |
abc7cf36 | 660 | trace_gt64120_write("SERR0MASK", size, val); |
05b4ff43 TS |
661 | break; |
662 | ||
663 | /* Reserved when only PCI_0 is configured. */ | |
664 | case GT_HINTRCAUSE: | |
665 | case GT_CPU_INTSEL: | |
666 | case GT_PCI0_INTSEL: | |
667 | case GT_HINTRMASK: | |
668 | case GT_PCI0_HICMASK: | |
669 | case GT_PCI1_SERR1MASK: | |
670 | /* not implemented */ | |
fde7d5bd TS |
671 | break; |
672 | ||
0da75eb1 TS |
673 | /* SDRAM Parameters */ |
674 | case GT_SDRAM_B0: | |
675 | case GT_SDRAM_B1: | |
676 | case GT_SDRAM_B2: | |
677 | case GT_SDRAM_B3: | |
c47aee35 PMD |
678 | /* |
679 | * We don't simulate electrical parameters of the SDRAM. | |
680 | * Accept, but ignore the values. | |
681 | */ | |
0da75eb1 TS |
682 | s->regs[saddr] = val; |
683 | break; | |
684 | ||
fde7d5bd | 685 | default: |
641ca2bf PMD |
686 | qemu_log_mask(LOG_GUEST_ERROR, |
687 | "gt64120: Illegal register write " | |
688 | "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", | |
689 | saddr << 2, size, size << 1, val); | |
fde7d5bd TS |
690 | break; |
691 | } | |
692 | } | |
693 | ||
b61104b2 PMD |
694 | static uint64_t gt64120_readl(void *opaque, |
695 | hwaddr addr, unsigned size) | |
fde7d5bd TS |
696 | { |
697 | GT64120State *s = opaque; | |
67c332fd | 698 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
fde7d5bd TS |
699 | uint32_t val; |
700 | uint32_t saddr; | |
701 | ||
fde7d5bd | 702 | saddr = (addr & 0xfff) >> 2; |
fde7d5bd TS |
703 | switch (saddr) { |
704 | ||
0da75eb1 TS |
705 | /* CPU Configuration */ |
706 | case GT_MULTI: | |
c47aee35 PMD |
707 | /* |
708 | * Only one GT64xxx is present on the CPU bus, return | |
709 | * the initial value. | |
710 | */ | |
0da75eb1 TS |
711 | val = s->regs[saddr]; |
712 | break; | |
713 | ||
fde7d5bd TS |
714 | /* CPU Error Report */ |
715 | case GT_CPUERR_ADDRLO: | |
716 | case GT_CPUERR_ADDRHI: | |
717 | case GT_CPUERR_DATALO: | |
718 | case GT_CPUERR_DATAHI: | |
719 | case GT_CPUERR_PARITY: | |
c47aee35 | 720 | /* Emulated memory has no error, always return the initial values. */ |
0da75eb1 TS |
721 | val = s->regs[saddr]; |
722 | break; | |
723 | ||
724 | /* CPU Sync Barrier */ | |
725 | case GT_PCI0SYNC: | |
726 | case GT_PCI1SYNC: | |
c47aee35 PMD |
727 | /* |
728 | * Reading those register should empty all FIFO on the PCI | |
729 | * bus, which are not emulated. The return value should be | |
730 | * a random value that should be ignored. | |
731 | */ | |
5fafdf24 | 732 | val = 0xc000ffee; |
fde7d5bd TS |
733 | break; |
734 | ||
735 | /* ECC */ | |
736 | case GT_ECC_ERRDATALO: | |
737 | case GT_ECC_ERRDATAHI: | |
738 | case GT_ECC_MEM: | |
739 | case GT_ECC_CALC: | |
740 | case GT_ECC_ERRADDR: | |
c47aee35 | 741 | /* Emulated memory has no error, always return the initial values. */ |
0da75eb1 | 742 | val = s->regs[saddr]; |
fde7d5bd TS |
743 | break; |
744 | ||
745 | case GT_CPU: | |
05b4ff43 TS |
746 | case GT_SCS10LD: |
747 | case GT_SCS10HD: | |
748 | case GT_SCS32LD: | |
749 | case GT_SCS32HD: | |
750 | case GT_CS20LD: | |
751 | case GT_CS20HD: | |
752 | case GT_CS3BOOTLD: | |
753 | case GT_CS3BOOTHD: | |
754 | case GT_SCS10AR: | |
755 | case GT_SCS32AR: | |
756 | case GT_CS20R: | |
757 | case GT_CS3BOOTR: | |
fde7d5bd TS |
758 | case GT_PCI0IOLD: |
759 | case GT_PCI0M0LD: | |
760 | case GT_PCI0M1LD: | |
761 | case GT_PCI1IOLD: | |
762 | case GT_PCI1M0LD: | |
763 | case GT_PCI1M1LD: | |
764 | case GT_PCI0IOHD: | |
765 | case GT_PCI0M0HD: | |
766 | case GT_PCI0M1HD: | |
767 | case GT_PCI1IOHD: | |
768 | case GT_PCI1M0HD: | |
769 | case GT_PCI1M1HD: | |
fde7d5bd TS |
770 | case GT_PCI0IOREMAP: |
771 | case GT_PCI0M0REMAP: | |
772 | case GT_PCI0M1REMAP: | |
773 | case GT_PCI1IOREMAP: | |
774 | case GT_PCI1M0REMAP: | |
775 | case GT_PCI1M1REMAP: | |
05b4ff43 | 776 | case GT_ISD: |
fde7d5bd TS |
777 | val = s->regs[saddr]; |
778 | break; | |
779 | case GT_PCI0_IACK: | |
5fafdf24 | 780 | /* Read the IRQ number */ |
4de9b249 | 781 | val = pic_read_irq(isa_pic); |
fde7d5bd TS |
782 | break; |
783 | ||
05b4ff43 TS |
784 | /* SDRAM and Device Address Decode */ |
785 | case GT_SCS0LD: | |
786 | case GT_SCS0HD: | |
787 | case GT_SCS1LD: | |
788 | case GT_SCS1HD: | |
789 | case GT_SCS2LD: | |
790 | case GT_SCS2HD: | |
791 | case GT_SCS3LD: | |
792 | case GT_SCS3HD: | |
793 | case GT_CS0LD: | |
794 | case GT_CS0HD: | |
795 | case GT_CS1LD: | |
796 | case GT_CS1HD: | |
797 | case GT_CS2LD: | |
798 | case GT_CS2HD: | |
799 | case GT_CS3LD: | |
800 | case GT_CS3HD: | |
801 | case GT_BOOTLD: | |
802 | case GT_BOOTHD: | |
803 | case GT_ADERR: | |
804 | val = s->regs[saddr]; | |
805 | break; | |
806 | ||
807 | /* SDRAM Configuration */ | |
808 | case GT_SDRAM_CFG: | |
809 | case GT_SDRAM_OPMODE: | |
810 | case GT_SDRAM_BM: | |
811 | case GT_SDRAM_ADDRDECODE: | |
812 | val = s->regs[saddr]; | |
813 | break; | |
814 | ||
0da75eb1 TS |
815 | /* SDRAM Parameters */ |
816 | case GT_SDRAM_B0: | |
817 | case GT_SDRAM_B1: | |
818 | case GT_SDRAM_B2: | |
819 | case GT_SDRAM_B3: | |
c47aee35 PMD |
820 | /* |
821 | * We don't simulate electrical parameters of the SDRAM. | |
822 | * Just return the last written value. | |
823 | */ | |
0da75eb1 TS |
824 | val = s->regs[saddr]; |
825 | break; | |
826 | ||
05b4ff43 TS |
827 | /* Device Parameters */ |
828 | case GT_DEV_B0: | |
829 | case GT_DEV_B1: | |
830 | case GT_DEV_B2: | |
831 | case GT_DEV_B3: | |
832 | case GT_DEV_BOOT: | |
833 | val = s->regs[saddr]; | |
834 | break; | |
835 | ||
836 | /* DMA Record */ | |
837 | case GT_DMA0_CNT: | |
838 | case GT_DMA1_CNT: | |
839 | case GT_DMA2_CNT: | |
840 | case GT_DMA3_CNT: | |
841 | case GT_DMA0_SA: | |
842 | case GT_DMA1_SA: | |
843 | case GT_DMA2_SA: | |
844 | case GT_DMA3_SA: | |
845 | case GT_DMA0_DA: | |
846 | case GT_DMA1_DA: | |
847 | case GT_DMA2_DA: | |
848 | case GT_DMA3_DA: | |
849 | case GT_DMA0_NEXT: | |
850 | case GT_DMA1_NEXT: | |
851 | case GT_DMA2_NEXT: | |
852 | case GT_DMA3_NEXT: | |
853 | case GT_DMA0_CUR: | |
854 | case GT_DMA1_CUR: | |
855 | case GT_DMA2_CUR: | |
856 | case GT_DMA3_CUR: | |
857 | val = s->regs[saddr]; | |
858 | break; | |
859 | ||
860 | /* DMA Channel Control */ | |
861 | case GT_DMA0_CTRL: | |
862 | case GT_DMA1_CTRL: | |
863 | case GT_DMA2_CTRL: | |
864 | case GT_DMA3_CTRL: | |
865 | val = s->regs[saddr]; | |
866 | break; | |
867 | ||
868 | /* DMA Arbiter */ | |
869 | case GT_DMA_ARB: | |
870 | val = s->regs[saddr]; | |
871 | break; | |
872 | ||
873 | /* Timer/Counter */ | |
874 | case GT_TC0: | |
875 | case GT_TC1: | |
876 | case GT_TC2: | |
877 | case GT_TC3: | |
878 | case GT_TC_CONTROL: | |
879 | val = s->regs[saddr]; | |
880 | break; | |
881 | ||
fde7d5bd TS |
882 | /* PCI Internal */ |
883 | case GT_PCI0_CFGADDR: | |
67c332fd | 884 | val = phb->config_reg; |
fde7d5bd TS |
885 | break; |
886 | case GT_PCI0_CFGDATA: | |
67c332fd | 887 | if (!(phb->config_reg & (1 << 31))) { |
c6c99c3f | 888 | val = 0xffffffff; |
67c332fd AF |
889 | } else { |
890 | val = pci_data_read(phb->bus, phb->config_reg, 4); | |
891 | } | |
892 | if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { | |
c6c99c3f | 893 | val = bswap32(val); |
67c332fd | 894 | } |
05b4ff43 TS |
895 | break; |
896 | ||
897 | case GT_PCI0_CMD: | |
898 | case GT_PCI0_TOR: | |
899 | case GT_PCI0_BS_SCS10: | |
900 | case GT_PCI0_BS_SCS32: | |
901 | case GT_PCI0_BS_CS20: | |
902 | case GT_PCI0_BS_CS3BT: | |
903 | case GT_PCI1_IACK: | |
904 | case GT_PCI0_BARE: | |
905 | case GT_PCI0_PREFMBR: | |
906 | case GT_PCI0_SCS10_BAR: | |
907 | case GT_PCI0_SCS32_BAR: | |
908 | case GT_PCI0_CS20_BAR: | |
909 | case GT_PCI0_CS3BT_BAR: | |
910 | case GT_PCI0_SSCS10_BAR: | |
911 | case GT_PCI0_SSCS32_BAR: | |
912 | case GT_PCI0_SCS3BT_BAR: | |
913 | case GT_PCI1_CMD: | |
914 | case GT_PCI1_TOR: | |
915 | case GT_PCI1_BS_SCS10: | |
916 | case GT_PCI1_BS_SCS32: | |
917 | case GT_PCI1_BS_CS20: | |
918 | case GT_PCI1_BS_CS3BT: | |
919 | case GT_PCI1_BARE: | |
920 | case GT_PCI1_PREFMBR: | |
921 | case GT_PCI1_SCS10_BAR: | |
922 | case GT_PCI1_SCS32_BAR: | |
923 | case GT_PCI1_CS20_BAR: | |
924 | case GT_PCI1_CS3BT_BAR: | |
925 | case GT_PCI1_SSCS10_BAR: | |
926 | case GT_PCI1_SSCS32_BAR: | |
927 | case GT_PCI1_SCS3BT_BAR: | |
928 | case GT_PCI1_CFGADDR: | |
929 | case GT_PCI1_CFGDATA: | |
930 | val = s->regs[saddr]; | |
931 | break; | |
932 | ||
933 | /* Interrupts */ | |
934 | case GT_INTRCAUSE: | |
935 | val = s->regs[saddr]; | |
abc7cf36 | 936 | trace_gt64120_read("INTRCAUSE", size, val); |
05b4ff43 TS |
937 | break; |
938 | case GT_INTRMASK: | |
939 | val = s->regs[saddr]; | |
abc7cf36 | 940 | trace_gt64120_read("INTRMASK", size, val); |
05b4ff43 TS |
941 | break; |
942 | case GT_PCI0_ICMASK: | |
943 | val = s->regs[saddr]; | |
abc7cf36 | 944 | trace_gt64120_read("ICMASK", size, val); |
05b4ff43 TS |
945 | break; |
946 | case GT_PCI0_SERR0MASK: | |
947 | val = s->regs[saddr]; | |
abc7cf36 | 948 | trace_gt64120_read("SERR0MASK", size, val); |
05b4ff43 TS |
949 | break; |
950 | ||
951 | /* Reserved when only PCI_0 is configured. */ | |
952 | case GT_HINTRCAUSE: | |
953 | case GT_CPU_INTSEL: | |
954 | case GT_PCI0_INTSEL: | |
955 | case GT_HINTRMASK: | |
956 | case GT_PCI0_HICMASK: | |
957 | case GT_PCI1_SERR1MASK: | |
958 | val = s->regs[saddr]; | |
fde7d5bd TS |
959 | break; |
960 | ||
961 | default: | |
962 | val = s->regs[saddr]; | |
641ca2bf PMD |
963 | qemu_log_mask(LOG_GUEST_ERROR, |
964 | "gt64120: Illegal register read " | |
965 | "reg:0x03%x size:%u value:0x%0*x\n", | |
966 | saddr << 2, size, size << 1, val); | |
fde7d5bd TS |
967 | break; |
968 | } | |
969 | ||
53539655 | 970 | if (!(s->regs[GT_CPU] & 0x00001000)) { |
1931e260 | 971 | val = bswap32(val); |
53539655 | 972 | } |
1931e260 | 973 | |
05b4ff43 | 974 | return val; |
fde7d5bd TS |
975 | } |
976 | ||
fc2bf449 AK |
977 | static const MemoryRegionOps isd_mem_ops = { |
978 | .read = gt64120_readl, | |
979 | .write = gt64120_writel, | |
980 | .endianness = DEVICE_NATIVE_ENDIAN, | |
fde7d5bd TS |
981 | }; |
982 | ||
c2dd2a23 | 983 | static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
fde7d5bd TS |
984 | { |
985 | int slot; | |
986 | ||
987 | slot = (pci_dev->devfn >> 3); | |
988 | ||
989 | switch (slot) { | |
c47aee35 PMD |
990 | /* PIIX4 USB */ |
991 | case 10: | |
fde7d5bd | 992 | return 3; |
c47aee35 PMD |
993 | /* AMD 79C973 Ethernet */ |
994 | case 11: | |
d4a4d056 | 995 | return 1; |
c47aee35 PMD |
996 | /* Crystal 4281 Sound */ |
997 | case 12: | |
d4a4d056 | 998 | return 2; |
c47aee35 PMD |
999 | /* PCI slot 1 to 4 */ |
1000 | case 18 ... 21: | |
fde7d5bd | 1001 | return ((slot - 18) + irq_num) & 0x03; |
c47aee35 PMD |
1002 | /* Unknown device, don't do any translation */ |
1003 | default: | |
fde7d5bd TS |
1004 | return irq_num; |
1005 | } | |
1006 | } | |
1007 | ||
fde7d5bd TS |
1008 | static int pci_irq_levels[4]; |
1009 | ||
c2dd2a23 | 1010 | static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) |
fde7d5bd TS |
1011 | { |
1012 | int i, pic_irq, pic_level; | |
5d4e84c8 | 1013 | qemu_irq *pic = opaque; |
fde7d5bd TS |
1014 | |
1015 | pci_irq_levels[irq_num] = level; | |
1016 | ||
1017 | /* now we change the pic irq level according to the piix irq mappings */ | |
1018 | /* XXX: optimize */ | |
4b19de14 | 1019 | pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num]; |
fde7d5bd | 1020 | if (pic_irq < 16) { |
c47aee35 | 1021 | /* The pic level is the logical OR of all the PCI irqs mapped to it. */ |
fde7d5bd TS |
1022 | pic_level = 0; |
1023 | for (i = 0; i < 4; i++) { | |
4b19de14 | 1024 | if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { |
fde7d5bd | 1025 | pic_level |= pci_irq_levels[i]; |
53539655 | 1026 | } |
fde7d5bd | 1027 | } |
d537cf6c | 1028 | qemu_set_irq(pic[pic_irq], pic_level); |
fde7d5bd TS |
1029 | } |
1030 | } | |
1031 | ||
1032 | ||
43fd7bbf | 1033 | static void gt64120_reset(DeviceState *dev) |
fde7d5bd | 1034 | { |
43fd7bbf | 1035 | GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); |
fde7d5bd | 1036 | |
30b6f3a8 TS |
1037 | /* FIXME: Malta specific hw assumptions ahead */ |
1038 | ||
fde7d5bd TS |
1039 | /* CPU Configuration */ |
1040 | #ifdef TARGET_WORDS_BIGENDIAN | |
1041 | s->regs[GT_CPU] = 0x00000000; | |
1042 | #else | |
bc687ec9 | 1043 | s->regs[GT_CPU] = 0x00001000; |
fde7d5bd | 1044 | #endif |
30b6f3a8 TS |
1045 | s->regs[GT_MULTI] = 0x00000003; |
1046 | ||
1047 | /* CPU Address decode */ | |
1048 | s->regs[GT_SCS10LD] = 0x00000000; | |
1049 | s->regs[GT_SCS10HD] = 0x00000007; | |
1050 | s->regs[GT_SCS32LD] = 0x00000008; | |
1051 | s->regs[GT_SCS32HD] = 0x0000000f; | |
1052 | s->regs[GT_CS20LD] = 0x000000e0; | |
1053 | s->regs[GT_CS20HD] = 0x00000070; | |
1054 | s->regs[GT_CS3BOOTLD] = 0x000000f8; | |
1055 | s->regs[GT_CS3BOOTHD] = 0x0000007f; | |
fde7d5bd | 1056 | |
fde7d5bd TS |
1057 | s->regs[GT_PCI0IOLD] = 0x00000080; |
1058 | s->regs[GT_PCI0IOHD] = 0x0000000f; | |
1059 | s->regs[GT_PCI0M0LD] = 0x00000090; | |
1060 | s->regs[GT_PCI0M0HD] = 0x0000001f; | |
30b6f3a8 | 1061 | s->regs[GT_ISD] = 0x000000a0; |
fde7d5bd TS |
1062 | s->regs[GT_PCI0M1LD] = 0x00000790; |
1063 | s->regs[GT_PCI0M1HD] = 0x0000001f; | |
1064 | s->regs[GT_PCI1IOLD] = 0x00000100; | |
1065 | s->regs[GT_PCI1IOHD] = 0x0000000f; | |
1066 | s->regs[GT_PCI1M0LD] = 0x00000110; | |
1067 | s->regs[GT_PCI1M0HD] = 0x0000001f; | |
1068 | s->regs[GT_PCI1M1LD] = 0x00000120; | |
1069 | s->regs[GT_PCI1M1HD] = 0x0000002f; | |
30b6f3a8 TS |
1070 | |
1071 | s->regs[GT_SCS10AR] = 0x00000000; | |
1072 | s->regs[GT_SCS32AR] = 0x00000008; | |
1073 | s->regs[GT_CS20R] = 0x000000e0; | |
1074 | s->regs[GT_CS3BOOTR] = 0x000000f8; | |
1075 | ||
fde7d5bd TS |
1076 | s->regs[GT_PCI0IOREMAP] = 0x00000080; |
1077 | s->regs[GT_PCI0M0REMAP] = 0x00000090; | |
1078 | s->regs[GT_PCI0M1REMAP] = 0x00000790; | |
1079 | s->regs[GT_PCI1IOREMAP] = 0x00000100; | |
1080 | s->regs[GT_PCI1M0REMAP] = 0x00000110; | |
1081 | s->regs[GT_PCI1M1REMAP] = 0x00000120; | |
1082 | ||
1083 | /* CPU Error Report */ | |
1084 | s->regs[GT_CPUERR_ADDRLO] = 0x00000000; | |
1085 | s->regs[GT_CPUERR_ADDRHI] = 0x00000000; | |
1086 | s->regs[GT_CPUERR_DATALO] = 0xffffffff; | |
1087 | s->regs[GT_CPUERR_DATAHI] = 0xffffffff; | |
1088 | s->regs[GT_CPUERR_PARITY] = 0x000000ff; | |
1089 | ||
30b6f3a8 TS |
1090 | /* CPU Sync Barrier */ |
1091 | s->regs[GT_PCI0SYNC] = 0x00000000; | |
1092 | s->regs[GT_PCI1SYNC] = 0x00000000; | |
1093 | ||
1094 | /* SDRAM and Device Address Decode */ | |
1095 | s->regs[GT_SCS0LD] = 0x00000000; | |
1096 | s->regs[GT_SCS0HD] = 0x00000007; | |
1097 | s->regs[GT_SCS1LD] = 0x00000008; | |
1098 | s->regs[GT_SCS1HD] = 0x0000000f; | |
1099 | s->regs[GT_SCS2LD] = 0x00000010; | |
1100 | s->regs[GT_SCS2HD] = 0x00000017; | |
1101 | s->regs[GT_SCS3LD] = 0x00000018; | |
1102 | s->regs[GT_SCS3HD] = 0x0000001f; | |
1103 | s->regs[GT_CS0LD] = 0x000000c0; | |
1104 | s->regs[GT_CS0HD] = 0x000000c7; | |
1105 | s->regs[GT_CS1LD] = 0x000000c8; | |
1106 | s->regs[GT_CS1HD] = 0x000000cf; | |
1107 | s->regs[GT_CS2LD] = 0x000000d0; | |
1108 | s->regs[GT_CS2HD] = 0x000000df; | |
1109 | s->regs[GT_CS3LD] = 0x000000f0; | |
1110 | s->regs[GT_CS3HD] = 0x000000fb; | |
1111 | s->regs[GT_BOOTLD] = 0x000000fc; | |
1112 | s->regs[GT_BOOTHD] = 0x000000ff; | |
1113 | s->regs[GT_ADERR] = 0xffffffff; | |
1114 | ||
1115 | /* SDRAM Configuration */ | |
1116 | s->regs[GT_SDRAM_CFG] = 0x00000200; | |
1117 | s->regs[GT_SDRAM_OPMODE] = 0x00000000; | |
1118 | s->regs[GT_SDRAM_BM] = 0x00000007; | |
1119 | s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002; | |
1120 | ||
1121 | /* SDRAM Parameters */ | |
1122 | s->regs[GT_SDRAM_B0] = 0x00000005; | |
1123 | s->regs[GT_SDRAM_B1] = 0x00000005; | |
1124 | s->regs[GT_SDRAM_B2] = 0x00000005; | |
1125 | s->regs[GT_SDRAM_B3] = 0x00000005; | |
1126 | ||
fde7d5bd TS |
1127 | /* ECC */ |
1128 | s->regs[GT_ECC_ERRDATALO] = 0x00000000; | |
1129 | s->regs[GT_ECC_ERRDATAHI] = 0x00000000; | |
1130 | s->regs[GT_ECC_MEM] = 0x00000000; | |
1131 | s->regs[GT_ECC_CALC] = 0x00000000; | |
1132 | s->regs[GT_ECC_ERRADDR] = 0x00000000; | |
1133 | ||
30b6f3a8 TS |
1134 | /* Device Parameters */ |
1135 | s->regs[GT_DEV_B0] = 0x386fffff; | |
1136 | s->regs[GT_DEV_B1] = 0x386fffff; | |
1137 | s->regs[GT_DEV_B2] = 0x386fffff; | |
1138 | s->regs[GT_DEV_B3] = 0x386fffff; | |
1139 | s->regs[GT_DEV_BOOT] = 0x146fffff; | |
0da75eb1 | 1140 | |
30b6f3a8 TS |
1141 | /* DMA registers are all zeroed at reset */ |
1142 | ||
1143 | /* Timer/Counter */ | |
1144 | s->regs[GT_TC0] = 0xffffffff; | |
1145 | s->regs[GT_TC1] = 0x00ffffff; | |
1146 | s->regs[GT_TC2] = 0x00ffffff; | |
1147 | s->regs[GT_TC3] = 0x00ffffff; | |
1148 | s->regs[GT_TC_CONTROL] = 0x00000000; | |
1149 | ||
1150 | /* PCI Internal */ | |
fde7d5bd TS |
1151 | #ifdef TARGET_WORDS_BIGENDIAN |
1152 | s->regs[GT_PCI0_CMD] = 0x00000000; | |
fde7d5bd TS |
1153 | #else |
1154 | s->regs[GT_PCI0_CMD] = 0x00010001; | |
fde7d5bd | 1155 | #endif |
30b6f3a8 TS |
1156 | s->regs[GT_PCI0_TOR] = 0x0000070f; |
1157 | s->regs[GT_PCI0_BS_SCS10] = 0x00fff000; | |
1158 | s->regs[GT_PCI0_BS_SCS32] = 0x00fff000; | |
1159 | s->regs[GT_PCI0_BS_CS20] = 0x01fff000; | |
1160 | s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000; | |
fde7d5bd | 1161 | s->regs[GT_PCI1_IACK] = 0x00000000; |
30b6f3a8 TS |
1162 | s->regs[GT_PCI0_IACK] = 0x00000000; |
1163 | s->regs[GT_PCI0_BARE] = 0x0000000f; | |
1164 | s->regs[GT_PCI0_PREFMBR] = 0x00000040; | |
1165 | s->regs[GT_PCI0_SCS10_BAR] = 0x00000000; | |
1166 | s->regs[GT_PCI0_SCS32_BAR] = 0x01000000; | |
1167 | s->regs[GT_PCI0_CS20_BAR] = 0x1c000000; | |
1168 | s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000; | |
1169 | s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000; | |
1170 | s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000; | |
1171 | s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000; | |
1172 | #ifdef TARGET_WORDS_BIGENDIAN | |
1173 | s->regs[GT_PCI1_CMD] = 0x00000000; | |
1174 | #else | |
1175 | s->regs[GT_PCI1_CMD] = 0x00010001; | |
1176 | #endif | |
1177 | s->regs[GT_PCI1_TOR] = 0x0000070f; | |
1178 | s->regs[GT_PCI1_BS_SCS10] = 0x00fff000; | |
1179 | s->regs[GT_PCI1_BS_SCS32] = 0x00fff000; | |
1180 | s->regs[GT_PCI1_BS_CS20] = 0x01fff000; | |
1181 | s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000; | |
1182 | s->regs[GT_PCI1_BARE] = 0x0000000f; | |
1183 | s->regs[GT_PCI1_PREFMBR] = 0x00000040; | |
1184 | s->regs[GT_PCI1_SCS10_BAR] = 0x00000000; | |
1185 | s->regs[GT_PCI1_SCS32_BAR] = 0x01000000; | |
1186 | s->regs[GT_PCI1_CS20_BAR] = 0x1c000000; | |
1187 | s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000; | |
1188 | s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000; | |
1189 | s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000; | |
1190 | s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000; | |
1191 | s->regs[GT_PCI1_CFGADDR] = 0x00000000; | |
1192 | s->regs[GT_PCI1_CFGDATA] = 0x00000000; | |
1193 | s->regs[GT_PCI0_CFGADDR] = 0x00000000; | |
30b6f3a8 TS |
1194 | |
1195 | /* Interrupt registers are all zeroed at reset */ | |
fde7d5bd | 1196 | |
a0a8793e | 1197 | gt64120_isd_mapping(s); |
9414cc6f | 1198 | gt64120_pci_mapping(s); |
fde7d5bd TS |
1199 | } |
1200 | ||
c2dd2a23 AJ |
1201 | PCIBus *gt64120_register(qemu_irq *pic) |
1202 | { | |
c2dd2a23 | 1203 | GT64120State *d; |
8d43d7e5 | 1204 | PCIHostState *phb; |
c2dd2a23 AJ |
1205 | DeviceState *dev; |
1206 | ||
3e80f690 | 1207 | dev = qdev_new(TYPE_GT64120_PCI_HOST_BRIDGE); |
8d43d7e5 | 1208 | d = GT64120_PCI_HOST_BRIDGE(dev); |
8558d942 | 1209 | phb = PCI_HOST_BRIDGE(dev); |
8110b2bf | 1210 | memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB); |
f720f203 | 1211 | address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem"); |
1115ff6d DG |
1212 | phb->bus = pci_register_root_bus(dev, "pci", |
1213 | gt64120_pci_set_irq, gt64120_pci_map_irq, | |
1214 | pic, | |
1215 | &d->pci0_mem, | |
1216 | get_system_io(), | |
1217 | PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); | |
3c6ef471 | 1218 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
b61104b2 PMD |
1219 | memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, |
1220 | "isd-mem", 0x1000); | |
c2dd2a23 | 1221 | |
8d43d7e5 AF |
1222 | pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); |
1223 | return phb->bus; | |
c2dd2a23 AJ |
1224 | } |
1225 | ||
b429d363 | 1226 | static void gt64120_pci_realize(PCIDevice *d, Error **errp) |
c2dd2a23 | 1227 | { |
0f78cf0c | 1228 | /* FIXME: Malta specific hw assumptions ahead */ |
c2dd2a23 AJ |
1229 | pci_set_word(d->config + PCI_COMMAND, 0); |
1230 | pci_set_word(d->config + PCI_STATUS, | |
1231 | PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); | |
c2dd2a23 | 1232 | pci_config_set_prog_interface(d->config, 0); |
c2dd2a23 AJ |
1233 | pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); |
1234 | pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); | |
1235 | pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); | |
1236 | pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); | |
1237 | pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); | |
1238 | pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); | |
1239 | pci_set_byte(d->config + 0x3d, 0x01); | |
c2dd2a23 | 1240 | } |
a0a8793e | 1241 | |
40021f08 AL |
1242 | static void gt64120_pci_class_init(ObjectClass *klass, void *data) |
1243 | { | |
1244 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 1245 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 1246 | |
b429d363 | 1247 | k->realize = gt64120_pci_realize; |
40021f08 AL |
1248 | k->vendor_id = PCI_VENDOR_ID_MARVELL; |
1249 | k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; | |
1250 | k->revision = 0x10; | |
1251 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
1252 | /* |
1253 | * PCI-facing part of the host bridge, not usable without the | |
1254 | * host-facing part, which can't be device_add'ed, yet. | |
1255 | */ | |
e90f2a8c | 1256 | dc->user_creatable = false; |
40021f08 AL |
1257 | } |
1258 | ||
4240abff | 1259 | static const TypeInfo gt64120_pci_info = { |
39bffca2 AL |
1260 | .name = "gt64120_pci", |
1261 | .parent = TYPE_PCI_DEVICE, | |
1262 | .instance_size = sizeof(PCIDevice), | |
1263 | .class_init = gt64120_pci_class_init, | |
fd3b02c8 EH |
1264 | .interfaces = (InterfaceInfo[]) { |
1265 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
1266 | { }, | |
1267 | }, | |
c2dd2a23 | 1268 | }; |
1823082c | 1269 | |
999e12bb AL |
1270 | static void gt64120_class_init(ObjectClass *klass, void *data) |
1271 | { | |
427e1750 | 1272 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1273 | |
d1268699 | 1274 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
43fd7bbf | 1275 | dc->reset = gt64120_reset; |
427e1750 | 1276 | dc->vmsd = &vmstate_gt64120; |
999e12bb AL |
1277 | } |
1278 | ||
4240abff | 1279 | static const TypeInfo gt64120_info = { |
8d43d7e5 | 1280 | .name = TYPE_GT64120_PCI_HOST_BRIDGE, |
8558d942 | 1281 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 AL |
1282 | .instance_size = sizeof(GT64120State), |
1283 | .class_init = gt64120_class_init, | |
999e12bb AL |
1284 | }; |
1285 | ||
83f7d43a | 1286 | static void gt64120_pci_register_types(void) |
c2dd2a23 | 1287 | { |
39bffca2 AL |
1288 | type_register_static(>64120_info); |
1289 | type_register_static(>64120_pci_info); | |
fde7d5bd | 1290 | } |
c2dd2a23 | 1291 | |
83f7d43a | 1292 | type_init(gt64120_pci_register_types) |