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Commit | Line | Data |
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5856de80 TS |
1 | /* |
2 | * QEMU Malta board support | |
3 | * | |
4 | * Copyright (c) 2006 Aurelien Jarno | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
c684822a | 25 | #include "qemu/osdep.h" |
be01029e | 26 | #include "qemu/units.h" |
07741e67 | 27 | #include "qemu/bitops.h" |
2c65db5e | 28 | #include "qemu/datadir.h" |
6233a138 | 29 | #include "qemu/guest-random.h" |
eea1f5ba | 30 | #include "hw/clock.h" |
fff123b8 | 31 | #include "hw/southbridge/piix.h" |
7313b1f2 | 32 | #include "hw/isa/superio.h" |
0d09e41a | 33 | #include "hw/char/serial.h" |
1422e32d | 34 | #include "net/net.h" |
83c9f4ca | 35 | #include "hw/boards.h" |
93198b6c | 36 | #include "hw/i2c/smbus_eeprom.h" |
0d09e41a PB |
37 | #include "hw/block/flash.h" |
38 | #include "hw/mips/mips.h" | |
fe1f2f4e | 39 | #include "hw/mips/bootloader.h" |
83c9f4ca | 40 | #include "hw/pci/pci.h" |
3c73d590 | 41 | #include "hw/pci/pci_bus.h" |
1de7afc9 | 42 | #include "qemu/log.h" |
d240d3fb | 43 | #include "hw/ide/pci.h" |
64552b6b | 44 | #include "hw/irq.h" |
83c9f4ca | 45 | #include "hw/loader.h" |
ca20cf32 | 46 | #include "elf.h" |
db1015e9 | 47 | #include "qom/object.h" |
83c9f4ca | 48 | #include "hw/sysbus.h" /* SysBusDevice */ |
02bccc77 | 49 | #include "qemu/host-utils.h" |
2c57bd9b | 50 | #include "sysemu/qtest.h" |
71e8a915 | 51 | #include "sysemu/reset.h" |
54d31236 | 52 | #include "sysemu/runstate.h" |
e688df6b | 53 | #include "qapi/error.h" |
2e985fe0 | 54 | #include "qemu/error-report.h" |
b0311811 | 55 | #include "sysemu/kvm.h" |
6b5fe137 | 56 | #include "semihosting/semihost.h" |
bff384a4 | 57 | #include "hw/mips/cps.h" |
eea1f5ba | 58 | #include "hw/qdev-clock.h" |
a8448735 | 59 | #include "target/mips/internal.h" |
9f81e43f | 60 | #include "trace.h" |
1eb64c39 | 61 | #include "cpu.h" |
5856de80 | 62 | |
df055c65 JY |
63 | #define ENVP_PADDR 0x2000 |
64 | #define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR) | |
94818443 AM |
65 | #define ENVP_NB_ENTRIES 16 |
66 | #define ENVP_ENTRY_SIZE 256 | |
5856de80 | 67 | |
03a1a8e1 | 68 | /* Hardware addresses */ |
94818443 AM |
69 | #define FLASH_ADDRESS 0x1e000000ULL |
70 | #define FPGA_ADDRESS 0x1f000000ULL | |
71 | #define RESET_ADDRESS 0x1fc00000ULL | |
03a1a8e1 | 72 | |
94818443 | 73 | #define FLASH_SIZE 0x400000 |
1eb64c39 | 74 | #define BIOS_SIZE (4 * MiB) |
03a1a8e1 | 75 | |
6dd92ce6 PMD |
76 | #define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0) |
77 | ||
5856de80 | 78 | typedef struct { |
ea85df72 AK |
79 | MemoryRegion iomem; |
80 | MemoryRegion iomem_lo; /* 0 - 0x900 */ | |
81 | MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */ | |
5856de80 TS |
82 | uint32_t leds; |
83 | uint32_t brk; | |
84 | uint32_t gpout; | |
130751ee | 85 | uint32_t i2cin; |
5856de80 TS |
86 | uint32_t i2coe; |
87 | uint32_t i2cout; | |
88 | uint32_t i2csel; | |
32a6ebec | 89 | CharBackend display; |
5856de80 | 90 | char display_text[9]; |
490a9d9b | 91 | SerialMM *uart; |
9850b05d | 92 | bool display_inited; |
5856de80 TS |
93 | } MaltaFPGAState; |
94 | ||
1eb64c39 PMD |
95 | #if TARGET_BIG_ENDIAN |
96 | #define BIOS_FILENAME "mips_bios.bin" | |
97 | #else | |
98 | #define BIOS_FILENAME "mipsel_bios.bin" | |
99 | #endif | |
100 | ||
cba5cb67 | 101 | #define TYPE_MIPS_MALTA "mips-malta" |
8063396b | 102 | OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA) |
cba5cb67 | 103 | |
db1015e9 | 104 | struct MaltaState { |
cba5cb67 AF |
105 | SysBusDevice parent_obj; |
106 | ||
eea1f5ba | 107 | Clock *cpuclk; |
2d5fac80 | 108 | MIPSCPSState cps; |
db1015e9 | 109 | }; |
e9b40fd3 | 110 | |
7df526e3 | 111 | static struct _loaderparams { |
71c199c8 | 112 | int ram_size, ram_low_size; |
7df526e3 TS |
113 | const char *kernel_filename; |
114 | const char *kernel_cmdline; | |
115 | const char *initrd_filename; | |
116 | } loaderparams; | |
117 | ||
5856de80 | 118 | /* Malta FPGA */ |
e7a65ba6 | 119 | static void malta_fpga_update_display_leds(MaltaFPGAState *s) |
5856de80 TS |
120 | { |
121 | char leds_text[9]; | |
122 | int i; | |
5856de80 | 123 | |
07cf0ba0 | 124 | for (i = 7 ; i >= 0 ; i--) { |
94818443 | 125 | if (s->leds & (1 << i)) { |
07cf0ba0 | 126 | leds_text[i] = '#'; |
94818443 | 127 | } else { |
07cf0ba0 | 128 | leds_text[i] = ' '; |
94818443 | 129 | } |
87ee1669 | 130 | } |
07cf0ba0 TS |
131 | leds_text[8] = '\0'; |
132 | ||
9f81e43f | 133 | trace_malta_fpga_leds(leds_text); |
5345fdb4 | 134 | qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", |
32a6ebec | 135 | leds_text); |
e7a65ba6 PMD |
136 | } |
137 | ||
138 | static void malta_fpga_update_display_ascii(MaltaFPGAState *s) | |
139 | { | |
9f81e43f | 140 | trace_malta_fpga_display(s->display_text); |
5345fdb4 | 141 | qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", |
32a6ebec | 142 | s->display_text); |
5856de80 TS |
143 | } |
144 | ||
130751ee TS |
145 | /* |
146 | * EEPROM 24C01 / 24C02 emulation. | |
147 | * | |
148 | * Emulation for serial EEPROMs: | |
149 | * 24C01 - 1024 bit (128 x 8) | |
150 | * 24C02 - 2048 bit (256 x 8) | |
151 | * | |
152 | * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02. | |
153 | */ | |
154 | ||
130751ee | 155 | #if defined(DEBUG) |
dbd07eda FB |
156 | # define logout(fmt, ...) \ |
157 | fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__) | |
130751ee | 158 | #else |
001faf32 | 159 | # define logout(fmt, ...) ((void)0) |
130751ee TS |
160 | #endif |
161 | ||
c227f099 | 162 | struct _eeprom24c0x_t { |
130751ee TS |
163 | uint8_t tick; |
164 | uint8_t address; | |
165 | uint8_t command; | |
166 | uint8_t ack; | |
167 | uint8_t scl; | |
168 | uint8_t sda; | |
169 | uint8_t data; | |
94818443 | 170 | /* uint16_t size; */ |
130751ee TS |
171 | uint8_t contents[256]; |
172 | }; | |
173 | ||
c227f099 | 174 | typedef struct _eeprom24c0x_t eeprom24c0x_t; |
130751ee | 175 | |
35c64807 | 176 | static eeprom24c0x_t spd_eeprom = { |
284b08f1 | 177 | .contents = { |
94818443 AM |
178 | /* 00000000: */ |
179 | 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00, | |
180 | /* 00000008: */ | |
181 | 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01, | |
182 | /* 00000010: */ | |
183 | 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, | |
184 | /* 00000018: */ | |
185 | 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF, | |
186 | /* 00000020: */ | |
187 | 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00, | |
188 | /* 00000028: */ | |
189 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
190 | /* 00000030: */ | |
191 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
192 | /* 00000038: */ | |
193 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0, | |
194 | /* 00000040: */ | |
195 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
196 | /* 00000048: */ | |
197 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
198 | /* 00000050: */ | |
199 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
200 | /* 00000058: */ | |
201 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
202 | /* 00000060: */ | |
203 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
204 | /* 00000068: */ | |
205 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
206 | /* 00000070: */ | |
207 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
208 | /* 00000078: */ | |
209 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4, | |
130751ee TS |
210 | }, |
211 | }; | |
212 | ||
35c64807 | 213 | static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size) |
02bccc77 | 214 | { |
9ce8c6dd | 215 | enum sdram_type type; |
35c64807 | 216 | uint8_t *spd = spd_eeprom.contents; |
02bccc77 PB |
217 | uint8_t nbanks = 0; |
218 | uint16_t density = 0; | |
219 | int i; | |
220 | ||
221 | /* work in terms of MB */ | |
be01029e | 222 | ram_size /= MiB; |
02bccc77 PB |
223 | |
224 | while ((ram_size >= 4) && (nbanks <= 2)) { | |
225 | int sz_log2 = MIN(31 - clz32(ram_size), 14); | |
226 | nbanks++; | |
227 | density |= 1 << (sz_log2 - 2); | |
228 | ram_size -= 1 << sz_log2; | |
229 | } | |
230 | ||
231 | /* split to 2 banks if possible */ | |
232 | if ((nbanks == 1) && (density > 1)) { | |
233 | nbanks++; | |
234 | density >>= 1; | |
235 | } | |
236 | ||
237 | if (density & 0xff00) { | |
238 | density = (density & 0xe0) | ((density >> 8) & 0x1f); | |
239 | type = DDR2; | |
240 | } else if (!(density & 0x1f)) { | |
241 | type = DDR2; | |
242 | } else { | |
243 | type = SDR; | |
244 | } | |
245 | ||
246 | if (ram_size) { | |
b62e39b4 AF |
247 | warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB" |
248 | " of SDRAM", ram_size); | |
02bccc77 PB |
249 | } |
250 | ||
251 | /* fill in SPD memory information */ | |
252 | spd[2] = type; | |
253 | spd[5] = nbanks; | |
254 | spd[31] = density; | |
255 | ||
256 | /* checksum */ | |
257 | spd[63] = 0; | |
258 | for (i = 0; i < 63; i++) { | |
259 | spd[63] += spd[i]; | |
260 | } | |
35c64807 PB |
261 | |
262 | /* copy for SMBUS */ | |
263 | memcpy(eeprom, spd, sizeof(spd_eeprom.contents)); | |
264 | } | |
265 | ||
266 | static void generate_eeprom_serial(uint8_t *eeprom) | |
267 | { | |
268 | int i, pos = 0; | |
269 | uint8_t mac[6] = { 0x00 }; | |
270 | uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 }; | |
271 | ||
272 | /* version */ | |
273 | eeprom[pos++] = 0x01; | |
274 | ||
275 | /* count */ | |
276 | eeprom[pos++] = 0x02; | |
277 | ||
278 | /* MAC address */ | |
279 | eeprom[pos++] = 0x01; /* MAC */ | |
280 | eeprom[pos++] = 0x06; /* length */ | |
281 | memcpy(&eeprom[pos], mac, sizeof(mac)); | |
282 | pos += sizeof(mac); | |
283 | ||
284 | /* serial number */ | |
285 | eeprom[pos++] = 0x02; /* serial */ | |
286 | eeprom[pos++] = 0x05; /* length */ | |
287 | memcpy(&eeprom[pos], sn, sizeof(sn)); | |
288 | pos += sizeof(sn); | |
289 | ||
290 | /* checksum */ | |
291 | eeprom[pos] = 0; | |
292 | for (i = 0; i < pos; i++) { | |
293 | eeprom[pos] += eeprom[i]; | |
294 | } | |
02bccc77 PB |
295 | } |
296 | ||
35c64807 | 297 | static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom) |
130751ee TS |
298 | { |
299 | logout("%u: scl = %u, sda = %u, data = 0x%02x\n", | |
35c64807 PB |
300 | eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data); |
301 | return eeprom->sda; | |
130751ee TS |
302 | } |
303 | ||
35c64807 | 304 | static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda) |
130751ee | 305 | { |
35c64807 | 306 | if (eeprom->scl && scl && (eeprom->sda != sda)) { |
130751ee | 307 | logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n", |
35c64807 PB |
308 | eeprom->tick, eeprom->scl, scl, eeprom->sda, sda, |
309 | sda ? "stop" : "start"); | |
130751ee | 310 | if (!sda) { |
35c64807 PB |
311 | eeprom->tick = 1; |
312 | eeprom->command = 0; | |
130751ee | 313 | } |
35c64807 | 314 | } else if (eeprom->tick == 0 && !eeprom->ack) { |
130751ee TS |
315 | /* Waiting for start. */ |
316 | logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n", | |
35c64807 PB |
317 | eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); |
318 | } else if (!eeprom->scl && scl) { | |
130751ee | 319 | logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n", |
35c64807 PB |
320 | eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); |
321 | if (eeprom->ack) { | |
130751ee TS |
322 | logout("\ti2c ack bit = 0\n"); |
323 | sda = 0; | |
35c64807 PB |
324 | eeprom->ack = 0; |
325 | } else if (eeprom->sda == sda) { | |
130751ee TS |
326 | uint8_t bit = (sda != 0); |
327 | logout("\ti2c bit = %d\n", bit); | |
35c64807 PB |
328 | if (eeprom->tick < 9) { |
329 | eeprom->command <<= 1; | |
330 | eeprom->command += bit; | |
331 | eeprom->tick++; | |
332 | if (eeprom->tick == 9) { | |
333 | logout("\tcommand 0x%04x, %s\n", eeprom->command, | |
334 | bit ? "read" : "write"); | |
335 | eeprom->ack = 1; | |
130751ee | 336 | } |
35c64807 PB |
337 | } else if (eeprom->tick < 17) { |
338 | if (eeprom->command & 1) { | |
339 | sda = ((eeprom->data & 0x80) != 0); | |
130751ee | 340 | } |
35c64807 PB |
341 | eeprom->address <<= 1; |
342 | eeprom->address += bit; | |
343 | eeprom->tick++; | |
344 | eeprom->data <<= 1; | |
345 | if (eeprom->tick == 17) { | |
346 | eeprom->data = eeprom->contents[eeprom->address]; | |
347 | logout("\taddress 0x%04x, data 0x%02x\n", | |
348 | eeprom->address, eeprom->data); | |
349 | eeprom->ack = 1; | |
350 | eeprom->tick = 0; | |
130751ee | 351 | } |
35c64807 | 352 | } else if (eeprom->tick >= 17) { |
130751ee TS |
353 | sda = 0; |
354 | } | |
355 | } else { | |
356 | logout("\tsda changed with raising scl\n"); | |
357 | } | |
358 | } else { | |
35c64807 PB |
359 | logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl, |
360 | scl, eeprom->sda, sda); | |
130751ee | 361 | } |
35c64807 PB |
362 | eeprom->scl = scl; |
363 | eeprom->sda = sda; | |
130751ee TS |
364 | } |
365 | ||
a8170e5e | 366 | static uint64_t malta_fpga_read(void *opaque, hwaddr addr, |
ea85df72 | 367 | unsigned size) |
5856de80 TS |
368 | { |
369 | MaltaFPGAState *s = opaque; | |
370 | uint32_t val = 0; | |
371 | uint32_t saddr; | |
372 | ||
373 | saddr = (addr & 0xfffff); | |
374 | ||
375 | switch (saddr) { | |
376 | ||
377 | /* SWITCH Register */ | |
378 | case 0x00200: | |
94818443 | 379 | val = 0x00000000; |
593c0d10 | 380 | break; |
5856de80 TS |
381 | |
382 | /* STATUS Register */ | |
383 | case 0x00208: | |
ee3eb3a7 | 384 | #if TARGET_BIG_ENDIAN |
5856de80 TS |
385 | val = 0x00000012; |
386 | #else | |
387 | val = 0x00000010; | |
388 | #endif | |
389 | break; | |
390 | ||
391 | /* JMPRS Register */ | |
392 | case 0x00210: | |
393 | val = 0x00; | |
394 | break; | |
395 | ||
396 | /* LEDBAR Register */ | |
397 | case 0x00408: | |
398 | val = s->leds; | |
399 | break; | |
400 | ||
401 | /* BRKRES Register */ | |
402 | case 0x00508: | |
403 | val = s->brk; | |
404 | break; | |
405 | ||
b6dc7ebb | 406 | /* UART Registers are handled directly by the serial device */ |
a4bc3afc | 407 | |
5856de80 TS |
408 | /* GPOUT Register */ |
409 | case 0x00a00: | |
410 | val = s->gpout; | |
411 | break; | |
412 | ||
413 | /* XXX: implement a real I2C controller */ | |
414 | ||
415 | /* GPINP Register */ | |
416 | case 0x00a08: | |
417 | /* IN = OUT until a real I2C control is implemented */ | |
94818443 | 418 | if (s->i2csel) { |
5856de80 | 419 | val = s->i2cout; |
94818443 | 420 | } else { |
5856de80 | 421 | val = 0x00; |
94818443 | 422 | } |
5856de80 TS |
423 | break; |
424 | ||
425 | /* I2CINP Register */ | |
426 | case 0x00b00: | |
35c64807 | 427 | val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom)); |
5856de80 TS |
428 | break; |
429 | ||
430 | /* I2COE Register */ | |
431 | case 0x00b08: | |
432 | val = s->i2coe; | |
433 | break; | |
434 | ||
435 | /* I2COUT Register */ | |
436 | case 0x00b10: | |
437 | val = s->i2cout; | |
438 | break; | |
439 | ||
440 | /* I2CSEL Register */ | |
441 | case 0x00b18: | |
130751ee | 442 | val = s->i2csel; |
5856de80 TS |
443 | break; |
444 | ||
445 | default: | |
c707f06f AM |
446 | qemu_log_mask(LOG_GUEST_ERROR, |
447 | "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n", | |
448 | addr); | |
5856de80 TS |
449 | break; |
450 | } | |
451 | return val; | |
452 | } | |
453 | ||
a8170e5e | 454 | static void malta_fpga_write(void *opaque, hwaddr addr, |
ea85df72 | 455 | uint64_t val, unsigned size) |
5856de80 TS |
456 | { |
457 | MaltaFPGAState *s = opaque; | |
458 | uint32_t saddr; | |
459 | ||
460 | saddr = (addr & 0xfffff); | |
461 | ||
462 | switch (saddr) { | |
463 | ||
464 | /* SWITCH Register */ | |
465 | case 0x00200: | |
466 | break; | |
467 | ||
468 | /* JMPRS Register */ | |
469 | case 0x00210: | |
470 | break; | |
471 | ||
472 | /* LEDBAR Register */ | |
5856de80 TS |
473 | case 0x00408: |
474 | s->leds = val & 0xff; | |
e7a65ba6 | 475 | malta_fpga_update_display_leds(s); |
5856de80 TS |
476 | break; |
477 | ||
478 | /* ASCIIWORD Register */ | |
479 | case 0x00410: | |
ea85df72 | 480 | snprintf(s->display_text, 9, "%08X", (uint32_t)val); |
e7a65ba6 | 481 | malta_fpga_update_display_ascii(s); |
5856de80 TS |
482 | break; |
483 | ||
484 | /* ASCIIPOS0 to ASCIIPOS7 Registers */ | |
485 | case 0x00418: | |
486 | case 0x00420: | |
487 | case 0x00428: | |
488 | case 0x00430: | |
489 | case 0x00438: | |
490 | case 0x00440: | |
491 | case 0x00448: | |
492 | case 0x00450: | |
493 | s->display_text[(saddr - 0x00418) >> 3] = (char) val; | |
e7a65ba6 | 494 | malta_fpga_update_display_ascii(s); |
5856de80 TS |
495 | break; |
496 | ||
497 | /* SOFTRES Register */ | |
498 | case 0x00500: | |
94818443 | 499 | if (val == 0x42) { |
cf83f140 | 500 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
94818443 | 501 | } |
5856de80 TS |
502 | break; |
503 | ||
504 | /* BRKRES Register */ | |
505 | case 0x00508: | |
506 | s->brk = val & 0xff; | |
507 | break; | |
508 | ||
b6dc7ebb | 509 | /* UART Registers are handled directly by the serial device */ |
a4bc3afc | 510 | |
5856de80 TS |
511 | /* GPOUT Register */ |
512 | case 0x00a00: | |
513 | s->gpout = val & 0xff; | |
514 | break; | |
515 | ||
516 | /* I2COE Register */ | |
517 | case 0x00b08: | |
518 | s->i2coe = val & 0x03; | |
519 | break; | |
520 | ||
521 | /* I2COUT Register */ | |
522 | case 0x00b10: | |
35c64807 | 523 | eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01); |
130751ee | 524 | s->i2cout = val; |
5856de80 TS |
525 | break; |
526 | ||
527 | /* I2CSEL Register */ | |
528 | case 0x00b18: | |
130751ee | 529 | s->i2csel = val & 0x01; |
5856de80 TS |
530 | break; |
531 | ||
532 | default: | |
c707f06f AM |
533 | qemu_log_mask(LOG_GUEST_ERROR, |
534 | "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n", | |
535 | addr); | |
5856de80 TS |
536 | break; |
537 | } | |
538 | } | |
539 | ||
ea85df72 AK |
540 | static const MemoryRegionOps malta_fpga_ops = { |
541 | .read = malta_fpga_read, | |
542 | .write = malta_fpga_write, | |
543 | .endianness = DEVICE_NATIVE_ENDIAN, | |
5856de80 TS |
544 | }; |
545 | ||
9596ebb7 | 546 | static void malta_fpga_reset(void *opaque) |
5856de80 TS |
547 | { |
548 | MaltaFPGAState *s = opaque; | |
549 | ||
550 | s->leds = 0x00; | |
551 | s->brk = 0x0a; | |
552 | s->gpout = 0x00; | |
130751ee | 553 | s->i2cin = 0x3; |
5856de80 TS |
554 | s->i2coe = 0x0; |
555 | s->i2cout = 0x3; | |
556 | s->i2csel = 0x1; | |
557 | ||
558 | s->display_text[8] = '\0'; | |
559 | snprintf(s->display_text, 9, " "); | |
ceecf1d1 AJ |
560 | } |
561 | ||
083b266f | 562 | static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event) |
ceecf1d1 | 563 | { |
9850b05d MAL |
564 | MaltaFPGAState *s = opaque; |
565 | ||
566 | if (event == CHR_EVENT_OPENED && !s->display_inited) { | |
5345fdb4 MAL |
567 | qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n"); |
568 | qemu_chr_fe_printf(&s->display, "+--------+\r\n"); | |
569 | qemu_chr_fe_printf(&s->display, "+ +\r\n"); | |
570 | qemu_chr_fe_printf(&s->display, "+--------+\r\n"); | |
571 | qemu_chr_fe_printf(&s->display, "\n"); | |
572 | qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n"); | |
573 | qemu_chr_fe_printf(&s->display, "+--------+\r\n"); | |
574 | qemu_chr_fe_printf(&s->display, "+ +\r\n"); | |
575 | qemu_chr_fe_printf(&s->display, "+--------+\r\n"); | |
9850b05d MAL |
576 | s->display_inited = true; |
577 | } | |
5856de80 TS |
578 | } |
579 | ||
ea85df72 | 580 | static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space, |
0ec7b3e7 | 581 | hwaddr base, qemu_irq uart_irq, Chardev *uart_chr) |
5856de80 TS |
582 | { |
583 | MaltaFPGAState *s; | |
0ec7b3e7 | 584 | Chardev *chr; |
5856de80 | 585 | |
dbd07eda | 586 | s = g_new0(MaltaFPGAState, 1); |
5856de80 | 587 | |
2c9b15ca | 588 | memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s, |
ea85df72 | 589 | "malta-fpga", 0x100000); |
2c9b15ca | 590 | memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga", |
ea85df72 | 591 | &s->iomem, 0, 0x900); |
2c9b15ca | 592 | memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga", |
9a2133f4 | 593 | &s->iomem, 0xa00, 0x100000 - 0xa00); |
a4bc3afc | 594 | |
ea85df72 AK |
595 | memory_region_add_subregion(address_space, base, &s->iomem_lo); |
596 | memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi); | |
5856de80 | 597 | |
4ad6f6cb | 598 | chr = qemu_chr_new("fpga", "vc:320x200", NULL); |
5345fdb4 MAL |
599 | qemu_chr_fe_init(&s->display, chr, NULL); |
600 | qemu_chr_fe_set_handlers(&s->display, NULL, NULL, | |
81517ba3 | 601 | malta_fgpa_display_event, NULL, s, NULL, true); |
ceecf1d1 | 602 | |
39186d8a RH |
603 | s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq, |
604 | 230400, uart_chr, DEVICE_NATIVE_ENDIAN); | |
a4bc3afc | 605 | |
5856de80 | 606 | malta_fpga_reset(s); |
a08d4367 | 607 | qemu_register_reset(malta_fpga_reset, s); |
5856de80 TS |
608 | |
609 | return s; | |
610 | } | |
611 | ||
5856de80 | 612 | /* Network support */ |
29b358f9 | 613 | static void network_init(PCIBus *pci_bus) |
5856de80 TS |
614 | { |
615 | int i; | |
5856de80 | 616 | |
94818443 | 617 | for (i = 0; i < nb_nics; i++) { |
cb457d76 | 618 | NICInfo *nd = &nd_table[i]; |
5607c388 | 619 | const char *default_devaddr = NULL; |
cb457d76 AL |
620 | |
621 | if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0)) | |
5856de80 | 622 | /* The malta board has a PCNet card using PCI SLOT 11 */ |
5607c388 | 623 | default_devaddr = "0b"; |
cb457d76 | 624 | |
29b358f9 | 625 | pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr); |
5856de80 TS |
626 | } |
627 | } | |
628 | ||
0e45355c PMD |
629 | static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, |
630 | uint64_t kernel_entry) | |
ce3940cc | 631 | { |
1953dfa8 PMD |
632 | static const char pci_pins_cfg[PCI_NUM_PINS] = { |
633 | 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ | |
634 | }; | |
635 | ||
d5c9fa47 | 636 | /* Bus endianness is always reversed */ |
ee3eb3a7 | 637 | #if TARGET_BIG_ENDIAN |
dc96009a | 638 | #define cpu_to_gt32(x) (x) |
28861af8 | 639 | #else |
dc96009a | 640 | #define cpu_to_gt32(x) bswap32(x) |
391a2bda | 641 | #endif |
28861af8 | 642 | |
3265f41f PMD |
643 | /* setup MEM-to-PCI0 mapping as done by YAMON */ |
644 | ||
645 | /* move GT64120 registers from 0x14000000 to 0x1be00000 */ | |
0e45355c | 646 | bl_gen_write_u32(p, /* GT_ISD */ |
3265f41f PMD |
647 | cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), |
648 | cpu_to_gt32(0x1be00000 << 3)); | |
649 | ||
02e0bec4 | 650 | /* setup PCI0 io window to 0x18000000-0x181fffff */ |
0e45355c | 651 | bl_gen_write_u32(p, /* GT_PCI0IOLD */ |
02e0bec4 PMD |
652 | cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), |
653 | cpu_to_gt32(0x18000000 << 3)); | |
0e45355c | 654 | bl_gen_write_u32(p, /* GT_PCI0IOHD */ |
02e0bec4 PMD |
655 | cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), |
656 | cpu_to_gt32(0x08000000 << 3)); | |
657 | ||
391a2bda | 658 | /* setup PCI0 mem windows */ |
0e45355c | 659 | bl_gen_write_u32(p, /* GT_PCI0M0LD */ |
262502a6 PMD |
660 | cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), |
661 | cpu_to_gt32(0x10000000 << 3)); | |
0e45355c | 662 | bl_gen_write_u32(p, /* GT_PCI0M0HD */ |
262502a6 PMD |
663 | cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), |
664 | cpu_to_gt32(0x07e00000 << 3)); | |
0e45355c | 665 | bl_gen_write_u32(p, /* GT_PCI0M1LD */ |
391a2bda PMD |
666 | cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), |
667 | cpu_to_gt32(0x18200000 << 3)); | |
0e45355c | 668 | bl_gen_write_u32(p, /* GT_PCI0M1HD */ |
391a2bda PMD |
669 | cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), |
670 | cpu_to_gt32(0x0bc00000 << 3)); | |
28861af8 | 671 | |
391a2bda | 672 | #undef cpu_to_gt32 |
28861af8 | 673 | |
1953dfa8 PMD |
674 | /* |
675 | * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. | |
676 | * Load the PIIX IRQC[A:D] routing config address, then | |
677 | * write routing configuration to the config data register. | |
678 | */ | |
679 | bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */ | |
680 | cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), | |
681 | tswap32((1 << 31) /* ConfigEn */ | |
682 | | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 | |
683 | | PIIX_PIRQCA)); | |
684 | bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */ | |
685 | cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), | |
686 | tswap32(ldl_be_p(pci_pins_cfg))); | |
687 | ||
0e45355c | 688 | bl_gen_jump_kernel(p, |
9f911a25 PMD |
689 | true, ENVP_VADDR - 64, |
690 | /* | |
0e45355c PMD |
691 | * If semihosting is used, arguments have already |
692 | * been passed, so we preserve $a0. | |
9f911a25 PMD |
693 | */ |
694 | !semihosting_get_argc(), 2, | |
695 | true, ENVP_VADDR, | |
696 | true, ENVP_VADDR + 8, | |
697 | true, loaderparams.ram_low_size, | |
698 | kernel_entry); | |
ce3940cc MF |
699 | } |
700 | ||
0e45355c PMD |
701 | static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, |
702 | uint64_t kernel_entry) | |
703 | { | |
704 | uint16_t *p; | |
705 | ||
706 | /* Small bootloader */ | |
707 | p = (uint16_t *)base; | |
708 | ||
709 | stw_p(p++, 0x2800); stw_p(p++, 0x001c); | |
710 | /* bc to_here */ | |
711 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
712 | /* nop */ | |
713 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
714 | /* nop */ | |
715 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
716 | /* nop */ | |
717 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
718 | /* nop */ | |
719 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
720 | /* nop */ | |
721 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
722 | /* nop */ | |
723 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
724 | /* nop */ | |
725 | ||
726 | /* to_here: */ | |
727 | ||
728 | bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); | |
729 | } | |
730 | ||
94818443 AM |
731 | /* |
732 | * ROM and pseudo bootloader | |
733 | * | |
734 | * The following code implements a very very simple bootloader. It first | |
735 | * loads the registers a0 to a3 to the values expected by the OS, and | |
736 | * then jump at the kernel address. | |
737 | * | |
738 | * The bootloader should pass the locations of the kernel arguments and | |
739 | * environment variables tables. Those tables contain the 32-bit address | |
740 | * of NULL terminated strings. The environment variables table should be | |
741 | * terminated by a NULL address. | |
742 | * | |
743 | * For a simpler implementation, the number of kernel arguments is fixed | |
744 | * to two (the name of the kernel and the command line), and the two | |
745 | * tables are actually the same one. | |
746 | * | |
747 | * The registers a0 to a3 should contain the following values: | |
748 | * a0 - number of kernel arguments | |
749 | * a1 - 32-bit address of the kernel arguments table | |
750 | * a2 - 32-bit address of the environment variables table | |
751 | * a3 - RAM size in bytes | |
752 | */ | |
dde98994 JY |
753 | static void write_bootloader(uint8_t *base, uint64_t run_addr, |
754 | uint64_t kernel_entry) | |
5856de80 TS |
755 | { |
756 | uint32_t *p; | |
757 | ||
758 | /* Small bootloader */ | |
d7585251 | 759 | p = (uint32_t *)base; |
b0311811 | 760 | |
dbd07eda | 761 | stl_p(p++, 0x08000000 | /* j 0x1fc00580 */ |
b0311811 | 762 | ((run_addr + 0x580) & 0x0fffffff) >> 2); |
dbd07eda | 763 | stl_p(p++, 0x00000000); /* nop */ |
5856de80 | 764 | |
26ea0918 | 765 | /* YAMON service vector */ |
dbd07eda FB |
766 | stl_p(base + 0x500, run_addr + 0x0580); /* start: */ |
767 | stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */ | |
768 | stl_p(base + 0x520, run_addr + 0x0580); /* start: */ | |
769 | stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */ | |
770 | stl_p(base + 0x534, run_addr + 0x0808); /* print: */ | |
771 | stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */ | |
772 | stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */ | |
773 | stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */ | |
774 | stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */ | |
775 | stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */ | |
776 | stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */ | |
777 | stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */ | |
778 | stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */ | |
26ea0918 TS |
779 | |
780 | ||
5856de80 | 781 | /* Second part of the bootloader */ |
d7585251 | 782 | p = (uint32_t *) (base + 0x580); |
3b3c1694 | 783 | |
0c8427ba JY |
784 | /* |
785 | * Load BAR registers as done by YAMON: | |
786 | * | |
787 | * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff | |
788 | * - set up PCI0 MEM0 at 0x10000000, size 0x7e00000 | |
789 | * - set up PCI0 MEM1 at 0x18200000, size 0xbc00000 | |
790 | * | |
791 | */ | |
2802bfe3 | 792 | |
9d8299bf | 793 | bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); |
26ea0918 TS |
794 | |
795 | /* YAMON subroutines */ | |
d7585251 | 796 | p = (uint32_t *) (base + 0x800); |
dbd07eda FB |
797 | stl_p(p++, 0x03e00009); /* jalr ra */ |
798 | stl_p(p++, 0x24020000); /* li v0,0 */ | |
b0311811 | 799 | /* 808 YAMON print */ |
dbd07eda FB |
800 | stl_p(p++, 0x03e06821); /* move t5,ra */ |
801 | stl_p(p++, 0x00805821); /* move t3,a0 */ | |
802 | stl_p(p++, 0x00a05021); /* move t2,a1 */ | |
803 | stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ | |
804 | stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ | |
805 | stl_p(p++, 0x10800005); /* beqz a0,834 */ | |
806 | stl_p(p++, 0x00000000); /* nop */ | |
807 | stl_p(p++, 0x0ff0021c); /* jal 870 */ | |
808 | stl_p(p++, 0x00000000); /* nop */ | |
809 | stl_p(p++, 0x1000fff9); /* b 814 */ | |
810 | stl_p(p++, 0x00000000); /* nop */ | |
811 | stl_p(p++, 0x01a00009); /* jalr t5 */ | |
812 | stl_p(p++, 0x01602021); /* move a0,t3 */ | |
26ea0918 | 813 | /* 0x83c YAMON print_count */ |
dbd07eda FB |
814 | stl_p(p++, 0x03e06821); /* move t5,ra */ |
815 | stl_p(p++, 0x00805821); /* move t3,a0 */ | |
816 | stl_p(p++, 0x00a05021); /* move t2,a1 */ | |
817 | stl_p(p++, 0x00c06021); /* move t4,a2 */ | |
818 | stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ | |
819 | stl_p(p++, 0x0ff0021c); /* jal 870 */ | |
820 | stl_p(p++, 0x00000000); /* nop */ | |
821 | stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ | |
822 | stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */ | |
823 | stl_p(p++, 0x1580fffa); /* bnez t4,84c */ | |
824 | stl_p(p++, 0x00000000); /* nop */ | |
825 | stl_p(p++, 0x01a00009); /* jalr t5 */ | |
826 | stl_p(p++, 0x01602021); /* move a0,t3 */ | |
26ea0918 | 827 | /* 0x870 */ |
dbd07eda FB |
828 | stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */ |
829 | stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */ | |
830 | stl_p(p++, 0x91090005); /* lbu t1,5(t0) */ | |
831 | stl_p(p++, 0x00000000); /* nop */ | |
832 | stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */ | |
833 | stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */ | |
834 | stl_p(p++, 0x00000000); /* nop */ | |
835 | stl_p(p++, 0x03e00009); /* jalr ra */ | |
836 | stl_p(p++, 0xa1040000); /* sb a0,0(t0) */ | |
5856de80 TS |
837 | } |
838 | ||
9edc6313 | 839 | static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index, |
8b7968f7 | 840 | const char *string, ...) |
5856de80 TS |
841 | { |
842 | va_list ap; | |
dde98994 | 843 | uint32_t table_addr; |
5856de80 | 844 | |
94818443 | 845 | if (index >= ENVP_NB_ENTRIES) { |
5856de80 | 846 | return; |
94818443 | 847 | } |
5856de80 | 848 | |
5856de80 | 849 | if (string == NULL) { |
c938ada2 | 850 | prom_buf[index] = 0; |
5856de80 TS |
851 | return; |
852 | } | |
853 | ||
dde98994 | 854 | table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; |
df055c65 | 855 | prom_buf[index] = tswap32(ENVP_VADDR + table_addr); |
5856de80 TS |
856 | |
857 | va_start(ap, string); | |
c938ada2 | 858 | vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap); |
5856de80 TS |
859 | va_end(ap); |
860 | } | |
861 | ||
6233a138 JD |
862 | static void reinitialize_rng_seed(void *opaque) |
863 | { | |
864 | char *rng_seed_hex = opaque; | |
865 | uint8_t rng_seed[32]; | |
866 | ||
867 | qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); | |
868 | for (size_t i = 0; i < sizeof(rng_seed); ++i) { | |
869 | sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]); | |
870 | } | |
871 | } | |
872 | ||
5856de80 | 873 | /* Kernel */ |
dde98994 | 874 | static uint64_t load_kernel(void) |
5856de80 | 875 | { |
dde98994 | 876 | uint64_t kernel_entry, kernel_high, initrd_size; |
f3839fda | 877 | long kernel_size; |
c227f099 | 878 | ram_addr_t initrd_offset; |
c938ada2 AJ |
879 | uint32_t *prom_buf; |
880 | long prom_size; | |
881 | int prom_index = 0; | |
6233a138 JD |
882 | uint8_t rng_seed[32]; |
883 | char rng_seed_hex[sizeof(rng_seed) * 2 + 1]; | |
884 | size_t rng_seed_prom_offset; | |
ca20cf32 | 885 | |
4366e1db LM |
886 | kernel_size = load_elf(loaderparams.kernel_filename, NULL, |
887 | cpu_mips_kseg0_to_phys, NULL, | |
dde98994 | 888 | &kernel_entry, NULL, |
ded625e7 | 889 | &kernel_high, NULL, TARGET_BIG_ENDIAN, EM_MIPS, |
6cdda0ff | 890 | 1, 0); |
3ee3122c | 891 | if (kernel_size < 0) { |
bd6e1d81 | 892 | error_report("could not load kernel '%s': %s", |
3ee3122c AJ |
893 | loaderparams.kernel_filename, |
894 | load_elf_strerror(kernel_size)); | |
acdf72bb | 895 | exit(1); |
5856de80 | 896 | } |
f7f15245 | 897 | |
d3d93c6c | 898 | /* Check where the kernel has been linked */ |
a8448735 PB |
899 | if (kernel_entry <= USEG_LIMIT) { |
900 | error_report("Trap-and-Emul kernels (Linux CONFIG_KVM_GUEST)" | |
901 | " are not supported"); | |
902 | exit(1); | |
b0311811 | 903 | } |
5856de80 TS |
904 | |
905 | /* load initrd */ | |
906 | initrd_size = 0; | |
74287114 | 907 | initrd_offset = 0; |
7df526e3 | 908 | if (loaderparams.initrd_filename) { |
94818443 | 909 | initrd_size = get_image_size(loaderparams.initrd_filename); |
74287114 | 910 | if (initrd_size > 0) { |
94818443 AM |
911 | /* |
912 | * The kernel allocates the bootmap memory in the low memory after | |
913 | * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB | |
914 | * pages. | |
915 | */ | |
acab36ca PMD |
916 | initrd_offset = ROUND_UP(loaderparams.ram_low_size |
917 | - (initrd_size + 128 * KiB), | |
918 | INITRD_PAGE_SIZE); | |
9768e2ab | 919 | if (kernel_high >= initrd_offset) { |
bd6e1d81 AF |
920 | error_report("memory too small for initial ram disk '%s'", |
921 | loaderparams.initrd_filename); | |
74287114 TS |
922 | exit(1); |
923 | } | |
dcac9679 PB |
924 | initrd_size = load_image_targphys(loaderparams.initrd_filename, |
925 | initrd_offset, | |
74d6bf85 | 926 | loaderparams.ram_size - initrd_offset); |
74287114 | 927 | } |
5856de80 | 928 | if (initrd_size == (target_ulong) -1) { |
bd6e1d81 AF |
929 | error_report("could not load initial ram disk '%s'", |
930 | loaderparams.initrd_filename); | |
5856de80 TS |
931 | exit(1); |
932 | } | |
933 | } | |
934 | ||
c938ada2 AJ |
935 | /* Setup prom parameters. */ |
936 | prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE); | |
7267c094 | 937 | prom_buf = g_malloc(prom_size); |
c938ada2 | 938 | |
f36d53ef | 939 | prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename); |
c938ada2 | 940 | if (initrd_size > 0) { |
94818443 AM |
941 | prom_set(prom_buf, prom_index++, |
942 | "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s", | |
a8448735 | 943 | cpu_mips_phys_to_kseg0(NULL, initrd_offset), |
94818443 | 944 | initrd_size, loaderparams.kernel_cmdline); |
c938ada2 | 945 | } else { |
f36d53ef | 946 | prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline); |
c938ada2 AJ |
947 | } |
948 | ||
949 | prom_set(prom_buf, prom_index++, "memsize"); | |
71c199c8 PB |
950 | prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size); |
951 | ||
952 | prom_set(prom_buf, prom_index++, "ememsize"); | |
953 | prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size); | |
b0311811 | 954 | |
c938ada2 AJ |
955 | prom_set(prom_buf, prom_index++, "modetty0"); |
956 | prom_set(prom_buf, prom_index++, "38400n8r"); | |
6233a138 JD |
957 | |
958 | qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); | |
959 | for (size_t i = 0; i < sizeof(rng_seed); ++i) { | |
960 | sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]); | |
961 | } | |
962 | prom_set(prom_buf, prom_index++, "rngseed"); | |
963 | rng_seed_prom_offset = prom_index * ENVP_ENTRY_SIZE + | |
964 | sizeof(uint32_t) * ENVP_NB_ENTRIES; | |
965 | prom_set(prom_buf, prom_index++, "%s", rng_seed_hex); | |
966 | ||
c938ada2 AJ |
967 | prom_set(prom_buf, prom_index++, NULL); |
968 | ||
df055c65 | 969 | rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR); |
6233a138 JD |
970 | qemu_register_reset_nosnapshotload(reinitialize_rng_seed, |
971 | rom_ptr(ENVP_PADDR, prom_size) + rng_seed_prom_offset); | |
5856de80 | 972 | |
3ad9fd5a | 973 | g_free(prom_buf); |
74287114 | 974 | return kernel_entry; |
5856de80 TS |
975 | } |
976 | ||
ce3960eb | 977 | static void malta_mips_config(MIPSCPU *cpu) |
c4cb2578 | 978 | { |
33decbd2 LX |
979 | MachineState *ms = MACHINE(qdev_get_machine()); |
980 | unsigned int smp_cpus = ms->smp.cpus; | |
ce3960eb AF |
981 | CPUMIPSState *env = &cpu->env; |
982 | CPUState *cs = CPU(cpu); | |
983 | ||
8de0f280 | 984 | if (ase_mt_available(env)) { |
07741e67 PMD |
985 | env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, |
986 | CP0MVPC0_PTC, 8, | |
987 | smp_cpus * cs->nr_threads - 1); | |
988 | env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, | |
989 | CP0MVPC0_PVPE, 4, smp_cpus - 1); | |
8de0f280 | 990 | } |
c4cb2578 EI |
991 | } |
992 | ||
3c73d590 BB |
993 | static int malta_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
994 | { | |
995 | int slot; | |
996 | ||
997 | slot = PCI_SLOT(pci_dev->devfn); | |
998 | ||
999 | switch (slot) { | |
1000 | /* PIIX4 USB */ | |
1001 | case 10: | |
1002 | return 3; | |
1003 | /* AMD 79C973 Ethernet */ | |
1004 | case 11: | |
1005 | return 1; | |
1006 | /* Crystal 4281 Sound */ | |
1007 | case 12: | |
1008 | return 2; | |
1009 | /* PCI slot 1 to 4 */ | |
1010 | case 18 ... 21: | |
1011 | return ((slot - 18) + irq_num) & 0x03; | |
1012 | /* Unknown device, don't do any translation */ | |
1013 | default: | |
1014 | return irq_num; | |
1015 | } | |
1016 | } | |
1017 | ||
5856de80 TS |
1018 | static void main_cpu_reset(void *opaque) |
1019 | { | |
1004ee8d AF |
1020 | MIPSCPU *cpu = opaque; |
1021 | CPUMIPSState *env = &cpu->env; | |
1022 | ||
1023 | cpu_reset(CPU(cpu)); | |
5856de80 | 1024 | |
94818443 AM |
1025 | /* |
1026 | * The bootloader does not need to be rewritten as it is located in a | |
1027 | * read only location. The kernel location and the arguments table | |
1028 | * location does not change. | |
1029 | */ | |
7df526e3 | 1030 | if (loaderparams.kernel_filename) { |
d6ca4277 | 1031 | env->CP0_Status &= ~(1 << CP0St_ERL); |
fb82fea0 | 1032 | } |
c4cb2578 | 1033 | |
ce3960eb | 1034 | malta_mips_config(cpu); |
5856de80 TS |
1035 | } |
1036 | ||
eea1f5ba | 1037 | static void create_cpu_without_cps(MachineState *ms, MaltaState *s, |
bff384a4 | 1038 | qemu_irq *cbus_irq, qemu_irq *i8259_irq) |
67a54961 LA |
1039 | { |
1040 | CPUMIPSState *env; | |
1041 | MIPSCPU *cpu; | |
1042 | int i; | |
67a54961 | 1043 | |
a0628599 | 1044 | for (i = 0; i < ms->smp.cpus; i++) { |
eea1f5ba | 1045 | cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk); |
67a54961 LA |
1046 | |
1047 | /* Init internal devices */ | |
5a975d43 PB |
1048 | cpu_mips_irq_init_cpu(cpu); |
1049 | cpu_mips_clock_init(cpu); | |
67a54961 LA |
1050 | qemu_register_reset(main_cpu_reset, cpu); |
1051 | } | |
1052 | ||
1053 | cpu = MIPS_CPU(first_cpu); | |
1054 | env = &cpu->env; | |
1055 | *i8259_irq = env->irq[2]; | |
1056 | *cbus_irq = env->irq[4]; | |
1057 | } | |
1058 | ||
a0628599 | 1059 | static void create_cps(MachineState *ms, MaltaState *s, |
bff384a4 LA |
1060 | qemu_irq *cbus_irq, qemu_irq *i8259_irq) |
1061 | { | |
0074fce6 | 1062 | object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); |
5325cc34 | 1063 | object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, |
a729f9bc | 1064 | &error_fatal); |
10997f2d | 1065 | object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus, |
a729f9bc | 1066 | &error_fatal); |
eea1f5ba | 1067 | qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); |
0074fce6 | 1068 | sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); |
bff384a4 | 1069 | |
2d5fac80 | 1070 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); |
bff384a4 | 1071 | |
2d5fac80 | 1072 | *i8259_irq = get_cps_irq(&s->cps, 3); |
bff384a4 LA |
1073 | *cbus_irq = NULL; |
1074 | } | |
1075 | ||
a0628599 | 1076 | static void mips_create_cpu(MachineState *ms, MaltaState *s, |
a7519f2b | 1077 | qemu_irq *cbus_irq, qemu_irq *i8259_irq) |
bff384a4 | 1078 | { |
ac70f976 | 1079 | if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) { |
a0628599 | 1080 | create_cps(ms, s, cbus_irq, i8259_irq); |
bff384a4 | 1081 | } else { |
eea1f5ba | 1082 | create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); |
bff384a4 LA |
1083 | } |
1084 | } | |
1085 | ||
70705261 | 1086 | static |
3ef96221 | 1087 | void mips_malta_init(MachineState *machine) |
5856de80 | 1088 | { |
3ef96221 | 1089 | ram_addr_t ram_size = machine->ram_size; |
b0311811 | 1090 | ram_addr_t ram_low_size; |
3ef96221 MA |
1091 | const char *kernel_filename = machine->kernel_filename; |
1092 | const char *kernel_cmdline = machine->kernel_cmdline; | |
1093 | const char *initrd_filename = machine->initrd_filename; | |
5cea8590 | 1094 | char *filename; |
16434065 | 1095 | PFlashCFI01 *fl; |
cfe5f011 | 1096 | MemoryRegion *system_memory = get_system_memory(); |
94c2b6af PB |
1097 | MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1); |
1098 | MemoryRegion *ram_low_postio; | |
a427338b | 1099 | MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); |
35c64807 PB |
1100 | const size_t smbus_eeprom_size = 8 * 256; |
1101 | uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); | |
dde98994 | 1102 | uint64_t kernel_entry, bootloader_run_addr; |
5856de80 | 1103 | PCIBus *pci_bus; |
48a18b3c | 1104 | ISABus *isa_bus; |
67a54961 | 1105 | qemu_irq cbus_irq, i8259_irq; |
a5c82852 | 1106 | I2CBus *smbus; |
751c6a17 | 1107 | DriveInfo *dinfo; |
c8b153d7 | 1108 | int fl_idx = 0; |
8df525a5 | 1109 | MaltaState *s; |
e8ebf549 | 1110 | PCIDevice *piix4; |
8df525a5 | 1111 | DeviceState *dev; |
5856de80 | 1112 | |
8df525a5 PMD |
1113 | s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA)); |
1114 | sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); | |
e9b40fd3 | 1115 | |
bff384a4 | 1116 | /* create CPU */ |
a0628599 | 1117 | mips_create_cpu(machine, s, &cbus_irq, &i8259_irq); |
5856de80 TS |
1118 | |
1119 | /* allocate RAM */ | |
be01029e PMD |
1120 | if (ram_size > 2 * GiB) { |
1121 | error_report("Too much memory for this machine: %" PRId64 "MB," | |
1122 | " maximum 2048MB", ram_size / MiB); | |
0ccff151 AJ |
1123 | exit(1); |
1124 | } | |
94c2b6af PB |
1125 | |
1126 | /* register RAM at high address where it is undisturbed by IO */ | |
3a6e6ac7 | 1127 | memory_region_add_subregion(system_memory, 0x80000000, machine->ram); |
94c2b6af PB |
1128 | |
1129 | /* alias for pre IO hole access */ | |
1130 | memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram", | |
3a6e6ac7 | 1131 | machine->ram, 0, MIN(ram_size, 256 * MiB)); |
94c2b6af PB |
1132 | memory_region_add_subregion(system_memory, 0, ram_low_preio); |
1133 | ||
1134 | /* alias for post IO hole access, if there is enough RAM */ | |
be01029e | 1135 | if (ram_size > 512 * MiB) { |
94c2b6af PB |
1136 | ram_low_postio = g_new(MemoryRegion, 1); |
1137 | memory_region_init_alias(ram_low_postio, NULL, | |
1138 | "mips_malta_low_postio.ram", | |
3a6e6ac7 | 1139 | machine->ram, 512 * MiB, |
be01029e PMD |
1140 | ram_size - 512 * MiB); |
1141 | memory_region_add_subregion(system_memory, 512 * MiB, | |
1142 | ram_low_postio); | |
94c2b6af | 1143 | } |
5856de80 | 1144 | |
070ce5ed | 1145 | /* FPGA */ |
7313b1f2 | 1146 | |
68d00192 | 1147 | /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ |
9bca0edb | 1148 | malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2)); |
070ce5ed | 1149 | |
bb4b3358 SW |
1150 | /* Load firmware in flash / BIOS. */ |
1151 | dinfo = drive_get(IF_PFLASH, 0, fl_idx); | |
940d5b13 | 1152 | fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios", |
7ebfece5 | 1153 | FLASH_SIZE, |
4be74634 | 1154 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
ce14710f | 1155 | 65536, |
ded625e7 TH |
1156 | 4, 0x0000, 0x0000, 0x0000, 0x0000, |
1157 | TARGET_BIG_ENDIAN); | |
bb4b3358 SW |
1158 | bios = pflash_cfi01_get_memory(fl); |
1159 | fl_idx++; | |
c8b153d7 | 1160 | if (kernel_filename) { |
be01029e | 1161 | ram_low_size = MIN(ram_size, 256 * MiB); |
a8448735 | 1162 | bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS); |
b0311811 | 1163 | |
c8b153d7 | 1164 | /* Write a small bootloader to the flash location. */ |
71c199c8 PB |
1165 | loaderparams.ram_size = ram_size; |
1166 | loaderparams.ram_low_size = ram_low_size; | |
c8b153d7 TS |
1167 | loaderparams.kernel_filename = kernel_filename; |
1168 | loaderparams.kernel_cmdline = kernel_cmdline; | |
1169 | loaderparams.initrd_filename = initrd_filename; | |
e16ad5b0 | 1170 | kernel_entry = load_kernel(); |
b0311811 | 1171 | |
ac70f976 | 1172 | if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { |
ce3940cc MF |
1173 | write_bootloader(memory_region_get_ram_ptr(bios), |
1174 | bootloader_run_addr, kernel_entry); | |
1175 | } else { | |
1176 | write_bootloader_nanomips(memory_region_get_ram_ptr(bios), | |
1177 | bootloader_run_addr, kernel_entry); | |
1178 | } | |
c8b153d7 | 1179 | } else { |
74c02ebd | 1180 | target_long bios_size = FLASH_SIZE; |
bb4b3358 SW |
1181 | /* Load firmware from flash. */ |
1182 | if (!dinfo) { | |
c8b153d7 | 1183 | /* Load a BIOS image. */ |
a4374f86 | 1184 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, |
59588bea | 1185 | machine->firmware ?: BIOS_FILENAME); |
5cea8590 | 1186 | if (filename) { |
03a1a8e1 | 1187 | bios_size = load_image_targphys(filename, FLASH_ADDRESS, |
5cea8590 | 1188 | BIOS_SIZE); |
7267c094 | 1189 | g_free(filename); |
5cea8590 PB |
1190 | } else { |
1191 | bios_size = -1; | |
1192 | } | |
2c57bd9b | 1193 | if ((bios_size < 0 || bios_size > BIOS_SIZE) && |
59588bea PB |
1194 | machine->firmware && !qtest_enabled()) { |
1195 | error_report("Could not load MIPS bios '%s'", machine->firmware); | |
2e985fe0 | 1196 | exit(1); |
c8b153d7 | 1197 | } |
070ce5ed | 1198 | } |
94818443 AM |
1199 | /* |
1200 | * In little endian mode the 32bit words in the bios are swapped, | |
1201 | * a neat trick which allows bi-endian firmware. | |
1202 | */ | |
ee3eb3a7 | 1203 | #if !TARGET_BIG_ENDIAN |
3187ef03 | 1204 | { |
0f0f8b61 TH |
1205 | uint32_t *end, *addr; |
1206 | const size_t swapsize = MIN(bios_size, 0x3e0000); | |
1207 | addr = rom_ptr(FLASH_ADDRESS, swapsize); | |
a2b8813d PB |
1208 | if (!addr) { |
1209 | addr = memory_region_get_ram_ptr(bios); | |
1210 | } | |
0f0f8b61 | 1211 | end = (void *)addr + swapsize; |
d7585251 PB |
1212 | while (addr < end) { |
1213 | bswap32s(addr); | |
a30cfee5 | 1214 | addr++; |
3187ef03 TS |
1215 | } |
1216 | } | |
1217 | #endif | |
070ce5ed TS |
1218 | } |
1219 | ||
a427338b PB |
1220 | /* |
1221 | * Map the BIOS at a 2nd physical location, as on the real board. | |
1222 | * Copy it so that we can patch in the MIPS revision, which cannot be | |
1223 | * handled by an overlapping region as the resulting ROM code subpage | |
1224 | * regions are not executable. | |
1225 | */ | |
917b77f5 | 1226 | memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE, |
f8ed85ac | 1227 | &error_fatal); |
a427338b | 1228 | if (!rom_copy(memory_region_get_ram_ptr(bios_copy), |
f05d4d94 | 1229 | FLASH_ADDRESS, BIOS_SIZE)) { |
a427338b | 1230 | memcpy(memory_region_get_ram_ptr(bios_copy), |
f05d4d94 | 1231 | memory_region_get_ram_ptr(bios), BIOS_SIZE); |
a427338b PB |
1232 | } |
1233 | memory_region_set_readonly(bios_copy, true); | |
1234 | memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy); | |
82a9807b | 1235 | |
a427338b PB |
1236 | /* Board ID = 0x420 (Malta Board with CoreLV) */ |
1237 | stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); | |
5856de80 | 1238 | |
5856de80 | 1239 | /* Northbridge */ |
fae45dd5 | 1240 | dev = qdev_new("gt64120"); |
ded625e7 | 1241 | qdev_prop_set_bit(dev, "cpu-little-endian", !TARGET_BIG_ENDIAN); |
fae45dd5 | 1242 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
aa85a461 | 1243 | pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); |
3c73d590 | 1244 | pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq); |
5856de80 TS |
1245 | |
1246 | /* Southbridge */ | |
2922dbc2 BB |
1247 | piix4 = pci_new_multifunction(PIIX4_PCI_DEVFN, TYPE_PIIX4_PCI_DEVICE); |
1248 | qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); | |
1249 | pci_realize_and_unref(piix4, pci_bus, &error_fatal); | |
d240d3fb BB |
1250 | isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); |
1251 | ||
1252 | dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide")); | |
1253 | pci_ide_create_devs(PCI_DEVICE(dev)); | |
5632ae46 | 1254 | |
078778c5 | 1255 | /* Interrupt controller */ |
d240d3fb | 1256 | qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); |
5632ae46 | 1257 | |
78f16256 | 1258 | /* generate SPD EEPROM data */ |
e5b6c3e2 BB |
1259 | dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); |
1260 | smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c")); | |
78f16256 PMD |
1261 | generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); |
1262 | generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); | |
1263 | smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); | |
1264 | g_free(smbus_eeprom_buf); | |
5856de80 | 1265 | |
7313b1f2 PMD |
1266 | /* Super I/O: SMS FDC37M817 */ |
1267 | isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO); | |
5856de80 | 1268 | |
5856de80 | 1269 | /* Network card */ |
29b358f9 | 1270 | network_init(pci_bus); |
11f29511 TS |
1271 | |
1272 | /* Optional PCI video card */ | |
9c59864d | 1273 | pci_vga_init(pci_bus); |
5856de80 TS |
1274 | } |
1275 | ||
eea1f5ba PMD |
1276 | static void mips_malta_instance_init(Object *obj) |
1277 | { | |
1278 | MaltaState *s = MIPS_MALTA(obj); | |
1279 | ||
1280 | s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); | |
1281 | clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */ | |
1282 | } | |
1283 | ||
8c43a6f0 | 1284 | static const TypeInfo mips_malta_device = { |
cba5cb67 | 1285 | .name = TYPE_MIPS_MALTA, |
39bffca2 AL |
1286 | .parent = TYPE_SYS_BUS_DEVICE, |
1287 | .instance_size = sizeof(MaltaState), | |
eea1f5ba | 1288 | .instance_init = mips_malta_instance_init, |
e9b40fd3 SW |
1289 | }; |
1290 | ||
bd64c210 IM |
1291 | GlobalProperty malta_compat[] = { |
1292 | { "PIIX4_PM", "memory-hotplug-support", "off" }, | |
1293 | { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, | |
1294 | { "PIIX4_PM", "acpi-root-pci-hotplug", "off" }, | |
1295 | { "PIIX4_PM", "x-not-migrate-acpi-index", "true" }, | |
1296 | }; | |
1297 | const size_t malta_compat_len = G_N_ELEMENTS(malta_compat); | |
1298 | ||
e264d29d | 1299 | static void mips_malta_machine_init(MachineClass *mc) |
e9b40fd3 | 1300 | { |
e264d29d EH |
1301 | mc->desc = "MIPS Malta Core LV"; |
1302 | mc->init = mips_malta_init; | |
2059839b | 1303 | mc->block_default_type = IF_IDE; |
e264d29d | 1304 | mc->max_cpus = 16; |
ea0ac7f6 | 1305 | mc->is_default = true; |
a7519f2b IM |
1306 | #ifdef TARGET_MIPS64 |
1307 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc"); | |
1308 | #else | |
1309 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); | |
1310 | #endif | |
3a6e6ac7 | 1311 | mc->default_ram_id = "mips_malta.ram"; |
bd64c210 | 1312 | compat_props_add(mc->compat_props, malta_compat, malta_compat_len); |
e9b40fd3 SW |
1313 | } |
1314 | ||
e264d29d EH |
1315 | DEFINE_MACHINE("malta", mips_malta_machine_init) |
1316 | ||
1317 | static void mips_malta_register_types(void) | |
f80f9ec9 | 1318 | { |
e264d29d | 1319 | type_register_static(&mips_malta_device); |
f80f9ec9 AL |
1320 | } |
1321 | ||
83f7d43a | 1322 | type_init(mips_malta_register_types) |