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Commit | Line | Data |
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051c190b HC |
1 | /* |
2 | * QEMU fulong 2e mini pc support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) | |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
7 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
051c190b HC |
11 | */ |
12 | ||
13 | /* | |
14 | * Fulong 2e mini pc is based on ICT/ST Loongson 2e CPU (MIPS III like, 800MHz) | |
15 | * http://www.linux-mips.org/wiki/Fulong | |
16 | * | |
17 | * Loongson 2e user manual: | |
18 | * http://www.loongsondeveloper.com/doc/Loongson2EUserGuide.pdf | |
19 | */ | |
20 | ||
83c9f4ca | 21 | #include "hw/hw.h" |
0d09e41a PB |
22 | #include "hw/i386/pc.h" |
23 | #include "hw/char/serial.h" | |
24 | #include "hw/block/fdc.h" | |
1422e32d | 25 | #include "net/net.h" |
83c9f4ca | 26 | #include "hw/boards.h" |
0d09e41a | 27 | #include "hw/i2c/smbus.h" |
4be74634 | 28 | #include "sysemu/block-backend.h" |
0d09e41a PB |
29 | #include "hw/block/flash.h" |
30 | #include "hw/mips/mips.h" | |
31 | #include "hw/mips/cpudevs.h" | |
83c9f4ca | 32 | #include "hw/pci/pci.h" |
dccfcd0e | 33 | #include "sysemu/char.h" |
9c17d615 | 34 | #include "sysemu/sysemu.h" |
051c190b | 35 | #include "audio/audio.h" |
1de7afc9 | 36 | #include "qemu/log.h" |
83c9f4ca | 37 | #include "hw/loader.h" |
0d09e41a | 38 | #include "hw/mips/bios.h" |
83c9f4ca | 39 | #include "hw/ide.h" |
051c190b | 40 | #include "elf.h" |
0d09e41a PB |
41 | #include "hw/isa/vt82c686.h" |
42 | #include "hw/timer/mc146818rtc.h" | |
43 | #include "hw/timer/i8254.h" | |
9c17d615 | 44 | #include "sysemu/blockdev.h" |
022c62cb | 45 | #include "exec/address-spaces.h" |
4a7ed999 | 46 | #include "sysemu/qtest.h" |
2e985fe0 | 47 | #include "qemu/error-report.h" |
051c190b HC |
48 | |
49 | #define DEBUG_FULONG2E_INIT | |
50 | ||
51 | #define ENVP_ADDR 0x80002000l | |
52 | #define ENVP_NB_ENTRIES 16 | |
53 | #define ENVP_ENTRY_SIZE 256 | |
54 | ||
55 | #define MAX_IDE_BUS 2 | |
56 | ||
57 | /* | |
58 | * PMON is not part of qemu and released with BSD license, anyone | |
59 | * who want to build a pmon binary please first git-clone the source | |
60 | * from the git repository at: | |
61 | * http://www.loongson.cn/support/git/pmon | |
62 | * Then follow the "Compile Guide" available at: | |
63 | * http://dev.lemote.com/code/pmon | |
64 | * | |
65 | * Notes: | |
66 | * 1, don't use the source at http://dev.lemote.com/http_git/pmon.git | |
67 | * 2, use "Bonito2edev" to replace "dir_corresponding_to_your_target_hardware" | |
68 | * in the "Compile Guide". | |
69 | */ | |
70 | #define FULONG_BIOSNAME "pmon_fulong2e.bin" | |
71 | ||
72 | /* PCI SLOT in fulong 2e */ | |
73 | #define FULONG2E_VIA_SLOT 5 | |
74 | #define FULONG2E_ATI_SLOT 6 | |
75 | #define FULONG2E_RTL8139_SLOT 7 | |
76 | ||
64d7e9a4 | 77 | static ISADevice *pit; |
051c190b HC |
78 | |
79 | static struct _loaderparams { | |
80 | int ram_size; | |
81 | const char *kernel_filename; | |
82 | const char *kernel_cmdline; | |
83 | const char *initrd_filename; | |
84 | } loaderparams; | |
85 | ||
8b7968f7 SW |
86 | static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index, |
87 | const char *string, ...) | |
051c190b HC |
88 | { |
89 | va_list ap; | |
90 | int32_t table_addr; | |
91 | ||
92 | if (index >= ENVP_NB_ENTRIES) | |
93 | return; | |
94 | ||
95 | if (string == NULL) { | |
96 | prom_buf[index] = 0; | |
97 | return; | |
98 | } | |
99 | ||
100 | table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; | |
101 | prom_buf[index] = tswap32(ENVP_ADDR + table_addr); | |
102 | ||
103 | va_start(ap, string); | |
104 | vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap); | |
105 | va_end(ap); | |
106 | } | |
107 | ||
61c56c8c | 108 | static int64_t load_kernel (CPUMIPSState *env) |
051c190b HC |
109 | { |
110 | int64_t kernel_entry, kernel_low, kernel_high; | |
111 | int index = 0; | |
112 | long initrd_size; | |
113 | ram_addr_t initrd_offset; | |
114 | uint32_t *prom_buf; | |
115 | long prom_size; | |
116 | ||
117 | if (load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL, | |
118 | (uint64_t *)&kernel_entry, (uint64_t *)&kernel_low, | |
119 | (uint64_t *)&kernel_high, 0, ELF_MACHINE, 1) < 0) { | |
120 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
121 | loaderparams.kernel_filename); | |
122 | exit(1); | |
123 | } | |
124 | ||
125 | /* load initrd */ | |
126 | initrd_size = 0; | |
127 | initrd_offset = 0; | |
128 | if (loaderparams.initrd_filename) { | |
129 | initrd_size = get_image_size (loaderparams.initrd_filename); | |
130 | if (initrd_size > 0) { | |
05b3274b | 131 | initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK; |
051c190b HC |
132 | if (initrd_offset + initrd_size > ram_size) { |
133 | fprintf(stderr, | |
134 | "qemu: memory too small for initial ram disk '%s'\n", | |
135 | loaderparams.initrd_filename); | |
136 | exit(1); | |
137 | } | |
138 | initrd_size = load_image_targphys(loaderparams.initrd_filename, | |
139 | initrd_offset, ram_size - initrd_offset); | |
140 | } | |
141 | if (initrd_size == (target_ulong) -1) { | |
142 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
143 | loaderparams.initrd_filename); | |
144 | exit(1); | |
145 | } | |
146 | } | |
147 | ||
148 | /* Setup prom parameters. */ | |
149 | prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE); | |
7267c094 | 150 | prom_buf = g_malloc(prom_size); |
051c190b | 151 | |
1ed1139d | 152 | prom_set(prom_buf, index++, "%s", loaderparams.kernel_filename); |
051c190b | 153 | if (initrd_size > 0) { |
1ed1139d | 154 | prom_set(prom_buf, index++, "rd_start=0x%" PRIx64 " rd_size=%li %s", |
051c190b HC |
155 | cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size, |
156 | loaderparams.kernel_cmdline); | |
157 | } else { | |
1ed1139d | 158 | prom_set(prom_buf, index++, "%s", loaderparams.kernel_cmdline); |
051c190b HC |
159 | } |
160 | ||
161 | /* Setup minimum environment variables */ | |
162 | prom_set(prom_buf, index++, "busclock=33000000"); | |
163 | prom_set(prom_buf, index++, "cpuclock=100000000"); | |
164 | prom_set(prom_buf, index++, "memsize=%i", loaderparams.ram_size/1024/1024); | |
165 | prom_set(prom_buf, index++, "modetty0=38400n8r"); | |
166 | prom_set(prom_buf, index++, NULL); | |
167 | ||
168 | rom_add_blob_fixed("prom", prom_buf, prom_size, | |
169 | cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR)); | |
170 | ||
3ad9fd5a | 171 | g_free(prom_buf); |
051c190b HC |
172 | return kernel_entry; |
173 | } | |
174 | ||
61c56c8c | 175 | static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_addr) |
051c190b HC |
176 | { |
177 | uint32_t *p; | |
178 | ||
179 | /* Small bootloader */ | |
180 | p = (uint32_t *) base; | |
181 | ||
0983979b PB |
182 | stl_p(p++, 0x0bf00010); /* j 0x1fc00040 */ |
183 | stl_p(p++, 0x00000000); /* nop */ | |
051c190b HC |
184 | |
185 | /* Second part of the bootloader */ | |
186 | p = (uint32_t *) (base + 0x040); | |
187 | ||
0983979b PB |
188 | stl_p(p++, 0x3c040000); /* lui a0, 0 */ |
189 | stl_p(p++, 0x34840002); /* ori a0, a0, 2 */ | |
190 | stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */ | |
191 | stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */ | |
192 | stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */ | |
193 | stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */ | |
194 | stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(env->ram_size) */ | |
195 | stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */ | |
196 | stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff)); /* lui ra, high(kernel_addr) */; | |
197 | stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff)); /* ori ra, ra, low(kernel_addr) */ | |
198 | stl_p(p++, 0x03e00008); /* jr ra */ | |
199 | stl_p(p++, 0x00000000); /* nop */ | |
051c190b HC |
200 | } |
201 | ||
202 | ||
203 | static void main_cpu_reset(void *opaque) | |
204 | { | |
800cf598 AF |
205 | MIPSCPU *cpu = opaque; |
206 | CPUMIPSState *env = &cpu->env; | |
051c190b | 207 | |
800cf598 | 208 | cpu_reset(CPU(cpu)); |
051c190b HC |
209 | /* TODO: 2E reset stuff */ |
210 | if (loaderparams.kernel_filename) { | |
211 | env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); | |
212 | } | |
213 | } | |
214 | ||
f73cdbc6 | 215 | static const uint8_t eeprom_spd[0x80] = { |
051c190b HC |
216 | 0x80,0x08,0x07,0x0d,0x09,0x02,0x40,0x00,0x04,0x70, |
217 | 0x70,0x00,0x82,0x10,0x00,0x01,0x0e,0x04,0x0c,0x01, | |
218 | 0x02,0x20,0x80,0x75,0x70,0x00,0x00,0x50,0x3c,0x50, | |
219 | 0x2d,0x20,0xb0,0xb0,0x50,0x50,0x00,0x00,0x00,0x00, | |
220 | 0x00,0x41,0x48,0x3c,0x32,0x75,0x00,0x00,0x00,0x00, | |
221 | 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, | |
222 | 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, | |
223 | 0x00,0x00,0x00,0x9c,0x7b,0x07,0x00,0x00,0x00,0x00, | |
224 | 0x00,0x00,0x00,0x00,0x48,0x42,0x35,0x34,0x41,0x32, | |
225 | 0x35,0x36,0x38,0x4b,0x4e,0x2d,0x41,0x37,0x35,0x42, | |
226 | 0x20,0x30,0x20 | |
227 | }; | |
228 | ||
229 | /* Audio support */ | |
051c190b HC |
230 | static void audio_init (PCIBus *pci_bus) |
231 | { | |
7899f799 IY |
232 | vt82c686b_ac97_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 5)); |
233 | vt82c686b_mc97_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 6)); | |
051c190b | 234 | } |
051c190b HC |
235 | |
236 | /* Network support */ | |
29b358f9 | 237 | static void network_init (PCIBus *pci_bus) |
051c190b HC |
238 | { |
239 | int i; | |
240 | ||
241 | for(i = 0; i < nb_nics; i++) { | |
242 | NICInfo *nd = &nd_table[i]; | |
243 | const char *default_devaddr = NULL; | |
244 | ||
245 | if (i == 0 && (!nd->model || strcmp(nd->model, "rtl8139") == 0)) { | |
246 | /* The fulong board has a RTL8139 card using PCI SLOT 7 */ | |
247 | default_devaddr = "07"; | |
248 | } | |
249 | ||
29b358f9 | 250 | pci_nic_init_nofail(nd, pci_bus, "rtl8139", default_devaddr); |
051c190b HC |
251 | } |
252 | } | |
253 | ||
3ef96221 | 254 | static void mips_fulong2e_init(MachineState *machine) |
051c190b | 255 | { |
3ef96221 MA |
256 | ram_addr_t ram_size = machine->ram_size; |
257 | const char *cpu_model = machine->cpu_model; | |
258 | const char *kernel_filename = machine->kernel_filename; | |
259 | const char *kernel_cmdline = machine->kernel_cmdline; | |
260 | const char *initrd_filename = machine->initrd_filename; | |
051c190b | 261 | char *filename; |
13faf2a7 AK |
262 | MemoryRegion *address_space_mem = get_system_memory(); |
263 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
264 | MemoryRegion *bios = g_new(MemoryRegion, 1); | |
093209cd | 265 | long bios_size; |
051c190b HC |
266 | int64_t kernel_entry; |
267 | qemu_irq *i8259; | |
051c190b | 268 | PCIBus *pci_bus; |
48a18b3c | 269 | ISABus *isa_bus; |
a5c82852 | 270 | I2CBus *smbus; |
051c190b | 271 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
f0f80366 | 272 | MIPSCPU *cpu; |
61c56c8c | 273 | CPUMIPSState *env; |
051c190b HC |
274 | |
275 | /* init CPUs */ | |
276 | if (cpu_model == NULL) { | |
277 | cpu_model = "Loongson-2E"; | |
278 | } | |
f0f80366 AF |
279 | cpu = cpu_mips_init(cpu_model); |
280 | if (cpu == NULL) { | |
051c190b HC |
281 | fprintf(stderr, "Unable to find CPU definition\n"); |
282 | exit(1); | |
283 | } | |
f0f80366 | 284 | env = &cpu->env; |
051c190b | 285 | |
800cf598 | 286 | qemu_register_reset(main_cpu_reset, cpu); |
051c190b HC |
287 | |
288 | /* fulong 2e has 256M ram. */ | |
289 | ram_size = 256 * 1024 * 1024; | |
290 | ||
291 | /* fulong 2e has a 1M flash.Winbond W39L040AP70Z */ | |
292 | bios_size = 1024 * 1024; | |
293 | ||
294 | /* allocate RAM */ | |
6a926fbc | 295 | memory_region_allocate_system_memory(ram, NULL, "fulong2e.ram", ram_size); |
49946538 | 296 | memory_region_init_ram(bios, NULL, "fulong2e.bios", bios_size, |
f8ed85ac | 297 | &error_fatal); |
c5705a77 | 298 | vmstate_register_ram_global(bios); |
13faf2a7 | 299 | memory_region_set_readonly(bios, true); |
051c190b | 300 | |
13faf2a7 AK |
301 | memory_region_add_subregion(address_space_mem, 0, ram); |
302 | memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios); | |
051c190b HC |
303 | |
304 | /* We do not support flash operation, just loading pmon.bin as raw BIOS. | |
305 | * Please use -L to set the BIOS path and -bios to set bios name. */ | |
306 | ||
307 | if (kernel_filename) { | |
308 | loaderparams.ram_size = ram_size; | |
309 | loaderparams.kernel_filename = kernel_filename; | |
310 | loaderparams.kernel_cmdline = kernel_cmdline; | |
311 | loaderparams.initrd_filename = initrd_filename; | |
312 | kernel_entry = load_kernel (env); | |
13faf2a7 | 313 | write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry); |
051c190b | 314 | } else { |
33dd2983 AJ |
315 | if (bios_name == NULL) { |
316 | bios_name = FULONG_BIOSNAME; | |
051c190b HC |
317 | } |
318 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
319 | if (filename) { | |
320 | bios_size = load_image_targphys(filename, 0x1fc00000LL, | |
321 | BIOS_SIZE); | |
7267c094 | 322 | g_free(filename); |
051c190b HC |
323 | } else { |
324 | bios_size = -1; | |
325 | } | |
326 | ||
4a7ed999 AF |
327 | if ((bios_size < 0 || bios_size > BIOS_SIZE) && |
328 | !kernel_filename && !qtest_enabled()) { | |
2e985fe0 AJ |
329 | error_report("Could not load MIPS bios '%s'", bios_name); |
330 | exit(1); | |
33dd2983 | 331 | } |
051c190b HC |
332 | } |
333 | ||
334 | /* Init internal devices */ | |
335 | cpu_mips_irq_init_cpu(env); | |
336 | cpu_mips_clock_init(env); | |
337 | ||
051c190b HC |
338 | /* North bridge, Bonito --> IP2 */ |
339 | pci_bus = bonito_init((qemu_irq *)&(env->irq[2])); | |
340 | ||
341 | /* South bridge */ | |
d8f94e1b | 342 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
051c190b | 343 | |
c9940edb HP |
344 | isa_bus = vt82c686b_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 0)); |
345 | if (!isa_bus) { | |
b2bedb21 | 346 | fprintf(stderr, "vt82c686b_init error\n"); |
051c190b HC |
347 | exit(1); |
348 | } | |
349 | ||
7e17a217 JK |
350 | /* Interrupt controller */ |
351 | /* The 8259 -> IP5 */ | |
48a18b3c HP |
352 | i8259 = i8259_init(isa_bus, env->irq[5]); |
353 | isa_bus_irqs(isa_bus, i8259); | |
7e17a217 | 354 | |
7899f799 | 355 | vt82c686b_ide_init(pci_bus, hd, PCI_DEVFN(FULONG2E_VIA_SLOT, 1)); |
afb9a60e GH |
356 | pci_create_simple(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 2), |
357 | "vt82c686b-usb-uhci"); | |
358 | pci_create_simple(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 3), | |
359 | "vt82c686b-usb-uhci"); | |
051c190b | 360 | |
7899f799 | 361 | smbus = vt82c686b_pm_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 4), |
051c190b | 362 | 0xeee1, NULL); |
051c190b | 363 | /* TODO: Populate SPD eeprom data. */ |
a88df0b9 | 364 | smbus_eeprom_init(smbus, 1, eeprom_spd, sizeof(eeprom_spd)); |
051c190b HC |
365 | |
366 | /* init other devices */ | |
319ba9f5 | 367 | pit = pit_init(isa_bus, 0x40, 0, NULL); |
5039d6e2 | 368 | DMA_init(0); |
051c190b HC |
369 | |
370 | /* Super I/O */ | |
48a18b3c | 371 | isa_create_simple(isa_bus, "i8042"); |
051c190b | 372 | |
48a18b3c | 373 | rtc_init(isa_bus, 2000, NULL); |
051c190b | 374 | |
b6607a1a | 375 | serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); |
07dc7880 | 376 | parallel_hds_isa_init(isa_bus, 1); |
051c190b HC |
377 | |
378 | /* Sound card */ | |
051c190b | 379 | audio_init(pci_bus); |
051c190b | 380 | /* Network card */ |
29b358f9 | 381 | network_init(pci_bus); |
051c190b HC |
382 | } |
383 | ||
da665c99 | 384 | static QEMUMachine mips_fulong2e_machine = { |
051c190b HC |
385 | .name = "fulong2e", |
386 | .desc = "Fulong 2e mini pc", | |
387 | .init = mips_fulong2e_init, | |
388 | }; | |
389 | ||
390 | static void mips_fulong2e_machine_init(void) | |
391 | { | |
392 | qemu_register_machine(&mips_fulong2e_machine); | |
393 | } | |
394 | ||
395 | machine_init(mips_fulong2e_machine_init); |