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7b9cbadb
AJ
1/*
2 * QEMU MIPS interrupt support
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
c684822a 23#include "qemu/osdep.h"
215581bd 24#include "qemu/main-loop.h"
64552b6b 25#include "hw/irq.h"
0d09e41a 26#include "hw/mips/cpudevs.h"
b1bd8b28
SL
27#include "sysemu/kvm.h"
28#include "kvm_mips.h"
4de9b249 29
d537cf6c 30static void cpu_mips_irq_request(void *opaque, int irq, int level)
4de9b249 31{
d8ed887b
AF
32 MIPSCPU *cpu = opaque;
33 CPUMIPSState *env = &cpu->env;
34 CPUState *cs = CPU(cpu);
215581bd 35 bool locked = false;
4de9b249 36
6c06ea4c 37 if (irq < 0 || irq > 7) {
4de9b249 38 return;
6c06ea4c 39 }
4de9b249 40
215581bd
AM
41 /* Make sure locking works even if BQL is already held by the caller */
42 if (!qemu_mutex_iothread_locked()) {
43 locked = true;
44 qemu_mutex_lock_iothread();
45 }
46
4de9b249 47 if (level) {
39d51eb8 48 env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
4de9b249 49 } else {
a4bc3afc 50 env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
56b92eee 51 }
b1bd8b28 52
c3173a35 53 if (kvm_enabled() && (irq == 2 || irq == 3)) {
56b92eee 54 kvm_mips_set_interrupt(cpu, irq, level);
4de9b249 55 }
36388314
EI
56
57 if (env->CP0_Cause & CP0Ca_IP_mask) {
c3affe56 58 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
36388314 59 } else {
d8ed887b 60 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
36388314 61 }
215581bd
AM
62
63 if (locked) {
64 qemu_mutex_unlock_iothread();
65 }
4de9b249 66}
d537cf6c 67
5a975d43 68void cpu_mips_irq_init_cpu(MIPSCPU *cpu)
d537cf6c 69{
5a975d43 70 CPUMIPSState *env = &cpu->env;
d537cf6c
PB
71 qemu_irq *qi;
72 int i;
73
0009b4f3 74 qi = qemu_allocate_irqs(cpu_mips_irq_request, cpu, 8);
d537cf6c
PB
75 for (i = 0; i < 8; i++) {
76 env->irq[i] = qi[i];
77 }
0287d89f 78 g_free(qi);
d537cf6c 79}
5dc5d9f0 80
61c56c8c 81void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
5dc5d9f0
AJ
82{
83 if (irq < 0 || irq > 2) {
84 return;
85 }
86
87 qemu_set_irq(env->irq[irq], level);
88}