[mirror_qemu.git] / hw / mips / mips_jazz.c

/*
 * QEMU MIPS Jazz support
 *
 * Copyright (c) 2007-2008 Hervé Poussineau
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
#include "hw/i386/pc.h"
#include "hw/dma/i8257.h"
#include "hw/char/serial.h"
#include "hw/char/parallel.h"
#include "hw/isa/isa.h"
#include "hw/block/fdc.h"
#include "sysemu/sysemu.h"
#include "sysemu/arch_init.h"
#include "hw/boards.h"
#include "net/net.h"
#include "hw/scsi/esp.h"
#include "hw/mips/bios.h"
#include "hw/loader.h"
#include "hw/timer/mc146818rtc.h"
#include "hw/timer/i8254.h"
#include "hw/display/vga.h"
#include "hw/audio/pcspk.h"
#include "hw/input/i8042.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/help_option.h"

enum jazz_model_e
{
    JAZZ_MAGNUM,
    JAZZ_PICA61,
};

static void main_cpu_reset(void *opaque)
{
    MIPSCPU *cpu = opaque;

    cpu_reset(CPU(cpu));
}

static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
{
    uint8_t val;
    address_space_read(&address_space_memory, 0x90000071,
                       MEMTXATTRS_UNSPECIFIED, &val, 1);
    return val;
}

static void rtc_write(void *opaque, hwaddr addr,
                      uint64_t val, unsigned size)
{
    uint8_t buf = val & 0xff;
    address_space_write(&address_space_memory, 0x90000071,
                        MEMTXATTRS_UNSPECIFIED, &buf, 1);
}

static const MemoryRegionOps rtc_ops = {
    .read = rtc_read,
    .write = rtc_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
                               unsigned size)
{
    /* Nothing to do. That is only to ensure that
     * the current DMA acknowledge cycle is completed. */
    return 0xff;
}

static void dma_dummy_write(void *opaque, hwaddr addr,
                            uint64_t val, unsigned size)
{
    /* Nothing to do. That is only to ensure that
     * the current DMA acknowledge cycle is completed. */
}

static const MemoryRegionOps dma_dummy_ops = {
    .read = dma_dummy_read,
    .write = dma_dummy_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)

static CPUUnassignedAccess real_do_unassigned_access;
static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
                                           bool is_write, bool is_exec,
                                           int opaque, unsigned size)
{
    if (!is_exec) {
        /* ignore invalid access (ie do not raise exception) */
        return;
    }
    (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
}

static void mips_jazz_init(MachineState *machine,
                           enum jazz_model_e jazz_model)
{
    MemoryRegion *address_space = get_system_memory();
    char *filename;
    int bios_size, n;
    MIPSCPU *cpu;
    CPUClass *cc;
    CPUMIPSState *env;
    qemu_irq *i8259;
    rc4030_dma *dmas;
    IOMMUMemoryRegion *rc4030_dma_mr;
    MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
    MemoryRegion *isa_io = g_new(MemoryRegion, 1);
    MemoryRegion *rtc = g_new(MemoryRegion, 1);
    MemoryRegion *i8042 = g_new(MemoryRegion, 1);
    MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
    NICInfo *nd;
    DeviceState *dev, *rc4030;
    SysBusDevice *sysbus;
    ISABus *isa_bus;
    ISADevice *pit;
    DriveInfo *fds[MAX_FD];
    qemu_irq esp_reset, dma_enable;
    MemoryRegion *ram = g_new(MemoryRegion, 1);
    MemoryRegion *bios = g_new(MemoryRegion, 1);
    MemoryRegion *bios2 = g_new(MemoryRegion, 1);
    ESPState *esp;

    /* init CPUs */
    cpu = MIPS_CPU(cpu_create(machine->cpu_type));
    env = &cpu->env;
    qemu_register_reset(main_cpu_reset, cpu);

    /* Chipset returns 0 in invalid reads and do not raise data exceptions.
     * However, we can't simply add a global memory region to catch
     * everything, as memory core directly call unassigned_mem_read/write
     * on some invalid accesses, which call do_unassigned_access on the
     * CPU, which raise an exception.
     * Handle that case by hijacking the do_unassigned_access method on
     * the CPU, and do not raise exceptions for data access. */
    cc = CPU_GET_CLASS(cpu);
    real_do_unassigned_access = cc->do_unassigned_access;
    cc->do_unassigned_access = mips_jazz_do_unassigned_access;

    /* allocate RAM */
    memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
                                         machine->ram_size);
    memory_region_add_subregion(address_space, 0, ram);

    memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
                           &error_fatal);
    memory_region_set_readonly(bios, true);
    memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
                             0, MAGNUM_BIOS_SIZE);
    memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
    memory_region_add_subregion(address_space, 0xfff00000LL, bios2);

    /* load the BIOS image. */
    if (bios_name == NULL)
        bios_name = BIOS_FILENAME;
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
    if (filename) {
        bios_size = load_image_targphys(filename, 0xfff00000LL,
                                        MAGNUM_BIOS_SIZE);
        g_free(filename);
    } else {
        bios_size = -1;
    }
    if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
        error_report("Could not load MIPS bios '%s'", bios_name);
        exit(1);
    }

    /* Init CPU internal devices */
    cpu_mips_irq_init_cpu(cpu);
    cpu_mips_clock_init(cpu);

    /* Chipset */
    rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
    sysbus = SYS_BUS_DEVICE(rc4030);
    sysbus_connect_irq(sysbus, 0, env->irq[6]);
    sysbus_connect_irq(sysbus, 1, env->irq[3]);
    memory_region_add_subregion(address_space, 0x80000000,
                                sysbus_mmio_get_region(sysbus, 0));
    memory_region_add_subregion(address_space, 0xf0000000,
                                sysbus_mmio_get_region(sysbus, 1));
    memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
    memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);

    /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
    memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
    memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
    memory_region_add_subregion(address_space, 0x90000000, isa_io);
    memory_region_add_subregion(address_space, 0x91000000, isa_mem);
    isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);

    /* ISA devices */
    i8259 = i8259_init(isa_bus, env->irq[4]);
    isa_bus_irqs(isa_bus, i8259);
    i8257_dma_init(isa_bus, 0);
    pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
    pcspk_init(isa_bus, pit);

    /* Video card */
    switch (jazz_model) {
    case JAZZ_MAGNUM:
        dev = qdev_create(NULL, "sysbus-g364");
        qdev_init_nofail(dev);
        sysbus = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(sysbus, 0, 0x60080000);
        sysbus_mmio_map(sysbus, 1, 0x40000000);
        sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
        {
            /* Simple ROM, so user doesn't have to provide one */
            MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
            memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
                                   &error_fatal);
            memory_region_set_readonly(rom_mr, true);
            uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
            memory_region_add_subregion(address_space, 0x60000000, rom_mr);
            rom[0] = 0x10; /* Mips G364 */
        }
        break;
    case JAZZ_PICA61:
        isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
        break;
    default:
        break;
    }

    /* Network controller */
    for (n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];
        if (!nd->model)
            nd->model = g_strdup("dp83932");
        if (strcmp(nd->model, "dp83932") == 0) {
            qemu_check_nic_model(nd, "dp83932");

            dev = qdev_create(NULL, "dp8393x");
            qdev_set_nic_properties(dev, nd);
            qdev_prop_set_uint8(dev, "it_shift", 2);
            qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
            qdev_init_nofail(dev);
            sysbus = SYS_BUS_DEVICE(dev);
            sysbus_mmio_map(sysbus, 0, 0x80001000);
            sysbus_mmio_map(sysbus, 1, 0x8000b000);
            sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
            break;
        } else if (is_help_option(nd->model)) {
            error_report("Supported NICs: dp83932");
            exit(1);
        } else {
            error_report("Unsupported NIC: %s", nd->model);
            exit(1);
        }
    }

    /* SCSI adapter */
    esp = esp_init(0x80002000, 0, rc4030_dma_read, rc4030_dma_write, dmas[0],
                   qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
    scsi_bus_legacy_handle_cmdline(&esp->bus);

    /* Floppy */
    for (n = 0; n < MAX_FD; n++) {
        fds[n] = drive_get(IF_FLOPPY, 0, n);
    }
    /* FIXME: we should enable DMA with a custom IsaDma device */
    fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);

    /* Real time clock */
    mc146818_rtc_init(isa_bus, 1980, NULL);
    memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
    memory_region_add_subregion(address_space, 0x80004000, rtc);

    /* Keyboard (i8042) */
    i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
                  i8042, 0x1000, 0x1);
    memory_region_add_subregion(address_space, 0x80005000, i8042);

    /* Serial ports */
    if (serial_hds[0]) {
        serial_mm_init(address_space, 0x80006000, 0,
                       qdev_get_gpio_in(rc4030, 8), 8000000/16,
                       serial_hds[0], DEVICE_NATIVE_ENDIAN);
    }
    if (serial_hds[1]) {
        serial_mm_init(address_space, 0x80007000, 0,
                       qdev_get_gpio_in(rc4030, 9), 8000000/16,
                       serial_hds[1], DEVICE_NATIVE_ENDIAN);
    }

    /* Parallel port */
    if (parallel_hds[0])
        parallel_mm_init(address_space, 0x80008000, 0,
                         qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);

    /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */

    /* NVRAM */
    dev = qdev_create(NULL, "ds1225y");
    qdev_init_nofail(dev);
    sysbus = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(sysbus, 0, 0x80009000);

    /* LED indicator */
    sysbus_create_simple("jazz-led", 0x8000f000, NULL);
}

static
void mips_magnum_init(MachineState *machine)
{
    mips_jazz_init(machine, JAZZ_MAGNUM);
}

static
void mips_pica61_init(MachineState *machine)
{
    mips_jazz_init(machine, JAZZ_PICA61);
}

static void mips_magnum_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "MIPS Magnum";
    mc->init = mips_magnum_init;
    mc->block_default_type = IF_SCSI;
    mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
}

static const TypeInfo mips_magnum_type = {
    .name = MACHINE_TYPE_NAME("magnum"),
    .parent = TYPE_MACHINE,
    .class_init = mips_magnum_class_init,
};

static void mips_pica61_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "Acer Pica 61";
    mc->init = mips_pica61_init;
    mc->block_default_type = IF_SCSI;
    mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
}

static const TypeInfo mips_pica61_type = {
    .name = MACHINE_TYPE_NAME("pica61"),
    .parent = TYPE_MACHINE,
    .class_init = mips_pica61_class_init,
};

static void mips_jazz_machine_init(void)
{
    type_register_static(&mips_magnum_type);
    type_register_static(&mips_pica61_type);
}

type_init(mips_jazz_machine_init)
Commit	Line	Data
4ce7ff6e AJ	1	/*
	2	* QEMU MIPS Jazz support
	3	*
	4	* Copyright (c) 2007-2008 Hervé Poussineau
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
c684822a	25	#include "qemu/osdep.h"
83c9f4ca	26	#include "hw/hw.h"
0d09e41a PB	27	#include "hw/mips/mips.h"
	28	#include "hw/mips/cpudevs.h"
	29	#include "hw/i386/pc.h"
55f613ac	30	#include "hw/dma/i8257.h"
0d09e41a	31	#include "hw/char/serial.h"
bb3d5ea8	32	#include "hw/char/parallel.h"
0d09e41a PB	33	#include "hw/isa/isa.h"
0d09e41a PB	34	#include "hw/block/fdc.h"
9c17d615 PB	35	#include "sysemu/sysemu.h"
9c17d615 PB	36	#include "sysemu/arch_init.h"
83c9f4ca	37	#include "hw/boards.h"
1422e32d	38	#include "net/net.h"
0d09e41a PB	39	#include "hw/scsi/esp.h"
0d09e41a PB	40	#include "hw/mips/bios.h"
83c9f4ca	41	#include "hw/loader.h"
0d09e41a PB	42	#include "hw/timer/mc146818rtc.h"
0d09e41a PB	43	#include "hw/timer/i8254.h"
866e2b37	44	#include "hw/display/vga.h"
0d09e41a	45	#include "hw/audio/pcspk.h"
47973a2d	46	#include "hw/input/i8042.h"
83c9f4ca	47	#include "hw/sysbus.h"
022c62cb	48	#include "exec/address-spaces.h"
38c8894f	49	#include "sysemu/qtest.h"
e688df6b	50	#include "qapi/error.h"
2e985fe0	51	#include "qemu/error-report.h"
f348b6d1	52	#include "qemu/help_option.h"
4ce7ff6e	53
4ce7ff6e AJ	54	enum jazz_model_e
	55	{
	56	JAZZ_MAGNUM,
c171148c	57	JAZZ_PICA61,
4ce7ff6e AJ	58	};
	59
	60	static void main_cpu_reset(void *opaque)
	61	{
f37f435a AF	62	MIPSCPU *cpu = opaque;
	63
	64	cpu_reset(CPU(cpu));
4ce7ff6e AJ	65	}
4ce7ff6e AJ	66
a8170e5e	67	static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
4ce7ff6e	68	{
5c63bcf7	69	uint8_t val;
5c9eb028 PM	70	address_space_read(&address_space_memory, 0x90000071,
5c9eb028 PM	71	MEMTXATTRS_UNSPECIFIED, &val, 1);
5c63bcf7	72	return val;
4ce7ff6e AJ	73	}
4ce7ff6e AJ	74
a8170e5e	75	static void rtc_write(void *opaque, hwaddr addr,
60581b37	76	uint64_t val, unsigned size)
4ce7ff6e	77	{
5c63bcf7	78	uint8_t buf = val & 0xff;
5c9eb028 PM	79	address_space_write(&address_space_memory, 0x90000071,
5c9eb028 PM	80	MEMTXATTRS_UNSPECIFIED, &buf, 1);
4ce7ff6e AJ	81	}
4ce7ff6e AJ	82
60581b37 AK	83	static const MemoryRegionOps rtc_ops = {
	84	.read = rtc_read,
	85	.write = rtc_write,
	86	.endianness = DEVICE_NATIVE_ENDIAN,
4ce7ff6e AJ	87	};
4ce7ff6e AJ	88
a8170e5e	89	static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
60581b37	90	unsigned size)
c6945b15 AJ	91	{
	92	/* Nothing to do. That is only to ensure that
	93	* the current DMA acknowledge cycle is completed. */
60581b37	94	return 0xff;
c6945b15 AJ	95	}
c6945b15 AJ	96
a8170e5e	97	static void dma_dummy_write(void *opaque, hwaddr addr,
60581b37 AK	98	uint64_t val, unsigned size)
	99	{
	100	/* Nothing to do. That is only to ensure that
	101	* the current DMA acknowledge cycle is completed. */
	102	}
c6945b15	103
60581b37 AK	104	static const MemoryRegionOps dma_dummy_ops = {
	105	.read = dma_dummy_read,
	106	.write = dma_dummy_write,
	107	.endianness = DEVICE_NATIVE_ENDIAN,
c6945b15 AJ	108	};
c6945b15 AJ	109
4ce7ff6e AJ	110	#define MAGNUM_BIOS_SIZE_MAX 0x7e000
	111	#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
	112
54e75558 HP	113	static CPUUnassignedAccess real_do_unassigned_access;
	114	static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
	115	bool is_write, bool is_exec,
	116	int opaque, unsigned size)
	117	{
	118	if (!is_exec) {
	119	/* ignore invalid access (ie do not raise exception) */
	120	return;
	121	}
	122	(*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
	123	}
	124
f33772c8	125	static void mips_jazz_init(MachineState *machine,
c2d0d012	126	enum jazz_model_e jazz_model)
4ce7ff6e	127	{
f33772c8	128	MemoryRegion *address_space = get_system_memory();
5cea8590	129	char *filename;
4ce7ff6e	130	int bios_size, n;
6bd8da65	131	MIPSCPU *cpu;
54e75558	132	CPUClass *cc;
61c56c8c	133	CPUMIPSState *env;
d791d60f	134	qemu_irq *i8259;
c6945b15	135	rc4030_dma *dmas;
3df9d748	136	IOMMUMemoryRegion *rc4030_dma_mr;
5c63bcf7 HP	137	MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
5c63bcf7 HP	138	MemoryRegion *isa_io = g_new(MemoryRegion, 1);
60581b37	139	MemoryRegion *rtc = g_new(MemoryRegion, 1);
dbff76ac	140	MemoryRegion *i8042 = g_new(MemoryRegion, 1);
60581b37	141	MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
a65f56ee	142	NICInfo *nd;
d791d60f	143	DeviceState dev, rc4030;
cd3e2409	144	SysBusDevice *sysbus;
48a18b3c	145	ISABus *isa_bus;
64d7e9a4	146	ISADevice *pit;
fd8014e1	147	DriveInfo *fds[MAX_FD];
73d74342	148	qemu_irq esp_reset, dma_enable;
60581b37 AK	149	MemoryRegion *ram = g_new(MemoryRegion, 1);
	150	MemoryRegion *bios = g_new(MemoryRegion, 1);
	151	MemoryRegion *bios2 = g_new(MemoryRegion, 1);
148b2ba1	152	ESPState *esp;
4ce7ff6e AJ	153
4ce7ff6e AJ	154	/* init CPUs */
3469e656	155	cpu = MIPS_CPU(cpu_create(machine->cpu_type));
6bd8da65	156	env = &cpu->env;
f37f435a	157	qemu_register_reset(main_cpu_reset, cpu);
4ce7ff6e	158
54e75558 HP	159	/* Chipset returns 0 in invalid reads and do not raise data exceptions.
	160	* However, we can't simply add a global memory region to catch
	161	* everything, as memory core directly call unassigned_mem_read/write
	162	* on some invalid accesses, which call do_unassigned_access on the
	163	* CPU, which raise an exception.
	164	* Handle that case by hijacking the do_unassigned_access method on
	165	* the CPU, and do not raise exceptions for data access. */
	166	cc = CPU_GET_CLASS(cpu);
	167	real_do_unassigned_access = cc->do_unassigned_access;
	168	cc->do_unassigned_access = mips_jazz_do_unassigned_access;
	169
4ce7ff6e	170	/* allocate RAM */
6a926fbc DM	171	memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
6a926fbc DM	172	machine->ram_size);
60581b37	173	memory_region_add_subregion(address_space, 0, ram);
dcac9679	174
98a99ce0	175	memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
f8ed85ac	176	&error_fatal);
60581b37	177	memory_region_set_readonly(bios, true);
2c9b15ca	178	memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
60581b37 AK	179	0, MAGNUM_BIOS_SIZE);
	180	memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
	181	memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
4ce7ff6e AJ	182
4ce7ff6e AJ	183	/* load the BIOS image. */
c6945b15 AJ	184	if (bios_name == NULL)
c6945b15 AJ	185	bios_name = BIOS_FILENAME;
5cea8590 PB	186	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
	187	if (filename) {
	188	bios_size = load_image_targphys(filename, 0xfff00000LL,
	189	MAGNUM_BIOS_SIZE);
7267c094	190	g_free(filename);
5cea8590 PB	191	} else {
	192	bios_size = -1;
	193	}
38c8894f	194	if ((bios_size < 0 \|\| bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
2e985fe0 AJ	195	error_report("Could not load MIPS bios '%s'", bios_name);
2e985fe0 AJ	196	exit(1);
4ce7ff6e AJ	197	}
4ce7ff6e AJ	198
4ce7ff6e	199	/* Init CPU internal devices */
5a975d43 PB	200	cpu_mips_irq_init_cpu(cpu);
5a975d43 PB	201	cpu_mips_clock_init(cpu);
4ce7ff6e AJ	202
4ce7ff6e AJ	203	/* Chipset */
d791d60f HP	204	rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
	205	sysbus = SYS_BUS_DEVICE(rc4030);
	206	sysbus_connect_irq(sysbus, 0, env->irq[6]);
	207	sysbus_connect_irq(sysbus, 1, env->irq[3]);
	208	memory_region_add_subregion(address_space, 0x80000000,
	209	sysbus_mmio_get_region(sysbus, 0));
	210	memory_region_add_subregion(address_space, 0xf0000000,
	211	sysbus_mmio_get_region(sysbus, 1));
2c9b15ca	212	memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
60581b37	213	memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
4ce7ff6e	214
5c63bcf7 HP	215	/* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
	216	memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
	217	memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
	218	memory_region_add_subregion(address_space, 0x90000000, isa_io);
	219	memory_region_add_subregion(address_space, 0x91000000, isa_mem);
d10e5432	220	isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
5c63bcf7	221
4ce7ff6e	222	/* ISA devices */
48a18b3c HP	223	i8259 = i8259_init(isa_bus, env->irq[4]);
48a18b3c HP	224	isa_bus_irqs(isa_bus, i8259);
55f613ac	225	i8257_dma_init(isa_bus, 0);
acf695ec	226	pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
302fe51b	227	pcspk_init(isa_bus, pit);
4ce7ff6e	228
4ce7ff6e AJ	229	/* Video card */
	230	switch (jazz_model) {
	231	case JAZZ_MAGNUM:
97a3f6ff HP	232	dev = qdev_create(NULL, "sysbus-g364");
97a3f6ff HP	233	qdev_init_nofail(dev);
1356b98d	234	sysbus = SYS_BUS_DEVICE(dev);
97a3f6ff HP	235	sysbus_mmio_map(sysbus, 0, 0x60080000);
97a3f6ff HP	236	sysbus_mmio_map(sysbus, 1, 0x40000000);
d791d60f	237	sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
97a3f6ff HP	238	{
97a3f6ff HP	239	/* Simple ROM, so user doesn't have to provide one */
60581b37	240	MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
98a99ce0	241	memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
f8ed85ac	242	&error_fatal);
60581b37 AK	243	memory_region_set_readonly(rom_mr, true);
	244	uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
	245	memory_region_add_subregion(address_space, 0x60000000, rom_mr);
97a3f6ff HP	246	rom[0] = 0x10; /* Mips G364 */
97a3f6ff HP	247	}
4ce7ff6e	248	break;
c171148c	249	case JAZZ_PICA61:
be20f9e9	250	isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
c171148c	251	break;
4ce7ff6e AJ	252	default:
	253	break;
	254	}
	255
	256	/* Network controller */
a65f56ee AJ	257	for (n = 0; n < nb_nics; n++) {
	258	nd = &nd_table[n];
	259	if (!nd->model)
7267c094	260	nd->model = g_strdup("dp83932");
a65f56ee	261	if (strcmp(nd->model, "dp83932") == 0) {
104655a5 HP	262	qemu_check_nic_model(nd, "dp83932");
	263
	264	dev = qdev_create(NULL, "dp8393x");
	265	qdev_set_nic_properties(dev, nd);
	266	qdev_prop_set_uint8(dev, "it_shift", 2);
	267	qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
	268	qdev_init_nofail(dev);
	269	sysbus = SYS_BUS_DEVICE(dev);
	270	sysbus_mmio_map(sysbus, 0, 0x80001000);
89ae0ff9	271	sysbus_mmio_map(sysbus, 1, 0x8000b000);
104655a5	272	sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
a65f56ee	273	break;
c8057f95	274	} else if (is_help_option(nd->model)) {
bd6e1d81	275	error_report("Supported NICs: dp83932");
a65f56ee AJ	276	exit(1);
a65f56ee AJ	277	} else {
bd6e1d81	278	error_report("Unsupported NIC: %s", nd->model);
a65f56ee AJ	279	exit(1);
	280	}
	281	}
4ce7ff6e AJ	282
4ce7ff6e AJ	283	/* SCSI adapter */
148b2ba1 TH	284	esp = esp_init(0x80002000, 0, rc4030_dma_read, rc4030_dma_write, dmas[0],
	285	qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
	286	scsi_bus_legacy_handle_cmdline(&esp->bus);
4ce7ff6e AJ	287
4ce7ff6e AJ	288	/* Floppy */
4ce7ff6e	289	for (n = 0; n < MAX_FD; n++) {
fd8014e1	290	fds[n] = drive_get(IF_FLOPPY, 0, n);
4ce7ff6e	291	}
020e2986 HP	292	/* FIXME: we should enable DMA with a custom IsaDma device */
020e2986 HP	293	fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
4ce7ff6e AJ	294
4ce7ff6e AJ	295	/* Real time clock */
6c646a11	296	mc146818_rtc_init(isa_bus, 1980, NULL);
2c9b15ca	297	memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
60581b37	298	memory_region_add_subregion(address_space, 0x80004000, rtc);
4ce7ff6e AJ	299
4ce7ff6e AJ	300	/* Keyboard (i8042) */
d791d60f HP	301	i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
d791d60f HP	302	i8042, 0x1000, 0x1);
dbff76ac	303	memory_region_add_subregion(address_space, 0x80005000, i8042);
4ce7ff6e AJ	304
4ce7ff6e AJ	305	/* Serial ports */
2d48377a	306	if (serial_hds[0]) {
d791d60f HP	307	serial_mm_init(address_space, 0x80006000, 0,
d791d60f HP	308	qdev_get_gpio_in(rc4030, 8), 8000000/16,
39186d8a	309	serial_hds[0], DEVICE_NATIVE_ENDIAN);
2d48377a BS	310	}
2d48377a BS	311	if (serial_hds[1]) {
d791d60f HP	312	serial_mm_init(address_space, 0x80007000, 0,
d791d60f HP	313	qdev_get_gpio_in(rc4030, 9), 8000000/16,
39186d8a	314	serial_hds[1], DEVICE_NATIVE_ENDIAN);
2d48377a	315	}
4ce7ff6e AJ	316
	317	/* Parallel port */
	318	if (parallel_hds[0])
d791d60f HP	319	parallel_mm_init(address_space, 0x80008000, 0,
d791d60f HP	320	qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
4ce7ff6e	321
4ce7ff6e	322	/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
4ce7ff6e	323
cd3e2409 HP	324	/* NVRAM */
	325	dev = qdev_create(NULL, "ds1225y");
	326	qdev_init_nofail(dev);
1356b98d	327	sysbus = SYS_BUS_DEVICE(dev);
cd3e2409	328	sysbus_mmio_map(sysbus, 0, 0x80009000);
4ce7ff6e AJ	329
4ce7ff6e AJ	330	/* LED indicator */
b39506e4	331	sysbus_create_simple("jazz-led", 0x8000f000, NULL);
4ce7ff6e AJ	332	}
	333
	334	static
3ef96221	335	void mips_magnum_init(MachineState *machine)
4ce7ff6e	336	{
f33772c8	337	mips_jazz_init(machine, JAZZ_MAGNUM);
4ce7ff6e AJ	338	}
4ce7ff6e AJ	339
c171148c	340	static
3ef96221	341	void mips_pica61_init(MachineState *machine)
c171148c	342	{
f33772c8	343	mips_jazz_init(machine, JAZZ_PICA61);
c171148c AJ	344	}
c171148c AJ	345
8a661aea	346	static void mips_magnum_class_init(ObjectClass oc, void data)
e264d29d	347	{
8a661aea AF	348	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	349
e264d29d EH	350	mc->desc = "MIPS Magnum";
	351	mc->init = mips_magnum_init;
	352	mc->block_default_type = IF_SCSI;
3469e656	353	mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
e264d29d	354	}
c171148c	355
8a661aea AF	356	static const TypeInfo mips_magnum_type = {
	357	.name = MACHINE_TYPE_NAME("magnum"),
	358	.parent = TYPE_MACHINE,
	359	.class_init = mips_magnum_class_init,
	360	};
f80f9ec9	361
8a661aea	362	static void mips_pica61_class_init(ObjectClass oc, void data)
f80f9ec9	363	{
8a661aea AF	364	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	365
e264d29d EH	366	mc->desc = "Acer Pica 61";
	367	mc->init = mips_pica61_init;
	368	mc->block_default_type = IF_SCSI;
3469e656	369	mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
f80f9ec9 AL	370	}
f80f9ec9 AL	371
8a661aea AF	372	static const TypeInfo mips_pica61_type = {
	373	.name = MACHINE_TYPE_NAME("pica61"),
	374	.parent = TYPE_MACHINE,
	375	.class_init = mips_pica61_class_init,
	376	};
	377
	378	static void mips_jazz_machine_init(void)
	379	{
	380	type_register_static(&mips_magnum_type);
	381	type_register_static(&mips_pica61_type);
	382	}
	383
0e6aac87	384	type_init(mips_jazz_machine_init)