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Commit | Line | Data |
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4ce7ff6e AJ |
1 | /* |
2 | * QEMU MIPS Jazz support | |
3 | * | |
4 | * Copyright (c) 2007-2008 Hervé Poussineau | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
c684822a | 25 | #include "qemu/osdep.h" |
a8d25326 | 26 | #include "qemu-common.h" |
0d09e41a PB |
27 | #include "hw/mips/mips.h" |
28 | #include "hw/mips/cpudevs.h" | |
29 | #include "hw/i386/pc.h" | |
55f613ac | 30 | #include "hw/dma/i8257.h" |
0d09e41a | 31 | #include "hw/char/serial.h" |
bb3d5ea8 | 32 | #include "hw/char/parallel.h" |
0d09e41a PB |
33 | #include "hw/isa/isa.h" |
34 | #include "hw/block/fdc.h" | |
9c17d615 PB |
35 | #include "sysemu/sysemu.h" |
36 | #include "sysemu/arch_init.h" | |
83c9f4ca | 37 | #include "hw/boards.h" |
1422e32d | 38 | #include "net/net.h" |
0d09e41a PB |
39 | #include "hw/scsi/esp.h" |
40 | #include "hw/mips/bios.h" | |
83c9f4ca | 41 | #include "hw/loader.h" |
0d09e41a PB |
42 | #include "hw/timer/mc146818rtc.h" |
43 | #include "hw/timer/i8254.h" | |
866e2b37 | 44 | #include "hw/display/vga.h" |
0d09e41a | 45 | #include "hw/audio/pcspk.h" |
47973a2d | 46 | #include "hw/input/i8042.h" |
83c9f4ca | 47 | #include "hw/sysbus.h" |
022c62cb | 48 | #include "exec/address-spaces.h" |
38c8894f | 49 | #include "sysemu/qtest.h" |
71e8a915 | 50 | #include "sysemu/reset.h" |
e688df6b | 51 | #include "qapi/error.h" |
2e985fe0 | 52 | #include "qemu/error-report.h" |
f348b6d1 | 53 | #include "qemu/help_option.h" |
4ce7ff6e | 54 | |
4ce7ff6e AJ |
55 | enum jazz_model_e |
56 | { | |
57 | JAZZ_MAGNUM, | |
c171148c | 58 | JAZZ_PICA61, |
4ce7ff6e AJ |
59 | }; |
60 | ||
61 | static void main_cpu_reset(void *opaque) | |
62 | { | |
f37f435a AF |
63 | MIPSCPU *cpu = opaque; |
64 | ||
65 | cpu_reset(CPU(cpu)); | |
4ce7ff6e AJ |
66 | } |
67 | ||
a8170e5e | 68 | static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) |
4ce7ff6e | 69 | { |
5c63bcf7 | 70 | uint8_t val; |
5c9eb028 PM |
71 | address_space_read(&address_space_memory, 0x90000071, |
72 | MEMTXATTRS_UNSPECIFIED, &val, 1); | |
5c63bcf7 | 73 | return val; |
4ce7ff6e AJ |
74 | } |
75 | ||
a8170e5e | 76 | static void rtc_write(void *opaque, hwaddr addr, |
60581b37 | 77 | uint64_t val, unsigned size) |
4ce7ff6e | 78 | { |
5c63bcf7 | 79 | uint8_t buf = val & 0xff; |
5c9eb028 PM |
80 | address_space_write(&address_space_memory, 0x90000071, |
81 | MEMTXATTRS_UNSPECIFIED, &buf, 1); | |
4ce7ff6e AJ |
82 | } |
83 | ||
60581b37 AK |
84 | static const MemoryRegionOps rtc_ops = { |
85 | .read = rtc_read, | |
86 | .write = rtc_write, | |
87 | .endianness = DEVICE_NATIVE_ENDIAN, | |
4ce7ff6e AJ |
88 | }; |
89 | ||
a8170e5e | 90 | static uint64_t dma_dummy_read(void *opaque, hwaddr addr, |
60581b37 | 91 | unsigned size) |
c6945b15 AJ |
92 | { |
93 | /* Nothing to do. That is only to ensure that | |
94 | * the current DMA acknowledge cycle is completed. */ | |
60581b37 | 95 | return 0xff; |
c6945b15 AJ |
96 | } |
97 | ||
a8170e5e | 98 | static void dma_dummy_write(void *opaque, hwaddr addr, |
60581b37 AK |
99 | uint64_t val, unsigned size) |
100 | { | |
101 | /* Nothing to do. That is only to ensure that | |
102 | * the current DMA acknowledge cycle is completed. */ | |
103 | } | |
c6945b15 | 104 | |
60581b37 AK |
105 | static const MemoryRegionOps dma_dummy_ops = { |
106 | .read = dma_dummy_read, | |
107 | .write = dma_dummy_write, | |
108 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c6945b15 AJ |
109 | }; |
110 | ||
4ce7ff6e AJ |
111 | #define MAGNUM_BIOS_SIZE_MAX 0x7e000 |
112 | #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) | |
113 | ||
8d2b8718 PM |
114 | static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr, |
115 | vaddr addr, unsigned size, | |
116 | MMUAccessType access_type, | |
117 | int mmu_idx, MemTxAttrs attrs, | |
118 | MemTxResult response, | |
119 | uintptr_t retaddr); | |
120 | ||
121 | static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr, | |
122 | vaddr addr, unsigned size, | |
123 | MMUAccessType access_type, | |
124 | int mmu_idx, MemTxAttrs attrs, | |
125 | MemTxResult response, | |
126 | uintptr_t retaddr) | |
127 | { | |
128 | if (access_type != MMU_INST_FETCH) { | |
129 | /* ignore invalid access (ie do not raise exception) */ | |
130 | return; | |
131 | } | |
132 | (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type, | |
133 | mmu_idx, attrs, response, retaddr); | |
134 | } | |
135 | ||
f33772c8 | 136 | static void mips_jazz_init(MachineState *machine, |
c2d0d012 | 137 | enum jazz_model_e jazz_model) |
4ce7ff6e | 138 | { |
f33772c8 | 139 | MemoryRegion *address_space = get_system_memory(); |
5cea8590 | 140 | char *filename; |
4ce7ff6e | 141 | int bios_size, n; |
6bd8da65 | 142 | MIPSCPU *cpu; |
54e75558 | 143 | CPUClass *cc; |
61c56c8c | 144 | CPUMIPSState *env; |
d791d60f | 145 | qemu_irq *i8259; |
c6945b15 | 146 | rc4030_dma *dmas; |
3df9d748 | 147 | IOMMUMemoryRegion *rc4030_dma_mr; |
5c63bcf7 HP |
148 | MemoryRegion *isa_mem = g_new(MemoryRegion, 1); |
149 | MemoryRegion *isa_io = g_new(MemoryRegion, 1); | |
60581b37 | 150 | MemoryRegion *rtc = g_new(MemoryRegion, 1); |
dbff76ac | 151 | MemoryRegion *i8042 = g_new(MemoryRegion, 1); |
60581b37 | 152 | MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); |
a65f56ee | 153 | NICInfo *nd; |
d791d60f | 154 | DeviceState *dev, *rc4030; |
cd3e2409 | 155 | SysBusDevice *sysbus; |
48a18b3c | 156 | ISABus *isa_bus; |
64d7e9a4 | 157 | ISADevice *pit; |
fd8014e1 | 158 | DriveInfo *fds[MAX_FD]; |
60581b37 AK |
159 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
160 | MemoryRegion *bios = g_new(MemoryRegion, 1); | |
161 | MemoryRegion *bios2 = g_new(MemoryRegion, 1); | |
09eb69a5 | 162 | SysBusESPState *sysbus_esp; |
148b2ba1 | 163 | ESPState *esp; |
4ce7ff6e AJ |
164 | |
165 | /* init CPUs */ | |
3469e656 | 166 | cpu = MIPS_CPU(cpu_create(machine->cpu_type)); |
6bd8da65 | 167 | env = &cpu->env; |
f37f435a | 168 | qemu_register_reset(main_cpu_reset, cpu); |
4ce7ff6e | 169 | |
8d2b8718 PM |
170 | /* |
171 | * Chipset returns 0 in invalid reads and do not raise data exceptions. | |
54e75558 | 172 | * However, we can't simply add a global memory region to catch |
8d2b8718 PM |
173 | * everything, as this would make all accesses including instruction |
174 | * accesses be ignored and not raise exceptions. | |
6626286e PM |
175 | * So instead we hijack the do_transaction_failed method on the CPU, and |
176 | * do not raise exceptions for data access. | |
8d2b8718 PM |
177 | * |
178 | * NOTE: this behaviour of raising exceptions for bad instruction | |
179 | * fetches but not bad data accesses was added in commit 54e755588cf1e9 | |
180 | * to restore behaviour broken by c658b94f6e8c206, but it is not clear | |
181 | * whether the real hardware behaves this way. It is possible that | |
182 | * real hardware ignores bad instruction fetches as well -- if so then | |
183 | * we could replace this hijacking of CPU methods with a simple global | |
184 | * memory region that catches all memory accesses, as we do on Malta. | |
185 | */ | |
54e75558 | 186 | cc = CPU_GET_CLASS(cpu); |
6626286e PM |
187 | real_do_transaction_failed = cc->do_transaction_failed; |
188 | cc->do_transaction_failed = mips_jazz_do_transaction_failed; | |
54e75558 | 189 | |
4ce7ff6e | 190 | /* allocate RAM */ |
6a926fbc DM |
191 | memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram", |
192 | machine->ram_size); | |
60581b37 | 193 | memory_region_add_subregion(address_space, 0, ram); |
dcac9679 | 194 | |
98a99ce0 | 195 | memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, |
f8ed85ac | 196 | &error_fatal); |
60581b37 | 197 | memory_region_set_readonly(bios, true); |
2c9b15ca | 198 | memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, |
60581b37 AK |
199 | 0, MAGNUM_BIOS_SIZE); |
200 | memory_region_add_subregion(address_space, 0x1fc00000LL, bios); | |
201 | memory_region_add_subregion(address_space, 0xfff00000LL, bios2); | |
4ce7ff6e AJ |
202 | |
203 | /* load the BIOS image. */ | |
c6945b15 AJ |
204 | if (bios_name == NULL) |
205 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
206 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
207 | if (filename) { | |
208 | bios_size = load_image_targphys(filename, 0xfff00000LL, | |
209 | MAGNUM_BIOS_SIZE); | |
7267c094 | 210 | g_free(filename); |
5cea8590 PB |
211 | } else { |
212 | bios_size = -1; | |
213 | } | |
38c8894f | 214 | if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) { |
2e985fe0 AJ |
215 | error_report("Could not load MIPS bios '%s'", bios_name); |
216 | exit(1); | |
4ce7ff6e AJ |
217 | } |
218 | ||
4ce7ff6e | 219 | /* Init CPU internal devices */ |
5a975d43 PB |
220 | cpu_mips_irq_init_cpu(cpu); |
221 | cpu_mips_clock_init(cpu); | |
4ce7ff6e AJ |
222 | |
223 | /* Chipset */ | |
d791d60f HP |
224 | rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); |
225 | sysbus = SYS_BUS_DEVICE(rc4030); | |
226 | sysbus_connect_irq(sysbus, 0, env->irq[6]); | |
227 | sysbus_connect_irq(sysbus, 1, env->irq[3]); | |
228 | memory_region_add_subregion(address_space, 0x80000000, | |
229 | sysbus_mmio_get_region(sysbus, 0)); | |
230 | memory_region_add_subregion(address_space, 0xf0000000, | |
231 | sysbus_mmio_get_region(sysbus, 1)); | |
2c9b15ca | 232 | memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000); |
60581b37 | 233 | memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); |
4ce7ff6e | 234 | |
5c63bcf7 HP |
235 | /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ |
236 | memory_region_init(isa_io, NULL, "isa-io", 0x00010000); | |
237 | memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); | |
238 | memory_region_add_subregion(address_space, 0x90000000, isa_io); | |
239 | memory_region_add_subregion(address_space, 0x91000000, isa_mem); | |
d10e5432 | 240 | isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort); |
5c63bcf7 | 241 | |
4ce7ff6e | 242 | /* ISA devices */ |
48a18b3c HP |
243 | i8259 = i8259_init(isa_bus, env->irq[4]); |
244 | isa_bus_irqs(isa_bus, i8259); | |
55f613ac | 245 | i8257_dma_init(isa_bus, 0); |
acf695ec | 246 | pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); |
302fe51b | 247 | pcspk_init(isa_bus, pit); |
4ce7ff6e | 248 | |
4ce7ff6e AJ |
249 | /* Video card */ |
250 | switch (jazz_model) { | |
251 | case JAZZ_MAGNUM: | |
97a3f6ff HP |
252 | dev = qdev_create(NULL, "sysbus-g364"); |
253 | qdev_init_nofail(dev); | |
1356b98d | 254 | sysbus = SYS_BUS_DEVICE(dev); |
97a3f6ff HP |
255 | sysbus_mmio_map(sysbus, 0, 0x60080000); |
256 | sysbus_mmio_map(sysbus, 1, 0x40000000); | |
d791d60f | 257 | sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3)); |
97a3f6ff HP |
258 | { |
259 | /* Simple ROM, so user doesn't have to provide one */ | |
60581b37 | 260 | MemoryRegion *rom_mr = g_new(MemoryRegion, 1); |
98a99ce0 | 261 | memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000, |
f8ed85ac | 262 | &error_fatal); |
60581b37 AK |
263 | memory_region_set_readonly(rom_mr, true); |
264 | uint8_t *rom = memory_region_get_ram_ptr(rom_mr); | |
265 | memory_region_add_subregion(address_space, 0x60000000, rom_mr); | |
97a3f6ff HP |
266 | rom[0] = 0x10; /* Mips G364 */ |
267 | } | |
4ce7ff6e | 268 | break; |
c171148c | 269 | case JAZZ_PICA61: |
be20f9e9 | 270 | isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); |
c171148c | 271 | break; |
4ce7ff6e AJ |
272 | default: |
273 | break; | |
274 | } | |
275 | ||
276 | /* Network controller */ | |
a65f56ee AJ |
277 | for (n = 0; n < nb_nics; n++) { |
278 | nd = &nd_table[n]; | |
279 | if (!nd->model) | |
7267c094 | 280 | nd->model = g_strdup("dp83932"); |
a65f56ee | 281 | if (strcmp(nd->model, "dp83932") == 0) { |
104655a5 HP |
282 | qemu_check_nic_model(nd, "dp83932"); |
283 | ||
284 | dev = qdev_create(NULL, "dp8393x"); | |
285 | qdev_set_nic_properties(dev, nd); | |
286 | qdev_prop_set_uint8(dev, "it_shift", 2); | |
287 | qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr); | |
288 | qdev_init_nofail(dev); | |
289 | sysbus = SYS_BUS_DEVICE(dev); | |
290 | sysbus_mmio_map(sysbus, 0, 0x80001000); | |
89ae0ff9 | 291 | sysbus_mmio_map(sysbus, 1, 0x8000b000); |
104655a5 | 292 | sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); |
a65f56ee | 293 | break; |
c8057f95 | 294 | } else if (is_help_option(nd->model)) { |
bd6e1d81 | 295 | error_report("Supported NICs: dp83932"); |
a65f56ee AJ |
296 | exit(1); |
297 | } else { | |
bd6e1d81 | 298 | error_report("Unsupported NIC: %s", nd->model); |
a65f56ee AJ |
299 | exit(1); |
300 | } | |
301 | } | |
4ce7ff6e AJ |
302 | |
303 | /* SCSI adapter */ | |
09eb69a5 MCA |
304 | dev = qdev_create(NULL, TYPE_ESP); |
305 | sysbus_esp = ESP_STATE(dev); | |
306 | esp = &sysbus_esp->esp; | |
307 | esp->dma_memory_read = rc4030_dma_read; | |
308 | esp->dma_memory_write = rc4030_dma_write; | |
309 | esp->dma_opaque = dmas[0]; | |
310 | sysbus_esp->it_shift = 0; | |
311 | /* XXX for now until rc4030 has been changed to use DMA enable signal */ | |
312 | esp->dma_enabled = 1; | |
313 | qdev_init_nofail(dev); | |
314 | ||
315 | sysbus = SYS_BUS_DEVICE(dev); | |
316 | sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5)); | |
317 | sysbus_mmio_map(sysbus, 0, 0x80002000); | |
318 | ||
148b2ba1 | 319 | scsi_bus_legacy_handle_cmdline(&esp->bus); |
4ce7ff6e AJ |
320 | |
321 | /* Floppy */ | |
4ce7ff6e | 322 | for (n = 0; n < MAX_FD; n++) { |
fd8014e1 | 323 | fds[n] = drive_get(IF_FLOPPY, 0, n); |
4ce7ff6e | 324 | } |
020e2986 HP |
325 | /* FIXME: we should enable DMA with a custom IsaDma device */ |
326 | fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds); | |
4ce7ff6e AJ |
327 | |
328 | /* Real time clock */ | |
6c646a11 | 329 | mc146818_rtc_init(isa_bus, 1980, NULL); |
2c9b15ca | 330 | memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); |
60581b37 | 331 | memory_region_add_subregion(address_space, 0x80004000, rtc); |
4ce7ff6e AJ |
332 | |
333 | /* Keyboard (i8042) */ | |
d791d60f HP |
334 | i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7), |
335 | i8042, 0x1000, 0x1); | |
dbff76ac | 336 | memory_region_add_subregion(address_space, 0x80005000, i8042); |
4ce7ff6e AJ |
337 | |
338 | /* Serial ports */ | |
9bca0edb | 339 | if (serial_hd(0)) { |
d791d60f HP |
340 | serial_mm_init(address_space, 0x80006000, 0, |
341 | qdev_get_gpio_in(rc4030, 8), 8000000/16, | |
9bca0edb | 342 | serial_hd(0), DEVICE_NATIVE_ENDIAN); |
2d48377a | 343 | } |
9bca0edb | 344 | if (serial_hd(1)) { |
d791d60f HP |
345 | serial_mm_init(address_space, 0x80007000, 0, |
346 | qdev_get_gpio_in(rc4030, 9), 8000000/16, | |
9bca0edb | 347 | serial_hd(1), DEVICE_NATIVE_ENDIAN); |
2d48377a | 348 | } |
4ce7ff6e AJ |
349 | |
350 | /* Parallel port */ | |
351 | if (parallel_hds[0]) | |
d791d60f HP |
352 | parallel_mm_init(address_space, 0x80008000, 0, |
353 | qdev_get_gpio_in(rc4030, 0), parallel_hds[0]); | |
4ce7ff6e | 354 | |
4ce7ff6e | 355 | /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ |
4ce7ff6e | 356 | |
cd3e2409 HP |
357 | /* NVRAM */ |
358 | dev = qdev_create(NULL, "ds1225y"); | |
359 | qdev_init_nofail(dev); | |
1356b98d | 360 | sysbus = SYS_BUS_DEVICE(dev); |
cd3e2409 | 361 | sysbus_mmio_map(sysbus, 0, 0x80009000); |
4ce7ff6e AJ |
362 | |
363 | /* LED indicator */ | |
b39506e4 | 364 | sysbus_create_simple("jazz-led", 0x8000f000, NULL); |
0287d89f PB |
365 | |
366 | g_free(dmas); | |
4ce7ff6e AJ |
367 | } |
368 | ||
369 | static | |
3ef96221 | 370 | void mips_magnum_init(MachineState *machine) |
4ce7ff6e | 371 | { |
f33772c8 | 372 | mips_jazz_init(machine, JAZZ_MAGNUM); |
4ce7ff6e AJ |
373 | } |
374 | ||
c171148c | 375 | static |
3ef96221 | 376 | void mips_pica61_init(MachineState *machine) |
c171148c | 377 | { |
f33772c8 | 378 | mips_jazz_init(machine, JAZZ_PICA61); |
c171148c AJ |
379 | } |
380 | ||
8a661aea | 381 | static void mips_magnum_class_init(ObjectClass *oc, void *data) |
e264d29d | 382 | { |
8a661aea AF |
383 | MachineClass *mc = MACHINE_CLASS(oc); |
384 | ||
e264d29d EH |
385 | mc->desc = "MIPS Magnum"; |
386 | mc->init = mips_magnum_init; | |
387 | mc->block_default_type = IF_SCSI; | |
3469e656 | 388 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); |
e264d29d | 389 | } |
c171148c | 390 | |
8a661aea AF |
391 | static const TypeInfo mips_magnum_type = { |
392 | .name = MACHINE_TYPE_NAME("magnum"), | |
393 | .parent = TYPE_MACHINE, | |
394 | .class_init = mips_magnum_class_init, | |
395 | }; | |
f80f9ec9 | 396 | |
8a661aea | 397 | static void mips_pica61_class_init(ObjectClass *oc, void *data) |
f80f9ec9 | 398 | { |
8a661aea AF |
399 | MachineClass *mc = MACHINE_CLASS(oc); |
400 | ||
e264d29d EH |
401 | mc->desc = "Acer Pica 61"; |
402 | mc->init = mips_pica61_init; | |
403 | mc->block_default_type = IF_SCSI; | |
3469e656 | 404 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); |
f80f9ec9 AL |
405 | } |
406 | ||
8a661aea AF |
407 | static const TypeInfo mips_pica61_type = { |
408 | .name = MACHINE_TYPE_NAME("pica61"), | |
409 | .parent = TYPE_MACHINE, | |
410 | .class_init = mips_pica61_class_init, | |
411 | }; | |
412 | ||
413 | static void mips_jazz_machine_init(void) | |
414 | { | |
415 | type_register_static(&mips_magnum_type); | |
416 | type_register_static(&mips_pica61_type); | |
417 | } | |
418 | ||
0e6aac87 | 419 | type_init(mips_jazz_machine_init) |