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CommitLineData
f0fc6f8f
TS
1/*
2 * QEMU/mipssim emulation
3 *
b5e4946f 4 * Emulates a very simple machine model similar to the one used by the
f0fc6f8f 5 * proprietary MIPS emulator.
a79ee211
TS
6 *
7 * Copyright (c) 2007 Thiemo Seufer
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
f0fc6f8f 26 */
c684822a 27#include "qemu/osdep.h"
da34e65c 28#include "qapi/error.h"
4771d756
PB
29#include "qemu-common.h"
30#include "cpu.h"
83c9f4ca 31#include "hw/hw.h"
0d09e41a
PB
32#include "hw/mips/mips.h"
33#include "hw/mips/cpudevs.h"
34#include "hw/char/serial.h"
35#include "hw/isa/isa.h"
1422e32d 36#include "net/net.h"
9c17d615 37#include "sysemu/sysemu.h"
83c9f4ca 38#include "hw/boards.h"
0d09e41a 39#include "hw/mips/bios.h"
83c9f4ca 40#include "hw/loader.h"
ca20cf32 41#include "elf.h"
83c9f4ca 42#include "hw/sysbus.h"
022c62cb 43#include "exec/address-spaces.h"
2e985fe0 44#include "qemu/error-report.h"
22d5523d 45#include "sysemu/qtest.h"
f0fc6f8f 46
7df526e3
TS
47static struct _loaderparams {
48 int ram_size;
49 const char *kernel_filename;
50 const char *kernel_cmdline;
51 const char *initrd_filename;
52} loaderparams;
53
e16ad5b0 54typedef struct ResetData {
2d44fc8e 55 MIPSCPU *cpu;
e16ad5b0
AJ
56 uint64_t vector;
57} ResetData;
58
59static int64_t load_kernel(void)
f0fc6f8f 60{
409dbce5 61 int64_t entry, kernel_high;
f0fc6f8f
TS
62 long kernel_size;
63 long initrd_size;
c227f099 64 ram_addr_t initrd_offset;
ca20cf32
BS
65 int big_endian;
66
67#ifdef TARGET_WORDS_BIGENDIAN
68 big_endian = 1;
69#else
70 big_endian = 0;
71#endif
f0fc6f8f 72
409dbce5
AJ
73 kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys,
74 NULL, (uint64_t *)&entry, NULL,
75 (uint64_t *)&kernel_high, big_endian,
7ef295ea 76 EM_MIPS, 1, 0);
f0fc6f8f
TS
77 if (kernel_size >= 0) {
78 if ((entry & ~0x7fffffffULL) == 0x80000000)
79 entry = (int32_t)entry;
f0fc6f8f
TS
80 } else {
81 fprintf(stderr, "qemu: could not load kernel '%s'\n",
7df526e3 82 loaderparams.kernel_filename);
f0fc6f8f
TS
83 exit(1);
84 }
85
86 /* load initrd */
87 initrd_size = 0;
88 initrd_offset = 0;
7df526e3
TS
89 if (loaderparams.initrd_filename) {
90 initrd_size = get_image_size (loaderparams.initrd_filename);
f0fc6f8f 91 if (initrd_size > 0) {
05b3274b 92 initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
7df526e3 93 if (initrd_offset + initrd_size > loaderparams.ram_size) {
f0fc6f8f
TS
94 fprintf(stderr,
95 "qemu: memory too small for initial ram disk '%s'\n",
7df526e3 96 loaderparams.initrd_filename);
f0fc6f8f
TS
97 exit(1);
98 }
dcac9679
PB
99 initrd_size = load_image_targphys(loaderparams.initrd_filename,
100 initrd_offset, loaderparams.ram_size - initrd_offset);
f0fc6f8f
TS
101 }
102 if (initrd_size == (target_ulong) -1) {
103 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
7df526e3 104 loaderparams.initrd_filename);
f0fc6f8f
TS
105 exit(1);
106 }
107 }
e16ad5b0 108 return entry;
f0fc6f8f
TS
109}
110
111static void main_cpu_reset(void *opaque)
112{
e16ad5b0 113 ResetData *s = (ResetData *)opaque;
2d44fc8e 114 CPUMIPSState *env = &s->cpu->env;
f0fc6f8f 115
2d44fc8e 116 cpu_reset(CPU(s->cpu));
aecf1376
NF
117 env->active_tc.PC = s->vector & ~(target_ulong)1;
118 if (s->vector & 1) {
119 env->hflags |= MIPS_HFLAG_M16;
120 }
f0fc6f8f
TS
121}
122
d118d64a
HP
123static void mipsnet_init(int base, qemu_irq irq, NICInfo *nd)
124{
125 DeviceState *dev;
126 SysBusDevice *s;
127
128 dev = qdev_create(NULL, "mipsnet");
129 qdev_set_nic_properties(dev, nd);
130 qdev_init_nofail(dev);
131
1356b98d 132 s = SYS_BUS_DEVICE(dev);
d118d64a
HP
133 sysbus_connect_irq(s, 0, irq);
134 memory_region_add_subregion(get_system_io(),
135 base,
136 sysbus_mmio_get_region(s, 0));
137}
138
f0fc6f8f 139static void
3ef96221 140mips_mipssim_init(MachineState *machine)
f0fc6f8f 141{
3ef96221
MA
142 ram_addr_t ram_size = machine->ram_size;
143 const char *cpu_model = machine->cpu_model;
144 const char *kernel_filename = machine->kernel_filename;
145 const char *kernel_cmdline = machine->kernel_cmdline;
146 const char *initrd_filename = machine->initrd_filename;
5cea8590 147 char *filename;
23ebf23d 148 MemoryRegion *address_space_mem = get_system_memory();
bdb75c79 149 MemoryRegion *isa = g_new(MemoryRegion, 1);
23ebf23d
AK
150 MemoryRegion *ram = g_new(MemoryRegion, 1);
151 MemoryRegion *bios = g_new(MemoryRegion, 1);
7ee274c1 152 MIPSCPU *cpu;
61c56c8c 153 CPUMIPSState *env;
e16ad5b0 154 ResetData *reset_info;
b5334159 155 int bios_size;
f0fc6f8f
TS
156
157 /* Init CPUs. */
158 if (cpu_model == NULL) {
159#ifdef TARGET_MIPS64
160 cpu_model = "5Kf";
161#else
162 cpu_model = "24Kf";
163#endif
164 }
7ee274c1
AF
165 cpu = cpu_mips_init(cpu_model);
166 if (cpu == NULL) {
aaed909a
FB
167 fprintf(stderr, "Unable to find CPU definition\n");
168 exit(1);
169 }
7ee274c1
AF
170 env = &cpu->env;
171
7267c094 172 reset_info = g_malloc0(sizeof(ResetData));
2d44fc8e 173 reset_info->cpu = cpu;
e16ad5b0
AJ
174 reset_info->vector = env->active_tc.PC;
175 qemu_register_reset(main_cpu_reset, reset_info);
f0fc6f8f
TS
176
177 /* Allocate RAM. */
6a926fbc
DM
178 memory_region_allocate_system_memory(ram, NULL, "mips_mipssim.ram",
179 ram_size);
98a99ce0 180 memory_region_init_ram(bios, NULL, "mips_mipssim.bios", BIOS_SIZE,
f8ed85ac 181 &error_fatal);
23ebf23d 182 memory_region_set_readonly(bios, true);
f0fc6f8f 183
23ebf23d 184 memory_region_add_subregion(address_space_mem, 0, ram);
dcac9679
PB
185
186 /* Map the BIOS / boot exception handler. */
23ebf23d 187 memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
f0fc6f8f
TS
188 /* Load a BIOS / boot exception handler image. */
189 if (bios_name == NULL)
190 bios_name = BIOS_FILENAME;
5cea8590
PB
191 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
192 if (filename) {
193 bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
7267c094 194 g_free(filename);
5cea8590
PB
195 } else {
196 bios_size = -1;
197 }
22d5523d
AF
198 if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
199 !kernel_filename && !qtest_enabled()) {
f0fc6f8f 200 /* Bail out if we have neither a kernel image nor boot vector code. */
2e985fe0 201 error_report("Could not load MIPS bios '%s', and no "
77e205a5 202 "-kernel argument was specified", bios_name);
2e985fe0 203 exit(1);
f0fc6f8f 204 } else {
b5334159 205 /* We have a boot vector start address. */
b5dc7732 206 env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
f0fc6f8f
TS
207 }
208
209 if (kernel_filename) {
7df526e3
TS
210 loaderparams.ram_size = ram_size;
211 loaderparams.kernel_filename = kernel_filename;
212 loaderparams.kernel_cmdline = kernel_cmdline;
213 loaderparams.initrd_filename = initrd_filename;
e16ad5b0 214 reset_info->vector = load_kernel();
f0fc6f8f
TS
215 }
216
217 /* Init CPU internal devices. */
5a975d43
PB
218 cpu_mips_irq_init_cpu(cpu);
219 cpu_mips_clock_init(cpu);
f0fc6f8f
TS
220
221 /* Register 64 KB of ISA IO space at 0x1fd00000. */
bdb75c79
PB
222 memory_region_init_alias(isa, NULL, "isa_mmio",
223 get_system_io(), 0, 0x00010000);
224 memory_region_add_subregion(get_system_memory(), 0x1fd00000, isa);
f0fc6f8f
TS
225
226 /* A single 16450 sits at offset 0x3f8. It is attached to
227 MIPS CPU INT2, which is interrupt 4. */
228 if (serial_hds[0])
568fd159
JG
229 serial_init(0x3f8, env->irq[4], 115200, serial_hds[0],
230 get_system_io());
f0fc6f8f 231
a005d073 232 if (nd_table[0].used)
0ae18cee
AL
233 /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
234 mipsnet_init(0x4200, env->irq[2], &nd_table[0]);
f0fc6f8f
TS
235}
236
e264d29d 237static void mips_mipssim_machine_init(MachineClass *mc)
f80f9ec9 238{
e264d29d
EH
239 mc->desc = "MIPS MIPSsim platform";
240 mc->init = mips_mipssim_init;
f80f9ec9
AL
241}
242
e264d29d 243DEFINE_MACHINE("mipssim", mips_mipssim_machine_init)