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include/qemu/osdep.h: Don't include qapi/error.h
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CommitLineData
e16fe40c
TS
1/*
2 * QEMU/MIPS pseudo-board
3 *
4 * emulates a simple machine with ISA-like bus.
5 * ISA IO space mapped to the 0x14000000 (PHYS) and
6 * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
7 * All peripherial devices are attached to this "bus" with
8 * the standard PC ISA addresses.
9*/
c684822a 10#include "qemu/osdep.h"
da34e65c 11#include "qapi/error.h"
83c9f4ca 12#include "hw/hw.h"
0d09e41a
PB
13#include "hw/mips/mips.h"
14#include "hw/mips/cpudevs.h"
15#include "hw/i386/pc.h"
16#include "hw/char/serial.h"
17#include "hw/isa/isa.h"
1422e32d 18#include "net/net.h"
9c17d615 19#include "sysemu/sysemu.h"
83c9f4ca 20#include "hw/boards.h"
0d09e41a 21#include "hw/block/flash.h"
1de7afc9 22#include "qemu/log.h"
0d09e41a 23#include "hw/mips/bios.h"
83c9f4ca
PB
24#include "hw/ide.h"
25#include "hw/loader.h"
ca20cf32 26#include "elf.h"
0d09e41a
PB
27#include "hw/timer/mc146818rtc.h"
28#include "hw/timer/i8254.h"
fa1d36df 29#include "sysemu/block-backend.h"
022c62cb 30#include "exec/address-spaces.h"
c9dd6a9f 31#include "sysemu/qtest.h"
44cbbf18 32
e4bcb14c
TS
33#define MAX_IDE_BUS 2
34
58126404
PB
35static const int ide_iobase[2] = { 0x1f0, 0x170 };
36static const int ide_iobase2[2] = { 0x3f6, 0x376 };
37static const int ide_irq[2] = { 14, 15 };
38
64d7e9a4 39static ISADevice *pit; /* PIT i8254 */
697584ab 40
1b66074b 41/* i8254 PIT is attached to the IRQ0 at PIC i8259 */
6af0bf9c 42
7df526e3
TS
43static struct _loaderparams {
44 int ram_size;
45 const char *kernel_filename;
46 const char *kernel_cmdline;
47 const char *initrd_filename;
48} loaderparams;
49
a8170e5e 50static void mips_qemu_write (void *opaque, hwaddr addr,
0ae16450 51 uint64_t val, unsigned size)
6ae81775
TS
52{
53 if ((addr & 0xffff) == 0 && val == 42)
54 qemu_system_reset_request ();
55 else if ((addr & 0xffff) == 4 && val == 42)
56 qemu_system_shutdown_request ();
57}
58
a8170e5e 59static uint64_t mips_qemu_read (void *opaque, hwaddr addr,
0ae16450 60 unsigned size)
6ae81775
TS
61{
62 return 0;
63}
64
0ae16450
AK
65static const MemoryRegionOps mips_qemu_ops = {
66 .read = mips_qemu_read,
67 .write = mips_qemu_write,
68 .endianness = DEVICE_NATIVE_ENDIAN,
6ae81775
TS
69};
70
e16ad5b0 71typedef struct ResetData {
fa156e51 72 MIPSCPU *cpu;
e16ad5b0
AJ
73 uint64_t vector;
74} ResetData;
75
76static int64_t load_kernel(void)
6ae81775 77{
409dbce5 78 int64_t entry, kernel_high;
e90e795e 79 long kernel_size, initrd_size, params_size;
c227f099 80 ram_addr_t initrd_offset;
e90e795e 81 uint32_t *params_buf;
ca20cf32 82 int big_endian;
6ae81775 83
ca20cf32
BS
84#ifdef TARGET_WORDS_BIGENDIAN
85 big_endian = 1;
86#else
87 big_endian = 0;
88#endif
409dbce5
AJ
89 kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys,
90 NULL, (uint64_t *)&entry, NULL,
91 (uint64_t *)&kernel_high, big_endian,
7ef295ea 92 EM_MIPS, 1, 0);
c570fd16
TS
93 if (kernel_size >= 0) {
94 if ((entry & ~0x7fffffffULL) == 0x80000000)
5dc4b744 95 entry = (int32_t)entry;
c570fd16 96 } else {
9042c0e2 97 fprintf(stderr, "qemu: could not load kernel '%s'\n",
7df526e3 98 loaderparams.kernel_filename);
9042c0e2 99 exit(1);
6ae81775
TS
100 }
101
102 /* load initrd */
103 initrd_size = 0;
74287114 104 initrd_offset = 0;
7df526e3
TS
105 if (loaderparams.initrd_filename) {
106 initrd_size = get_image_size (loaderparams.initrd_filename);
74287114 107 if (initrd_size > 0) {
05b3274b 108 initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
74287114
TS
109 if (initrd_offset + initrd_size > ram_size) {
110 fprintf(stderr,
111 "qemu: memory too small for initial ram disk '%s'\n",
7df526e3 112 loaderparams.initrd_filename);
74287114
TS
113 exit(1);
114 }
dcac9679
PB
115 initrd_size = load_image_targphys(loaderparams.initrd_filename,
116 initrd_offset,
117 ram_size - initrd_offset);
74287114 118 }
6ae81775
TS
119 if (initrd_size == (target_ulong) -1) {
120 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
7df526e3 121 loaderparams.initrd_filename);
6ae81775
TS
122 exit(1);
123 }
124 }
125
126 /* Store command line. */
e90e795e 127 params_size = 264;
7267c094 128 params_buf = g_malloc(params_size);
e90e795e
AJ
129
130 params_buf[0] = tswap32(ram_size);
131 params_buf[1] = tswap32(0x12345678);
132
6ae81775 133 if (initrd_size > 0) {
409dbce5
AJ
134 snprintf((char *)params_buf + 8, 256, "rd_start=0x%" PRIx64 " rd_size=%li %s",
135 cpu_mips_phys_to_kseg0(NULL, initrd_offset),
e90e795e 136 initrd_size, loaderparams.kernel_cmdline);
d7585251 137 } else {
e90e795e 138 snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline);
6ae81775
TS
139 }
140
e90e795e
AJ
141 rom_add_blob_fixed("params", params_buf, params_size,
142 (16 << 20) - 264);
143
3ad9fd5a 144 g_free(params_buf);
e16ad5b0 145 return entry;
6ae81775
TS
146}
147
148static void main_cpu_reset(void *opaque)
149{
e16ad5b0 150 ResetData *s = (ResetData *)opaque;
fa156e51 151 CPUMIPSState *env = &s->cpu->env;
6ae81775 152
fa156e51 153 cpu_reset(CPU(s->cpu));
e16ad5b0 154 env->active_tc.PC = s->vector;
6ae81775 155}
66a93e0f 156
b305b5ba 157static const int sector_len = 32 * 1024;
70705261 158static
3ef96221 159void mips_r4k_init(MachineState *machine)
6af0bf9c 160{
3ef96221
MA
161 ram_addr_t ram_size = machine->ram_size;
162 const char *cpu_model = machine->cpu_model;
163 const char *kernel_filename = machine->kernel_filename;
164 const char *kernel_cmdline = machine->kernel_cmdline;
165 const char *initrd_filename = machine->initrd_filename;
5cea8590 166 char *filename;
0ae16450
AK
167 MemoryRegion *address_space_mem = get_system_memory();
168 MemoryRegion *ram = g_new(MemoryRegion, 1);
cfe5f011 169 MemoryRegion *bios;
0ae16450 170 MemoryRegion *iomem = g_new(MemoryRegion, 1);
0c10962a
HP
171 MemoryRegion *isa_io = g_new(MemoryRegion, 1);
172 MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
f7bcd4e3 173 int bios_size;
9ac67e21 174 MIPSCPU *cpu;
61c56c8c 175 CPUMIPSState *env;
e16ad5b0 176 ResetData *reset_info;
58126404 177 int i;
d537cf6c 178 qemu_irq *i8259;
48a18b3c 179 ISABus *isa_bus;
f455e98c 180 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
751c6a17 181 DriveInfo *dinfo;
3d08ff69 182 int be;
c68ea704 183
33d68b5f
TS
184 /* init CPUs */
185 if (cpu_model == NULL) {
60aa19ab 186#ifdef TARGET_MIPS64
33d68b5f
TS
187 cpu_model = "R4000";
188#else
1c32f43e 189 cpu_model = "24Kf";
33d68b5f
TS
190#endif
191 }
9ac67e21
AF
192 cpu = cpu_mips_init(cpu_model);
193 if (cpu == NULL) {
aaed909a
FB
194 fprintf(stderr, "Unable to find CPU definition\n");
195 exit(1);
196 }
9ac67e21
AF
197 env = &cpu->env;
198
7267c094 199 reset_info = g_malloc0(sizeof(ResetData));
fa156e51 200 reset_info->cpu = cpu;
e16ad5b0
AJ
201 reset_info->vector = env->active_tc.PC;
202 qemu_register_reset(main_cpu_reset, reset_info);
c68ea704 203
6af0bf9c 204 /* allocate RAM */
0ccff151
AJ
205 if (ram_size > (256 << 20)) {
206 fprintf(stderr,
207 "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
208 ((unsigned int)ram_size / (1 << 20)));
209 exit(1);
210 }
6a926fbc 211 memory_region_allocate_system_memory(ram, NULL, "mips_r4k.ram", ram_size);
dcac9679 212
0ae16450 213 memory_region_add_subregion(address_space_mem, 0, ram);
66a93e0f 214
2c9b15ca 215 memory_region_init_io(iomem, NULL, &mips_qemu_ops, NULL, "mips-qemu", 0x10000);
0ae16450 216 memory_region_add_subregion(address_space_mem, 0x1fbf0000, iomem);
6ae81775 217
66a93e0f
FB
218 /* Try to load a BIOS image. If this fails, we continue regardless,
219 but initialize the hardware ourselves. When a kernel gets
220 preloaded we also initialize the hardware, since the BIOS wasn't
221 run. */
1192dad8
JM
222 if (bios_name == NULL)
223 bios_name = BIOS_FILENAME;
5cea8590
PB
224 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
225 if (filename) {
226 bios_size = get_image_size(filename);
227 } else {
228 bios_size = -1;
229 }
3d08ff69
BS
230#ifdef TARGET_WORDS_BIGENDIAN
231 be = 1;
232#else
233 be = 0;
234#endif
2909b29a 235 if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
cfe5f011 236 bios = g_new(MemoryRegion, 1);
49946538 237 memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE,
f8ed85ac 238 &error_fatal);
c5705a77 239 vmstate_register_ram_global(bios);
cfe5f011
AK
240 memory_region_set_readonly(bios, true);
241 memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios);
01e0451a 242
5cea8590 243 load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
751c6a17 244 } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) {
b305b5ba 245 uint32_t mips_rom = 0x00400000;
cfe5f011 246 if (!pflash_cfi01_register(0x1fc00000, NULL, "mips_r4k.bios", mips_rom,
4be74634 247 blk_by_legacy_dinfo(dinfo),
fa1d36df 248 sector_len, mips_rom / sector_len,
01e0451a 249 4, 0, 0, 0, 0, be)) {
b305b5ba
TS
250 fprintf(stderr, "qemu: Error registering flash memory.\n");
251 }
c9dd6a9f 252 } else if (!qtest_enabled()) {
66a93e0f
FB
253 /* not fatal */
254 fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
5cea8590
PB
255 bios_name);
256 }
ef1e1e07 257 g_free(filename);
66a93e0f 258
66a93e0f 259 if (kernel_filename) {
7df526e3
TS
260 loaderparams.ram_size = ram_size;
261 loaderparams.kernel_filename = kernel_filename;
262 loaderparams.kernel_cmdline = kernel_cmdline;
263 loaderparams.initrd_filename = initrd_filename;
e16ad5b0 264 reset_info->vector = load_kernel();
6af0bf9c 265 }
6af0bf9c 266
e16fe40c 267 /* Init CPU internal devices */
d537cf6c 268 cpu_mips_irq_init_cpu(env);
c68ea704 269 cpu_mips_clock_init(env);
6af0bf9c 270
0c10962a
HP
271 /* ISA bus: IO space at 0x14000000, mem space at 0x10000000 */
272 memory_region_init_alias(isa_io, NULL, "isa-io",
273 get_system_io(), 0, 0x00010000);
274 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
275 memory_region_add_subregion(get_system_memory(), 0x14000000, isa_io);
276 memory_region_add_subregion(get_system_memory(), 0x10000000, isa_mem);
d10e5432 277 isa_bus = isa_bus_new(NULL, isa_mem, get_system_io(), &error_abort);
0c10962a 278
d537cf6c 279 /* The PIC is attached to the MIPS CPU INT0 pin */
48a18b3c
HP
280 i8259 = i8259_init(isa_bus, env->irq[2]);
281 isa_bus_irqs(isa_bus, i8259);
d537cf6c 282
48a18b3c 283 rtc_init(isa_bus, 2000, NULL);
afdfa781 284
319ba9f5 285 pit = pit_init(isa_bus, 0x40, 0, NULL);
afdfa781 286
b6607a1a 287 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS);
eddbd288 288
f642dfce 289 isa_vga_init(isa_bus);
9827e95c 290
a005d073 291 if (nd_table[0].used)
48a18b3c 292 isa_ne2000_init(isa_bus, 0x300, 9, &nd_table[0]);
58126404 293
d8f94e1b 294 ide_drive_get(hd, ARRAY_SIZE(hd));
e4bcb14c 295 for(i = 0; i < MAX_IDE_BUS; i++)
48a18b3c 296 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
e4bcb14c
TS
297 hd[MAX_IDE_DEVS * i],
298 hd[MAX_IDE_DEVS * i + 1]);
70705261 299
48a18b3c 300 isa_create_simple(isa_bus, "i8042");
6af0bf9c
FB
301}
302
e264d29d 303static void mips_machine_init(MachineClass *mc)
f80f9ec9 304{
e264d29d
EH
305 mc->desc = "mips r4k platform";
306 mc->init = mips_r4k_init;
f80f9ec9
AL
307}
308
e264d29d 309DEFINE_MACHINE("mips", mips_machine_init)