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e16fe40c
TS
1/*
2 * QEMU/MIPS pseudo-board
3 *
4 * emulates a simple machine with ISA-like bus.
5 * ISA IO space mapped to the 0x14000000 (PHYS) and
6 * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
7 * All peripherial devices are attached to this "bus" with
8 * the standard PC ISA addresses.
9*/
83c9f4ca 10#include "hw/hw.h"
0d09e41a
PB
11#include "hw/mips/mips.h"
12#include "hw/mips/cpudevs.h"
13#include "hw/i386/pc.h"
14#include "hw/char/serial.h"
15#include "hw/isa/isa.h"
1422e32d 16#include "net/net.h"
9c17d615 17#include "sysemu/sysemu.h"
83c9f4ca 18#include "hw/boards.h"
0d09e41a 19#include "hw/block/flash.h"
1de7afc9 20#include "qemu/log.h"
0d09e41a 21#include "hw/mips/bios.h"
83c9f4ca
PB
22#include "hw/ide.h"
23#include "hw/loader.h"
ca20cf32 24#include "elf.h"
0d09e41a
PB
25#include "hw/timer/mc146818rtc.h"
26#include "hw/timer/i8254.h"
fa1d36df 27#include "sysemu/block-backend.h"
022c62cb 28#include "exec/address-spaces.h"
c9dd6a9f 29#include "sysemu/qtest.h"
44cbbf18 30
e4bcb14c
TS
31#define MAX_IDE_BUS 2
32
58126404
PB
33static const int ide_iobase[2] = { 0x1f0, 0x170 };
34static const int ide_iobase2[2] = { 0x3f6, 0x376 };
35static const int ide_irq[2] = { 14, 15 };
36
64d7e9a4 37static ISADevice *pit; /* PIT i8254 */
697584ab 38
1b66074b 39/* i8254 PIT is attached to the IRQ0 at PIC i8259 */
6af0bf9c 40
7df526e3
TS
41static struct _loaderparams {
42 int ram_size;
43 const char *kernel_filename;
44 const char *kernel_cmdline;
45 const char *initrd_filename;
46} loaderparams;
47
a8170e5e 48static void mips_qemu_write (void *opaque, hwaddr addr,
0ae16450 49 uint64_t val, unsigned size)
6ae81775
TS
50{
51 if ((addr & 0xffff) == 0 && val == 42)
52 qemu_system_reset_request ();
53 else if ((addr & 0xffff) == 4 && val == 42)
54 qemu_system_shutdown_request ();
55}
56
a8170e5e 57static uint64_t mips_qemu_read (void *opaque, hwaddr addr,
0ae16450 58 unsigned size)
6ae81775
TS
59{
60 return 0;
61}
62
0ae16450
AK
63static const MemoryRegionOps mips_qemu_ops = {
64 .read = mips_qemu_read,
65 .write = mips_qemu_write,
66 .endianness = DEVICE_NATIVE_ENDIAN,
6ae81775
TS
67};
68
e16ad5b0 69typedef struct ResetData {
fa156e51 70 MIPSCPU *cpu;
e16ad5b0
AJ
71 uint64_t vector;
72} ResetData;
73
74static int64_t load_kernel(void)
6ae81775 75{
409dbce5 76 int64_t entry, kernel_high;
e90e795e 77 long kernel_size, initrd_size, params_size;
c227f099 78 ram_addr_t initrd_offset;
e90e795e 79 uint32_t *params_buf;
ca20cf32 80 int big_endian;
6ae81775 81
ca20cf32
BS
82#ifdef TARGET_WORDS_BIGENDIAN
83 big_endian = 1;
84#else
85 big_endian = 0;
86#endif
409dbce5
AJ
87 kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys,
88 NULL, (uint64_t *)&entry, NULL,
89 (uint64_t *)&kernel_high, big_endian,
90 ELF_MACHINE, 1);
c570fd16
TS
91 if (kernel_size >= 0) {
92 if ((entry & ~0x7fffffffULL) == 0x80000000)
5dc4b744 93 entry = (int32_t)entry;
c570fd16 94 } else {
9042c0e2 95 fprintf(stderr, "qemu: could not load kernel '%s'\n",
7df526e3 96 loaderparams.kernel_filename);
9042c0e2 97 exit(1);
6ae81775
TS
98 }
99
100 /* load initrd */
101 initrd_size = 0;
74287114 102 initrd_offset = 0;
7df526e3
TS
103 if (loaderparams.initrd_filename) {
104 initrd_size = get_image_size (loaderparams.initrd_filename);
74287114 105 if (initrd_size > 0) {
05b3274b 106 initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
74287114
TS
107 if (initrd_offset + initrd_size > ram_size) {
108 fprintf(stderr,
109 "qemu: memory too small for initial ram disk '%s'\n",
7df526e3 110 loaderparams.initrd_filename);
74287114
TS
111 exit(1);
112 }
dcac9679
PB
113 initrd_size = load_image_targphys(loaderparams.initrd_filename,
114 initrd_offset,
115 ram_size - initrd_offset);
74287114 116 }
6ae81775
TS
117 if (initrd_size == (target_ulong) -1) {
118 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
7df526e3 119 loaderparams.initrd_filename);
6ae81775
TS
120 exit(1);
121 }
122 }
123
124 /* Store command line. */
e90e795e 125 params_size = 264;
7267c094 126 params_buf = g_malloc(params_size);
e90e795e
AJ
127
128 params_buf[0] = tswap32(ram_size);
129 params_buf[1] = tswap32(0x12345678);
130
6ae81775 131 if (initrd_size > 0) {
409dbce5
AJ
132 snprintf((char *)params_buf + 8, 256, "rd_start=0x%" PRIx64 " rd_size=%li %s",
133 cpu_mips_phys_to_kseg0(NULL, initrd_offset),
e90e795e 134 initrd_size, loaderparams.kernel_cmdline);
d7585251 135 } else {
e90e795e 136 snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline);
6ae81775
TS
137 }
138
e90e795e
AJ
139 rom_add_blob_fixed("params", params_buf, params_size,
140 (16 << 20) - 264);
141
3ad9fd5a 142 g_free(params_buf);
e16ad5b0 143 return entry;
6ae81775
TS
144}
145
146static void main_cpu_reset(void *opaque)
147{
e16ad5b0 148 ResetData *s = (ResetData *)opaque;
fa156e51 149 CPUMIPSState *env = &s->cpu->env;
6ae81775 150
fa156e51 151 cpu_reset(CPU(s->cpu));
e16ad5b0 152 env->active_tc.PC = s->vector;
6ae81775 153}
66a93e0f 154
b305b5ba 155static const int sector_len = 32 * 1024;
70705261 156static
3ef96221 157void mips_r4k_init(MachineState *machine)
6af0bf9c 158{
3ef96221
MA
159 ram_addr_t ram_size = machine->ram_size;
160 const char *cpu_model = machine->cpu_model;
161 const char *kernel_filename = machine->kernel_filename;
162 const char *kernel_cmdline = machine->kernel_cmdline;
163 const char *initrd_filename = machine->initrd_filename;
5cea8590 164 char *filename;
0ae16450
AK
165 MemoryRegion *address_space_mem = get_system_memory();
166 MemoryRegion *ram = g_new(MemoryRegion, 1);
cfe5f011 167 MemoryRegion *bios;
0ae16450 168 MemoryRegion *iomem = g_new(MemoryRegion, 1);
0c10962a
HP
169 MemoryRegion *isa_io = g_new(MemoryRegion, 1);
170 MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
f7bcd4e3 171 int bios_size;
9ac67e21 172 MIPSCPU *cpu;
61c56c8c 173 CPUMIPSState *env;
e16ad5b0 174 ResetData *reset_info;
58126404 175 int i;
d537cf6c 176 qemu_irq *i8259;
48a18b3c 177 ISABus *isa_bus;
f455e98c 178 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
751c6a17 179 DriveInfo *dinfo;
3d08ff69 180 int be;
c68ea704 181
33d68b5f
TS
182 /* init CPUs */
183 if (cpu_model == NULL) {
60aa19ab 184#ifdef TARGET_MIPS64
33d68b5f
TS
185 cpu_model = "R4000";
186#else
1c32f43e 187 cpu_model = "24Kf";
33d68b5f
TS
188#endif
189 }
9ac67e21
AF
190 cpu = cpu_mips_init(cpu_model);
191 if (cpu == NULL) {
aaed909a
FB
192 fprintf(stderr, "Unable to find CPU definition\n");
193 exit(1);
194 }
9ac67e21
AF
195 env = &cpu->env;
196
7267c094 197 reset_info = g_malloc0(sizeof(ResetData));
fa156e51 198 reset_info->cpu = cpu;
e16ad5b0
AJ
199 reset_info->vector = env->active_tc.PC;
200 qemu_register_reset(main_cpu_reset, reset_info);
c68ea704 201
6af0bf9c 202 /* allocate RAM */
0ccff151
AJ
203 if (ram_size > (256 << 20)) {
204 fprintf(stderr,
205 "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
206 ((unsigned int)ram_size / (1 << 20)));
207 exit(1);
208 }
6a926fbc 209 memory_region_allocate_system_memory(ram, NULL, "mips_r4k.ram", ram_size);
dcac9679 210
0ae16450 211 memory_region_add_subregion(address_space_mem, 0, ram);
66a93e0f 212
2c9b15ca 213 memory_region_init_io(iomem, NULL, &mips_qemu_ops, NULL, "mips-qemu", 0x10000);
0ae16450 214 memory_region_add_subregion(address_space_mem, 0x1fbf0000, iomem);
6ae81775 215
66a93e0f
FB
216 /* Try to load a BIOS image. If this fails, we continue regardless,
217 but initialize the hardware ourselves. When a kernel gets
218 preloaded we also initialize the hardware, since the BIOS wasn't
219 run. */
1192dad8
JM
220 if (bios_name == NULL)
221 bios_name = BIOS_FILENAME;
5cea8590
PB
222 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
223 if (filename) {
224 bios_size = get_image_size(filename);
225 } else {
226 bios_size = -1;
227 }
3d08ff69
BS
228#ifdef TARGET_WORDS_BIGENDIAN
229 be = 1;
230#else
231 be = 0;
232#endif
2909b29a 233 if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
cfe5f011 234 bios = g_new(MemoryRegion, 1);
49946538 235 memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE,
f8ed85ac 236 &error_fatal);
c5705a77 237 vmstate_register_ram_global(bios);
cfe5f011
AK
238 memory_region_set_readonly(bios, true);
239 memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios);
01e0451a 240
5cea8590 241 load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
751c6a17 242 } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) {
b305b5ba 243 uint32_t mips_rom = 0x00400000;
cfe5f011 244 if (!pflash_cfi01_register(0x1fc00000, NULL, "mips_r4k.bios", mips_rom,
4be74634 245 blk_by_legacy_dinfo(dinfo),
fa1d36df 246 sector_len, mips_rom / sector_len,
01e0451a 247 4, 0, 0, 0, 0, be)) {
b305b5ba
TS
248 fprintf(stderr, "qemu: Error registering flash memory.\n");
249 }
c9dd6a9f 250 } else if (!qtest_enabled()) {
66a93e0f
FB
251 /* not fatal */
252 fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
5cea8590
PB
253 bios_name);
254 }
ef1e1e07 255 g_free(filename);
66a93e0f 256
66a93e0f 257 if (kernel_filename) {
7df526e3
TS
258 loaderparams.ram_size = ram_size;
259 loaderparams.kernel_filename = kernel_filename;
260 loaderparams.kernel_cmdline = kernel_cmdline;
261 loaderparams.initrd_filename = initrd_filename;
e16ad5b0 262 reset_info->vector = load_kernel();
6af0bf9c 263 }
6af0bf9c 264
e16fe40c 265 /* Init CPU internal devices */
d537cf6c 266 cpu_mips_irq_init_cpu(env);
c68ea704 267 cpu_mips_clock_init(env);
6af0bf9c 268
0c10962a
HP
269 /* ISA bus: IO space at 0x14000000, mem space at 0x10000000 */
270 memory_region_init_alias(isa_io, NULL, "isa-io",
271 get_system_io(), 0, 0x00010000);
272 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
273 memory_region_add_subregion(get_system_memory(), 0x14000000, isa_io);
274 memory_region_add_subregion(get_system_memory(), 0x10000000, isa_mem);
275 isa_bus = isa_bus_new(NULL, isa_mem, get_system_io());
276
d537cf6c 277 /* The PIC is attached to the MIPS CPU INT0 pin */
48a18b3c
HP
278 i8259 = i8259_init(isa_bus, env->irq[2]);
279 isa_bus_irqs(isa_bus, i8259);
d537cf6c 280
48a18b3c 281 rtc_init(isa_bus, 2000, NULL);
afdfa781 282
319ba9f5 283 pit = pit_init(isa_bus, 0x40, 0, NULL);
afdfa781 284
b6607a1a 285 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS);
eddbd288 286
f642dfce 287 isa_vga_init(isa_bus);
9827e95c 288
a005d073 289 if (nd_table[0].used)
48a18b3c 290 isa_ne2000_init(isa_bus, 0x300, 9, &nd_table[0]);
58126404 291
d8f94e1b 292 ide_drive_get(hd, ARRAY_SIZE(hd));
e4bcb14c 293 for(i = 0; i < MAX_IDE_BUS; i++)
48a18b3c 294 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
e4bcb14c
TS
295 hd[MAX_IDE_DEVS * i],
296 hd[MAX_IDE_DEVS * i + 1]);
70705261 297
48a18b3c 298 isa_create_simple(isa_bus, "i8042");
6af0bf9c
FB
299}
300
f80f9ec9 301static QEMUMachine mips_machine = {
eec2743e
TS
302 .name = "mips",
303 .desc = "mips r4k platform",
304 .init = mips_r4k_init,
6af0bf9c 305};
f80f9ec9
AL
306
307static void mips_machine_init(void)
308{
309 qemu_register_machine(&mips_machine);
310}
311
312machine_init(mips_machine_init);