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Commit | Line | Data |
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f0fc6f8f TS |
1 | /* |
2 | * QEMU/mipssim emulation | |
3 | * | |
b5e4946f | 4 | * Emulates a very simple machine model similar to the one used by the |
f0fc6f8f | 5 | * proprietary MIPS emulator. |
33dd6f44 | 6 | * |
a79ee211 TS |
7 | * Copyright (c) 2007 Thiemo Seufer |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
10 | * of this software and associated documentation files (the "Software"), to deal | |
11 | * in the Software without restriction, including without limitation the rights | |
12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
13 | * copies of the Software, and to permit persons to whom the Software is | |
14 | * furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice shall be included in | |
17 | * all copies or substantial portions of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
25 | * THE SOFTWARE. | |
f0fc6f8f | 26 | */ |
71e8a915 | 27 | |
c684822a | 28 | #include "qemu/osdep.h" |
da34e65c | 29 | #include "qapi/error.h" |
4771d756 PB |
30 | #include "qemu-common.h" |
31 | #include "cpu.h" | |
0d09e41a PB |
32 | #include "hw/mips/mips.h" |
33 | #include "hw/mips/cpudevs.h" | |
34 | #include "hw/char/serial.h" | |
35 | #include "hw/isa/isa.h" | |
1422e32d | 36 | #include "net/net.h" |
9c17d615 | 37 | #include "sysemu/sysemu.h" |
83c9f4ca | 38 | #include "hw/boards.h" |
0d09e41a | 39 | #include "hw/mips/bios.h" |
83c9f4ca | 40 | #include "hw/loader.h" |
ca20cf32 | 41 | #include "elf.h" |
83c9f4ca | 42 | #include "hw/sysbus.h" |
9fac5d88 | 43 | #include "hw/qdev-properties.h" |
022c62cb | 44 | #include "exec/address-spaces.h" |
2e985fe0 | 45 | #include "qemu/error-report.h" |
22d5523d | 46 | #include "sysemu/qtest.h" |
71e8a915 | 47 | #include "sysemu/reset.h" |
f0fc6f8f | 48 | |
7df526e3 TS |
49 | static struct _loaderparams { |
50 | int ram_size; | |
51 | const char *kernel_filename; | |
52 | const char *kernel_cmdline; | |
53 | const char *initrd_filename; | |
54 | } loaderparams; | |
55 | ||
e16ad5b0 | 56 | typedef struct ResetData { |
2d44fc8e | 57 | MIPSCPU *cpu; |
e16ad5b0 AJ |
58 | uint64_t vector; |
59 | } ResetData; | |
60 | ||
61 | static int64_t load_kernel(void) | |
f0fc6f8f | 62 | { |
f3839fda | 63 | int64_t entry, kernel_high, initrd_size; |
f0fc6f8f | 64 | long kernel_size; |
c227f099 | 65 | ram_addr_t initrd_offset; |
ca20cf32 BS |
66 | int big_endian; |
67 | ||
68 | #ifdef TARGET_WORDS_BIGENDIAN | |
69 | big_endian = 1; | |
70 | #else | |
71 | big_endian = 0; | |
72 | #endif | |
f0fc6f8f | 73 | |
4366e1db LM |
74 | kernel_size = load_elf(loaderparams.kernel_filename, NULL, |
75 | cpu_mips_kseg0_to_phys, NULL, | |
76 | (uint64_t *)&entry, NULL, | |
6cdda0ff | 77 | (uint64_t *)&kernel_high, NULL, big_endian, |
7ef295ea | 78 | EM_MIPS, 1, 0); |
f0fc6f8f | 79 | if (kernel_size >= 0) { |
33dd6f44 | 80 | if ((entry & ~0x7fffffffULL) == 0x80000000) { |
f0fc6f8f | 81 | entry = (int32_t)entry; |
33dd6f44 | 82 | } |
f0fc6f8f | 83 | } else { |
bd6e1d81 | 84 | error_report("could not load kernel '%s': %s", |
3ee3122c AJ |
85 | loaderparams.kernel_filename, |
86 | load_elf_strerror(kernel_size)); | |
f0fc6f8f TS |
87 | exit(1); |
88 | } | |
89 | ||
90 | /* load initrd */ | |
91 | initrd_size = 0; | |
92 | initrd_offset = 0; | |
7df526e3 | 93 | if (loaderparams.initrd_filename) { |
33dd6f44 | 94 | initrd_size = get_image_size(loaderparams.initrd_filename); |
f0fc6f8f | 95 | if (initrd_size > 0) { |
33dd6f44 AM |
96 | initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & |
97 | INITRD_PAGE_MASK; | |
7df526e3 | 98 | if (initrd_offset + initrd_size > loaderparams.ram_size) { |
bd6e1d81 AF |
99 | error_report("memory too small for initial ram disk '%s'", |
100 | loaderparams.initrd_filename); | |
f0fc6f8f TS |
101 | exit(1); |
102 | } | |
dcac9679 PB |
103 | initrd_size = load_image_targphys(loaderparams.initrd_filename, |
104 | initrd_offset, loaderparams.ram_size - initrd_offset); | |
f0fc6f8f TS |
105 | } |
106 | if (initrd_size == (target_ulong) -1) { | |
bd6e1d81 AF |
107 | error_report("could not load initial ram disk '%s'", |
108 | loaderparams.initrd_filename); | |
f0fc6f8f TS |
109 | exit(1); |
110 | } | |
111 | } | |
e16ad5b0 | 112 | return entry; |
f0fc6f8f TS |
113 | } |
114 | ||
115 | static void main_cpu_reset(void *opaque) | |
116 | { | |
e16ad5b0 | 117 | ResetData *s = (ResetData *)opaque; |
2d44fc8e | 118 | CPUMIPSState *env = &s->cpu->env; |
f0fc6f8f | 119 | |
2d44fc8e | 120 | cpu_reset(CPU(s->cpu)); |
aecf1376 NF |
121 | env->active_tc.PC = s->vector & ~(target_ulong)1; |
122 | if (s->vector & 1) { | |
123 | env->hflags |= MIPS_HFLAG_M16; | |
124 | } | |
f0fc6f8f TS |
125 | } |
126 | ||
d118d64a HP |
127 | static void mipsnet_init(int base, qemu_irq irq, NICInfo *nd) |
128 | { | |
129 | DeviceState *dev; | |
130 | SysBusDevice *s; | |
131 | ||
3e80f690 | 132 | dev = qdev_new("mipsnet"); |
d118d64a | 133 | qdev_set_nic_properties(dev, nd); |
d118d64a | 134 | |
1356b98d | 135 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 136 | sysbus_realize_and_unref(s, &error_fatal); |
d118d64a HP |
137 | sysbus_connect_irq(s, 0, irq); |
138 | memory_region_add_subregion(get_system_io(), | |
139 | base, | |
140 | sysbus_mmio_get_region(s, 0)); | |
141 | } | |
142 | ||
f0fc6f8f | 143 | static void |
3ef96221 | 144 | mips_mipssim_init(MachineState *machine) |
f0fc6f8f | 145 | { |
3ef96221 MA |
146 | const char *kernel_filename = machine->kernel_filename; |
147 | const char *kernel_cmdline = machine->kernel_cmdline; | |
148 | const char *initrd_filename = machine->initrd_filename; | |
5cea8590 | 149 | char *filename; |
23ebf23d | 150 | MemoryRegion *address_space_mem = get_system_memory(); |
bdb75c79 | 151 | MemoryRegion *isa = g_new(MemoryRegion, 1); |
23ebf23d | 152 | MemoryRegion *bios = g_new(MemoryRegion, 1); |
7ee274c1 | 153 | MIPSCPU *cpu; |
61c56c8c | 154 | CPUMIPSState *env; |
e16ad5b0 | 155 | ResetData *reset_info; |
b5334159 | 156 | int bios_size; |
f0fc6f8f TS |
157 | |
158 | /* Init CPUs. */ | |
0fc52fd2 | 159 | cpu = MIPS_CPU(cpu_create(machine->cpu_type)); |
7ee274c1 AF |
160 | env = &cpu->env; |
161 | ||
7267c094 | 162 | reset_info = g_malloc0(sizeof(ResetData)); |
2d44fc8e | 163 | reset_info->cpu = cpu; |
e16ad5b0 AJ |
164 | reset_info->vector = env->active_tc.PC; |
165 | qemu_register_reset(main_cpu_reset, reset_info); | |
f0fc6f8f TS |
166 | |
167 | /* Allocate RAM. */ | |
3fab7f23 | 168 | memory_region_init_rom(bios, NULL, "mips_mipssim.bios", BIOS_SIZE, |
f8ed85ac | 169 | &error_fatal); |
f0fc6f8f | 170 | |
ceefaa3b | 171 | memory_region_add_subregion(address_space_mem, 0, machine->ram); |
dcac9679 PB |
172 | |
173 | /* Map the BIOS / boot exception handler. */ | |
23ebf23d | 174 | memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios); |
f0fc6f8f | 175 | /* Load a BIOS / boot exception handler image. */ |
33dd6f44 | 176 | if (bios_name == NULL) { |
f0fc6f8f | 177 | bios_name = BIOS_FILENAME; |
33dd6f44 | 178 | } |
5cea8590 PB |
179 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
180 | if (filename) { | |
181 | bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE); | |
7267c094 | 182 | g_free(filename); |
5cea8590 PB |
183 | } else { |
184 | bios_size = -1; | |
185 | } | |
22d5523d AF |
186 | if ((bios_size < 0 || bios_size > BIOS_SIZE) && |
187 | !kernel_filename && !qtest_enabled()) { | |
f0fc6f8f | 188 | /* Bail out if we have neither a kernel image nor boot vector code. */ |
2e985fe0 | 189 | error_report("Could not load MIPS bios '%s', and no " |
77e205a5 | 190 | "-kernel argument was specified", bios_name); |
2e985fe0 | 191 | exit(1); |
f0fc6f8f | 192 | } else { |
b5334159 | 193 | /* We have a boot vector start address. */ |
b5dc7732 | 194 | env->active_tc.PC = (target_long)(int32_t)0xbfc00000; |
f0fc6f8f TS |
195 | } |
196 | ||
197 | if (kernel_filename) { | |
ceefaa3b | 198 | loaderparams.ram_size = machine->ram_size; |
7df526e3 TS |
199 | loaderparams.kernel_filename = kernel_filename; |
200 | loaderparams.kernel_cmdline = kernel_cmdline; | |
201 | loaderparams.initrd_filename = initrd_filename; | |
e16ad5b0 | 202 | reset_info->vector = load_kernel(); |
f0fc6f8f TS |
203 | } |
204 | ||
205 | /* Init CPU internal devices. */ | |
5a975d43 PB |
206 | cpu_mips_irq_init_cpu(cpu); |
207 | cpu_mips_clock_init(cpu); | |
f0fc6f8f TS |
208 | |
209 | /* Register 64 KB of ISA IO space at 0x1fd00000. */ | |
bdb75c79 PB |
210 | memory_region_init_alias(isa, NULL, "isa_mmio", |
211 | get_system_io(), 0, 0x00010000); | |
212 | memory_region_add_subregion(get_system_memory(), 0x1fd00000, isa); | |
f0fc6f8f | 213 | |
33dd6f44 AM |
214 | /* |
215 | * A single 16450 sits at offset 0x3f8. It is attached to | |
216 | * MIPS CPU INT2, which is interrupt 4. | |
217 | */ | |
9fac5d88 | 218 | if (serial_hd(0)) { |
3e80f690 | 219 | DeviceState *dev = qdev_new(TYPE_SERIAL_IO); |
9fac5d88 | 220 | |
9fac5d88 MAL |
221 | qdev_prop_set_chr(dev, "chardev", serial_hd(0)); |
222 | qdev_set_legacy_instance_id(dev, 0x3f8, 2); | |
3c6ef471 | 223 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
9fac5d88 | 224 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]); |
d9259178 MAL |
225 | sysbus_add_io(SYS_BUS_DEVICE(dev), 0x3f8, |
226 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); | |
9fac5d88 | 227 | } |
f0fc6f8f | 228 | |
a005d073 | 229 | if (nd_table[0].used) |
0ae18cee AL |
230 | /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */ |
231 | mipsnet_init(0x4200, env->irq[2], &nd_table[0]); | |
f0fc6f8f TS |
232 | } |
233 | ||
e264d29d | 234 | static void mips_mipssim_machine_init(MachineClass *mc) |
f80f9ec9 | 235 | { |
e264d29d EH |
236 | mc->desc = "MIPS MIPSsim platform"; |
237 | mc->init = mips_mipssim_init; | |
0fc52fd2 IM |
238 | #ifdef TARGET_MIPS64 |
239 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("5Kf"); | |
240 | #else | |
241 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); | |
242 | #endif | |
ceefaa3b | 243 | mc->default_ram_id = "mips_mipssim.ram"; |
f80f9ec9 AL |
244 | } |
245 | ||
e264d29d | 246 | DEFINE_MACHINE("mipssim", mips_mipssim_machine_init) |