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Commit | Line | Data |
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4ce7ff6e AJ |
1 | /* |
2 | * QEMU MIPS Jazz support | |
3 | * | |
4 | * Copyright (c) 2007-2008 Hervé Poussineau | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "hw.h" | |
26 | #include "mips.h" | |
b970ea8f | 27 | #include "mips_cpudevs.h" |
4ce7ff6e AJ |
28 | #include "pc.h" |
29 | #include "isa.h" | |
30 | #include "fdc.h" | |
31 | #include "sysemu.h" | |
0dfa5ef9 | 32 | #include "arch_init.h" |
4ce7ff6e AJ |
33 | #include "boards.h" |
34 | #include "net.h" | |
1cd3af54 | 35 | #include "esp.h" |
bba831e8 | 36 | #include "mips-bios.h" |
ca20cf32 | 37 | #include "loader.h" |
1d914fa0 | 38 | #include "mc146818rtc.h" |
b1277b03 | 39 | #include "i8254.h" |
2446333c | 40 | #include "blockdev.h" |
cd3e2409 | 41 | #include "sysbus.h" |
be20f9e9 | 42 | #include "exec-memory.h" |
4ce7ff6e | 43 | |
4ce7ff6e AJ |
44 | enum jazz_model_e |
45 | { | |
46 | JAZZ_MAGNUM, | |
c171148c | 47 | JAZZ_PICA61, |
4ce7ff6e AJ |
48 | }; |
49 | ||
50 | static void main_cpu_reset(void *opaque) | |
51 | { | |
52 | CPUState *env = opaque; | |
53 | cpu_reset(env); | |
54 | } | |
55 | ||
60581b37 | 56 | static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size) |
4ce7ff6e | 57 | { |
afcea8cb | 58 | return cpu_inw(0x71); |
4ce7ff6e AJ |
59 | } |
60 | ||
60581b37 AK |
61 | static void rtc_write(void *opaque, target_phys_addr_t addr, |
62 | uint64_t val, unsigned size) | |
4ce7ff6e | 63 | { |
afcea8cb | 64 | cpu_outw(0x71, val & 0xff); |
4ce7ff6e AJ |
65 | } |
66 | ||
60581b37 AK |
67 | static const MemoryRegionOps rtc_ops = { |
68 | .read = rtc_read, | |
69 | .write = rtc_write, | |
70 | .endianness = DEVICE_NATIVE_ENDIAN, | |
4ce7ff6e AJ |
71 | }; |
72 | ||
60581b37 AK |
73 | static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr, |
74 | unsigned size) | |
c6945b15 AJ |
75 | { |
76 | /* Nothing to do. That is only to ensure that | |
77 | * the current DMA acknowledge cycle is completed. */ | |
60581b37 | 78 | return 0xff; |
c6945b15 AJ |
79 | } |
80 | ||
60581b37 AK |
81 | static void dma_dummy_write(void *opaque, target_phys_addr_t addr, |
82 | uint64_t val, unsigned size) | |
83 | { | |
84 | /* Nothing to do. That is only to ensure that | |
85 | * the current DMA acknowledge cycle is completed. */ | |
86 | } | |
c6945b15 | 87 | |
60581b37 AK |
88 | static const MemoryRegionOps dma_dummy_ops = { |
89 | .read = dma_dummy_read, | |
90 | .write = dma_dummy_write, | |
91 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c6945b15 AJ |
92 | }; |
93 | ||
4ce7ff6e AJ |
94 | #define MAGNUM_BIOS_SIZE_MAX 0x7e000 |
95 | #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) | |
96 | ||
4556bd8b BS |
97 | static void cpu_request_exit(void *opaque, int irq, int level) |
98 | { | |
99 | CPUState *env = cpu_single_env; | |
100 | ||
101 | if (env && level) { | |
102 | cpu_exit(env); | |
103 | } | |
104 | } | |
105 | ||
c2d0d012 RH |
106 | static void mips_jazz_init(MemoryRegion *address_space, |
107 | MemoryRegion *address_space_io, | |
108 | ram_addr_t ram_size, | |
109 | const char *cpu_model, | |
110 | enum jazz_model_e jazz_model) | |
4ce7ff6e | 111 | { |
5cea8590 | 112 | char *filename; |
4ce7ff6e AJ |
113 | int bios_size, n; |
114 | CPUState *env; | |
115 | qemu_irq *rc4030, *i8259; | |
c6945b15 | 116 | rc4030_dma *dmas; |
68238a9e | 117 | void* rc4030_opaque; |
60581b37 | 118 | MemoryRegion *rtc = g_new(MemoryRegion, 1); |
dbff76ac | 119 | MemoryRegion *i8042 = g_new(MemoryRegion, 1); |
60581b37 | 120 | MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); |
a65f56ee | 121 | NICInfo *nd; |
cd3e2409 HP |
122 | DeviceState *dev; |
123 | SysBusDevice *sysbus; | |
48a18b3c | 124 | ISABus *isa_bus; |
64d7e9a4 | 125 | ISADevice *pit; |
fd8014e1 | 126 | DriveInfo *fds[MAX_FD]; |
73d74342 | 127 | qemu_irq esp_reset, dma_enable; |
4556bd8b | 128 | qemu_irq *cpu_exit_irq; |
60581b37 AK |
129 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
130 | MemoryRegion *bios = g_new(MemoryRegion, 1); | |
131 | MemoryRegion *bios2 = g_new(MemoryRegion, 1); | |
4ce7ff6e AJ |
132 | |
133 | /* init CPUs */ | |
134 | if (cpu_model == NULL) { | |
135 | #ifdef TARGET_MIPS64 | |
136 | cpu_model = "R4000"; | |
137 | #else | |
138 | /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */ | |
139 | cpu_model = "24Kf"; | |
140 | #endif | |
141 | } | |
142 | env = cpu_init(cpu_model); | |
143 | if (!env) { | |
144 | fprintf(stderr, "Unable to find CPU definition\n"); | |
145 | exit(1); | |
146 | } | |
a08d4367 | 147 | qemu_register_reset(main_cpu_reset, env); |
4ce7ff6e AJ |
148 | |
149 | /* allocate RAM */ | |
c5705a77 AK |
150 | memory_region_init_ram(ram, "mips_jazz.ram", ram_size); |
151 | vmstate_register_ram_global(ram); | |
60581b37 | 152 | memory_region_add_subregion(address_space, 0, ram); |
dcac9679 | 153 | |
c5705a77 AK |
154 | memory_region_init_ram(bios, "mips_jazz.bios", MAGNUM_BIOS_SIZE); |
155 | vmstate_register_ram_global(bios); | |
60581b37 AK |
156 | memory_region_set_readonly(bios, true); |
157 | memory_region_init_alias(bios2, "mips_jazz.bios", bios, | |
158 | 0, MAGNUM_BIOS_SIZE); | |
159 | memory_region_add_subregion(address_space, 0x1fc00000LL, bios); | |
160 | memory_region_add_subregion(address_space, 0xfff00000LL, bios2); | |
4ce7ff6e AJ |
161 | |
162 | /* load the BIOS image. */ | |
c6945b15 AJ |
163 | if (bios_name == NULL) |
164 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
165 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
166 | if (filename) { | |
167 | bios_size = load_image_targphys(filename, 0xfff00000LL, | |
168 | MAGNUM_BIOS_SIZE); | |
7267c094 | 169 | g_free(filename); |
5cea8590 PB |
170 | } else { |
171 | bios_size = -1; | |
172 | } | |
4ce7ff6e AJ |
173 | if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) { |
174 | fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n", | |
5cea8590 | 175 | bios_name); |
4ce7ff6e AJ |
176 | exit(1); |
177 | } | |
178 | ||
4ce7ff6e AJ |
179 | /* Init CPU internal devices */ |
180 | cpu_mips_irq_init_cpu(env); | |
181 | cpu_mips_clock_init(env); | |
182 | ||
183 | /* Chipset */ | |
3054434d AK |
184 | rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas, |
185 | address_space); | |
60581b37 AK |
186 | memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000); |
187 | memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); | |
4ce7ff6e AJ |
188 | |
189 | /* ISA devices */ | |
48a18b3c HP |
190 | isa_bus = isa_bus_new(NULL, address_space_io); |
191 | i8259 = i8259_init(isa_bus, env->irq[4]); | |
192 | isa_bus_irqs(isa_bus, i8259); | |
4556bd8b BS |
193 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
194 | DMA_init(0, cpu_exit_irq); | |
319ba9f5 | 195 | pit = pit_init(isa_bus, 0x40, 0, NULL); |
4ce7ff6e AJ |
196 | pcspk_init(pit); |
197 | ||
198 | /* ISA IO space at 0x90000000 */ | |
968d683c | 199 | isa_mmio_init(0x90000000, 0x01000000); |
4ce7ff6e AJ |
200 | isa_mem_base = 0x11000000; |
201 | ||
202 | /* Video card */ | |
203 | switch (jazz_model) { | |
204 | case JAZZ_MAGNUM: | |
97a3f6ff HP |
205 | dev = qdev_create(NULL, "sysbus-g364"); |
206 | qdev_init_nofail(dev); | |
207 | sysbus = sysbus_from_qdev(dev); | |
208 | sysbus_mmio_map(sysbus, 0, 0x60080000); | |
209 | sysbus_mmio_map(sysbus, 1, 0x40000000); | |
210 | sysbus_connect_irq(sysbus, 0, rc4030[3]); | |
211 | { | |
212 | /* Simple ROM, so user doesn't have to provide one */ | |
60581b37 | 213 | MemoryRegion *rom_mr = g_new(MemoryRegion, 1); |
c5705a77 AK |
214 | memory_region_init_ram(rom_mr, "g364fb.rom", 0x80000); |
215 | vmstate_register_ram_global(rom_mr); | |
60581b37 AK |
216 | memory_region_set_readonly(rom_mr, true); |
217 | uint8_t *rom = memory_region_get_ram_ptr(rom_mr); | |
218 | memory_region_add_subregion(address_space, 0x60000000, rom_mr); | |
97a3f6ff HP |
219 | rom[0] = 0x10; /* Mips G364 */ |
220 | } | |
4ce7ff6e | 221 | break; |
c171148c | 222 | case JAZZ_PICA61: |
be20f9e9 | 223 | isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); |
c171148c | 224 | break; |
4ce7ff6e AJ |
225 | default: |
226 | break; | |
227 | } | |
228 | ||
229 | /* Network controller */ | |
a65f56ee AJ |
230 | for (n = 0; n < nb_nics; n++) { |
231 | nd = &nd_table[n]; | |
232 | if (!nd->model) | |
7267c094 | 233 | nd->model = g_strdup("dp83932"); |
a65f56ee | 234 | if (strcmp(nd->model, "dp83932") == 0) { |
024e5bb6 | 235 | dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4], |
a65f56ee AJ |
236 | rc4030_opaque, rc4030_dma_memory_rw); |
237 | break; | |
238 | } else if (strcmp(nd->model, "?") == 0) { | |
239 | fprintf(stderr, "qemu: Supported NICs: dp83932\n"); | |
240 | exit(1); | |
241 | } else { | |
242 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); | |
243 | exit(1); | |
244 | } | |
245 | } | |
4ce7ff6e AJ |
246 | |
247 | /* SCSI adapter */ | |
cfb9de9c PB |
248 | esp_init(0x80002000, 0, |
249 | rc4030_dma_read, rc4030_dma_write, dmas[0], | |
73d74342 | 250 | rc4030[5], &esp_reset, &dma_enable); |
4ce7ff6e AJ |
251 | |
252 | /* Floppy */ | |
253 | if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) { | |
254 | fprintf(stderr, "qemu: too many floppy drives\n"); | |
255 | exit(1); | |
256 | } | |
257 | for (n = 0; n < MAX_FD; n++) { | |
fd8014e1 | 258 | fds[n] = drive_get(IF_FLOPPY, 0, n); |
4ce7ff6e | 259 | } |
2091ba23 | 260 | fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds); |
4ce7ff6e AJ |
261 | |
262 | /* Real time clock */ | |
48a18b3c | 263 | rtc_init(isa_bus, 1980, NULL); |
60581b37 AK |
264 | memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000); |
265 | memory_region_add_subregion(address_space, 0x80004000, rtc); | |
4ce7ff6e AJ |
266 | |
267 | /* Keyboard (i8042) */ | |
dbff76ac RH |
268 | i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1); |
269 | memory_region_add_subregion(address_space, 0x80005000, i8042); | |
4ce7ff6e AJ |
270 | |
271 | /* Serial ports */ | |
2d48377a | 272 | if (serial_hds[0]) { |
39186d8a RH |
273 | serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16, |
274 | serial_hds[0], DEVICE_NATIVE_ENDIAN); | |
2d48377a BS |
275 | } |
276 | if (serial_hds[1]) { | |
39186d8a RH |
277 | serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16, |
278 | serial_hds[1], DEVICE_NATIVE_ENDIAN); | |
2d48377a | 279 | } |
4ce7ff6e AJ |
280 | |
281 | /* Parallel port */ | |
282 | if (parallel_hds[0]) | |
63858cd9 AK |
283 | parallel_mm_init(address_space, 0x80008000, 0, rc4030[0], |
284 | parallel_hds[0]); | |
4ce7ff6e AJ |
285 | |
286 | /* Sound card */ | |
287 | /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ | |
4a0f031d | 288 | audio_init(isa_bus, NULL); |
4ce7ff6e | 289 | |
cd3e2409 HP |
290 | /* NVRAM */ |
291 | dev = qdev_create(NULL, "ds1225y"); | |
292 | qdev_init_nofail(dev); | |
293 | sysbus = sysbus_from_qdev(dev); | |
294 | sysbus_mmio_map(sysbus, 0, 0x80009000); | |
4ce7ff6e AJ |
295 | |
296 | /* LED indicator */ | |
c6017850 | 297 | jazz_led_init(address_space, 0x8000f000); |
4ce7ff6e AJ |
298 | } |
299 | ||
300 | static | |
c227f099 | 301 | void mips_magnum_init (ram_addr_t ram_size, |
3023f332 | 302 | const char *boot_device, |
4ce7ff6e AJ |
303 | const char *kernel_filename, const char *kernel_cmdline, |
304 | const char *initrd_filename, const char *cpu_model) | |
305 | { | |
c2d0d012 RH |
306 | mips_jazz_init(get_system_memory(), get_system_io(), |
307 | ram_size, cpu_model, JAZZ_MAGNUM); | |
4ce7ff6e AJ |
308 | } |
309 | ||
c171148c | 310 | static |
c227f099 | 311 | void mips_pica61_init (ram_addr_t ram_size, |
3023f332 | 312 | const char *boot_device, |
c171148c AJ |
313 | const char *kernel_filename, const char *kernel_cmdline, |
314 | const char *initrd_filename, const char *cpu_model) | |
315 | { | |
c2d0d012 RH |
316 | mips_jazz_init(get_system_memory(), get_system_io(), |
317 | ram_size, cpu_model, JAZZ_PICA61); | |
c171148c AJ |
318 | } |
319 | ||
f80f9ec9 | 320 | static QEMUMachine mips_magnum_machine = { |
eec2743e TS |
321 | .name = "magnum", |
322 | .desc = "MIPS Magnum", | |
323 | .init = mips_magnum_init, | |
c6945b15 | 324 | .use_scsi = 1, |
4ce7ff6e | 325 | }; |
c171148c | 326 | |
f80f9ec9 | 327 | static QEMUMachine mips_pica61_machine = { |
eec2743e TS |
328 | .name = "pica61", |
329 | .desc = "Acer Pica 61", | |
330 | .init = mips_pica61_init, | |
c6945b15 | 331 | .use_scsi = 1, |
c171148c | 332 | }; |
f80f9ec9 AL |
333 | |
334 | static void mips_jazz_machine_init(void) | |
335 | { | |
336 | qemu_register_machine(&mips_magnum_machine); | |
337 | qemu_register_machine(&mips_pica61_machine); | |
338 | } | |
339 | ||
340 | machine_init(mips_jazz_machine_init); |