]>
Commit | Line | Data |
---|---|---|
e16fe40c TS |
1 | /* |
2 | * QEMU/MIPS pseudo-board | |
3 | * | |
4 | * emulates a simple machine with ISA-like bus. | |
5 | * ISA IO space mapped to the 0x14000000 (PHYS) and | |
6 | * ISA memory at the 0x10000000 (PHYS, 16Mb in size). | |
7 | * All peripherial devices are attached to this "bus" with | |
8 | * the standard PC ISA addresses. | |
9 | */ | |
6af0bf9c FB |
10 | #include "vl.h" |
11 | ||
2909b29a | 12 | #ifdef TARGET_WORDS_BIGENDIAN |
6af0bf9c | 13 | #define BIOS_FILENAME "mips_bios.bin" |
f7bcd4e3 TS |
14 | #else |
15 | #define BIOS_FILENAME "mipsel_bios.bin" | |
16 | #endif | |
44cbbf18 | 17 | |
60aa19ab | 18 | #ifdef TARGET_MIPS64 |
74287114 | 19 | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL) |
5dc4b744 | 20 | #else |
74287114 | 21 | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU) |
5dc4b744 | 22 | #endif |
6af0bf9c | 23 | |
5dc4b744 | 24 | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
66a93e0f | 25 | |
58126404 PB |
26 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
27 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
28 | static const int ide_irq[2] = { 14, 15 }; | |
29 | ||
eddbd288 TS |
30 | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
31 | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
32 | ||
6af0bf9c FB |
33 | extern FILE *logfile; |
34 | ||
e16fe40c | 35 | static PITState *pit; /* PIT i8254 */ |
697584ab | 36 | |
e16fe40c | 37 | /*i8254 PIT is attached to the IRQ0 at PIC i8259 */ |
6af0bf9c | 38 | |
6ae81775 TS |
39 | static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, |
40 | uint32_t val) | |
41 | { | |
42 | if ((addr & 0xffff) == 0 && val == 42) | |
43 | qemu_system_reset_request (); | |
44 | else if ((addr & 0xffff) == 4 && val == 42) | |
45 | qemu_system_shutdown_request (); | |
46 | } | |
47 | ||
48 | static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) | |
49 | { | |
50 | return 0; | |
51 | } | |
52 | ||
53 | static CPUWriteMemoryFunc *mips_qemu_write[] = { | |
54 | &mips_qemu_writel, | |
55 | &mips_qemu_writel, | |
56 | &mips_qemu_writel, | |
57 | }; | |
58 | ||
59 | static CPUReadMemoryFunc *mips_qemu_read[] = { | |
60 | &mips_qemu_readl, | |
61 | &mips_qemu_readl, | |
62 | &mips_qemu_readl, | |
63 | }; | |
64 | ||
65 | static int mips_qemu_iomemtype = 0; | |
66 | ||
67 | void load_kernel (CPUState *env, int ram_size, const char *kernel_filename, | |
68 | const char *kernel_cmdline, | |
69 | const char *initrd_filename) | |
70 | { | |
74287114 | 71 | int64_t entry, kernel_low, kernel_high; |
6ae81775 | 72 | long kernel_size, initrd_size; |
74287114 | 73 | ram_addr_t initrd_offset; |
6ae81775 | 74 | |
74287114 TS |
75 | kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, |
76 | &entry, &kernel_low, &kernel_high); | |
c570fd16 TS |
77 | if (kernel_size >= 0) { |
78 | if ((entry & ~0x7fffffffULL) == 0x80000000) | |
5dc4b744 | 79 | entry = (int32_t)entry; |
6ae81775 | 80 | env->PC = entry; |
c570fd16 | 81 | } else { |
9042c0e2 TS |
82 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
83 | kernel_filename); | |
84 | exit(1); | |
6ae81775 TS |
85 | } |
86 | ||
87 | /* load initrd */ | |
88 | initrd_size = 0; | |
74287114 | 89 | initrd_offset = 0; |
6ae81775 | 90 | if (initrd_filename) { |
74287114 TS |
91 | initrd_size = get_image_size (initrd_filename); |
92 | if (initrd_size > 0) { | |
93 | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; | |
94 | if (initrd_offset + initrd_size > ram_size) { | |
95 | fprintf(stderr, | |
96 | "qemu: memory too small for initial ram disk '%s'\n", | |
97 | initrd_filename); | |
98 | exit(1); | |
99 | } | |
100 | initrd_size = load_image(initrd_filename, | |
101 | phys_ram_base + initrd_offset); | |
102 | } | |
6ae81775 TS |
103 | if (initrd_size == (target_ulong) -1) { |
104 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
105 | initrd_filename); | |
106 | exit(1); | |
107 | } | |
108 | } | |
109 | ||
110 | /* Store command line. */ | |
111 | if (initrd_size > 0) { | |
112 | int ret; | |
113 | ret = sprintf(phys_ram_base + (16 << 20) - 256, | |
3594c774 | 114 | "rd_start=0x" TARGET_FMT_lx " rd_size=%li ", |
74287114 | 115 | PHYS_TO_VIRT((uint32_t)initrd_offset), |
6ae81775 TS |
116 | initrd_size); |
117 | strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline); | |
118 | } | |
119 | else { | |
120 | strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); | |
121 | } | |
122 | ||
44cbbf18 TS |
123 | *(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); |
124 | *(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); | |
6ae81775 TS |
125 | } |
126 | ||
127 | static void main_cpu_reset(void *opaque) | |
128 | { | |
129 | CPUState *env = opaque; | |
130 | cpu_reset(env); | |
131 | ||
132 | if (env->kernel_filename) | |
133 | load_kernel (env, env->ram_size, env->kernel_filename, | |
134 | env->kernel_cmdline, env->initrd_filename); | |
135 | } | |
66a93e0f | 136 | |
70705261 | 137 | static |
6af0bf9c FB |
138 | void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, |
139 | DisplayState *ds, const char **fd_filename, int snapshot, | |
140 | const char *kernel_filename, const char *kernel_cmdline, | |
94fc95cd | 141 | const char *initrd_filename, const char *cpu_model) |
6af0bf9c FB |
142 | { |
143 | char buf[1024]; | |
6af0bf9c | 144 | unsigned long bios_offset; |
f7bcd4e3 | 145 | int bios_size; |
c68ea704 | 146 | CPUState *env; |
153a08db | 147 | RTCState *rtc_state; |
58126404 | 148 | int i; |
33d68b5f | 149 | mips_def_t *def; |
d537cf6c | 150 | qemu_irq *i8259; |
c68ea704 | 151 | |
33d68b5f TS |
152 | /* init CPUs */ |
153 | if (cpu_model == NULL) { | |
60aa19ab | 154 | #ifdef TARGET_MIPS64 |
33d68b5f TS |
155 | cpu_model = "R4000"; |
156 | #else | |
1c32f43e | 157 | cpu_model = "24Kf"; |
33d68b5f TS |
158 | #endif |
159 | } | |
160 | if (mips_find_by_name(cpu_model, &def) != 0) | |
161 | def = NULL; | |
c68ea704 | 162 | env = cpu_init(); |
33d68b5f | 163 | cpu_mips_register(env, def); |
c68ea704 | 164 | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
6ae81775 | 165 | qemu_register_reset(main_cpu_reset, env); |
c68ea704 | 166 | |
6af0bf9c FB |
167 | /* allocate RAM */ |
168 | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); | |
66a93e0f | 169 | |
6ae81775 TS |
170 | if (!mips_qemu_iomemtype) { |
171 | mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read, | |
33d68b5f | 172 | mips_qemu_write, NULL); |
6ae81775 TS |
173 | } |
174 | cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); | |
175 | ||
66a93e0f FB |
176 | /* Try to load a BIOS image. If this fails, we continue regardless, |
177 | but initialize the hardware ourselves. When a kernel gets | |
178 | preloaded we also initialize the hardware, since the BIOS wasn't | |
179 | run. */ | |
6af0bf9c FB |
180 | bios_offset = ram_size + vga_ram_size; |
181 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); | |
f7bcd4e3 | 182 | bios_size = load_image(buf, phys_ram_base + bios_offset); |
2909b29a | 183 | if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { |
44cbbf18 | 184 | cpu_register_physical_memory(0x1fc00000, |
66a93e0f | 185 | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
66a93e0f FB |
186 | } else { |
187 | /* not fatal */ | |
188 | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", | |
189 | buf); | |
6af0bf9c | 190 | } |
66a93e0f | 191 | |
66a93e0f | 192 | if (kernel_filename) { |
6ae81775 TS |
193 | load_kernel (env, ram_size, kernel_filename, kernel_cmdline, |
194 | initrd_filename); | |
195 | env->ram_size = ram_size; | |
196 | env->kernel_filename = kernel_filename; | |
197 | env->kernel_cmdline = kernel_cmdline; | |
198 | env->initrd_filename = initrd_filename; | |
6af0bf9c | 199 | } |
6af0bf9c | 200 | |
e16fe40c | 201 | /* Init CPU internal devices */ |
d537cf6c | 202 | cpu_mips_irq_init_cpu(env); |
c68ea704 | 203 | cpu_mips_clock_init(env); |
6af0bf9c FB |
204 | cpu_mips_irqctrl_init(); |
205 | ||
d537cf6c PB |
206 | /* The PIC is attached to the MIPS CPU INT0 pin */ |
207 | i8259 = i8259_init(env->irq[2]); | |
208 | ||
209 | rtc_state = rtc_init(0x70, i8259[8]); | |
afdfa781 | 210 | |
0699b548 | 211 | /* Register 64 KB of ISA IO space at 0x14000000 */ |
aef445bd | 212 | isa_mmio_init(0x14000000, 0x00010000); |
0699b548 FB |
213 | isa_mem_base = 0x10000000; |
214 | ||
d537cf6c | 215 | pit = pit_init(0x40, i8259[0]); |
afdfa781 | 216 | |
eddbd288 TS |
217 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
218 | if (serial_hds[i]) { | |
d537cf6c | 219 | serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]); |
eddbd288 TS |
220 | } |
221 | } | |
222 | ||
89b6b508 FB |
223 | isa_vga_init(ds, phys_ram_base + ram_size, ram_size, |
224 | vga_ram_size); | |
9827e95c | 225 | |
a41b2ff2 PB |
226 | if (nd_table[0].vlan) { |
227 | if (nd_table[0].model == NULL | |
228 | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { | |
d537cf6c | 229 | isa_ne2000_init(0x300, i8259[9], &nd_table[0]); |
a41b2ff2 PB |
230 | } else { |
231 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | |
232 | exit (1); | |
233 | } | |
234 | } | |
58126404 PB |
235 | |
236 | for(i = 0; i < 2; i++) | |
d537cf6c | 237 | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
58126404 | 238 | bs_table[2 * i], bs_table[2 * i + 1]); |
70705261 | 239 | |
d537cf6c | 240 | i8042_init(i8259[1], i8259[12], 0x60); |
9542611a | 241 | ds1225y_init(0x9000, "nvram"); |
6af0bf9c FB |
242 | } |
243 | ||
244 | QEMUMachine mips_machine = { | |
245 | "mips", | |
246 | "mips r4k platform", | |
247 | mips_r4k_init, | |
248 | }; |