[mirror_qemu.git] / hw / mipsnet.c

#include "hw.h"
#include "mips.h"
#include "net.h"
#include "isa.h"

//#define DEBUG_MIPSNET_SEND
//#define DEBUG_MIPSNET_RECEIVE
//#define DEBUG_MIPSNET_DATA
//#define DEBUG_MIPSNET_IRQ

/* MIPSnet register offsets */

#define MIPSNET_DEV_ID		0x00
# define MIPSNET_DEV_ID_STRING	"MIPSNET0"
#define MIPSNET_BUSY		0x08
#define MIPSNET_RX_DATA_COUNT	0x0c
#define MIPSNET_TX_DATA_COUNT	0x10
#define MIPSNET_INT_CTL		0x14
# define MIPSNET_INTCTL_TXDONE		0x00000001
# define MIPSNET_INTCTL_RXDONE		0x00000002
# define MIPSNET_INTCTL_TESTBIT		0x80000000
#define MIPSNET_INTERRUPT_INFO	0x18
#define MIPSNET_RX_DATA_BUFFER	0x1c
#define MIPSNET_TX_DATA_BUFFER	0x20

#define MAX_ETH_FRAME_SIZE	1514

typedef struct MIPSnetState {
    uint32_t busy;
    uint32_t rx_count;
    uint32_t rx_read;
    uint32_t tx_count;
    uint32_t tx_written;
    uint32_t intctl;
    uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
    uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
    qemu_irq irq;
    VLANClientState *vc;
    NICInfo *nd;
} MIPSnetState;

static void mipsnet_reset(MIPSnetState *s)
{
    s->busy = 1;
    s->rx_count = 0;
    s->rx_read = 0;
    s->tx_count = 0;
    s->tx_written = 0;
    s->intctl = 0;
    memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
    memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
}

static void mipsnet_update_irq(MIPSnetState *s)
{
    int isr = !!s->intctl;
#ifdef DEBUG_MIPSNET_IRQ
    printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
#endif
    qemu_set_irq(s->irq, isr);
}

static int mipsnet_buffer_full(MIPSnetState *s)
{
    if (s->rx_count >= MAX_ETH_FRAME_SIZE)
        return 1;
    return 0;
}

static int mipsnet_can_receive(void *opaque)
{
    MIPSnetState *s = opaque;

    if (s->busy)
        return 0;
    return !mipsnet_buffer_full(s);
}

static void mipsnet_receive(void *opaque, const uint8_t *buf, int size)
{
    MIPSnetState *s = opaque;

#ifdef DEBUG_MIPSNET_RECEIVE
    printf("mipsnet: receiving len=%d\n", size);
#endif
    if (!mipsnet_can_receive(opaque))
        return;

    s->busy = 1;

    /* Just accept everything. */

    /* Write packet data. */
    memcpy(s->rx_buffer, buf, size);

    s->rx_count = size;
    s->rx_read = 0;

    /* Now we can signal we have received something. */
    s->intctl |= MIPSNET_INTCTL_RXDONE;
    mipsnet_update_irq(s);
}

static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr)
{
    MIPSnetState *s = opaque;
    int ret = 0;
    const char *devid = MIPSNET_DEV_ID_STRING;

    addr &= 0x3f;
    switch (addr) {
    case MIPSNET_DEV_ID:
	ret = *((uint32_t *)&devid);
        break;
    case MIPSNET_DEV_ID + 4:
	ret = *((uint32_t *)(&devid + 4));
        break;
    case MIPSNET_BUSY:
	ret = s->busy;
        break;
    case MIPSNET_RX_DATA_COUNT:
	ret = s->rx_count;
        break;
    case MIPSNET_TX_DATA_COUNT:
	ret = s->tx_count;
        break;
    case MIPSNET_INT_CTL:
	ret = s->intctl;
        s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
        break;
    case MIPSNET_INTERRUPT_INFO:
        /* XXX: This seems to be a per-VPE interrupt number. */
	ret = 0;
        break;
    case MIPSNET_RX_DATA_BUFFER:
        if (s->rx_count) {
            s->rx_count--;
            ret = s->rx_buffer[s->rx_read++];
        }
        break;
    /* Reads as zero. */
    case MIPSNET_TX_DATA_BUFFER:
    default:
        break;
    }
#ifdef DEBUG_MIPSNET_DATA
    printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
    return ret;
}

static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    MIPSnetState *s = opaque;

    addr &= 0x3f;
#ifdef DEBUG_MIPSNET_DATA
    printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
    switch (addr) {
    case MIPSNET_TX_DATA_COUNT:
	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
        s->tx_written = 0;
        break;
    case MIPSNET_INT_CTL:
        if (val & MIPSNET_INTCTL_TXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_TXDONE;
        } else if (val & MIPSNET_INTCTL_RXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_RXDONE;
        } else if (val & MIPSNET_INTCTL_TESTBIT) {
            mipsnet_reset(s);
            s->intctl |= MIPSNET_INTCTL_TESTBIT;
        } else if (!val) {
            /* ACK testbit interrupt, flag was cleared on read. */
        }
        s->busy = !!s->intctl;
        mipsnet_update_irq(s);
        break;
    case MIPSNET_TX_DATA_BUFFER:
        s->tx_buffer[s->tx_written++] = val;
        if (s->tx_written == s->tx_count) {
            /* Send buffer. */
#ifdef DEBUG_MIPSNET_SEND
            printf("mipsnet: sending len=%d\n", s->tx_count);
#endif
            qemu_send_packet(s->vc, s->tx_buffer, s->tx_count);
            s->tx_count = s->tx_written = 0;
            s->intctl |= MIPSNET_INTCTL_TXDONE;
            s->busy = 1;
            mipsnet_update_irq(s);
        }
        break;
    /* Read-only registers */
    case MIPSNET_DEV_ID:
    case MIPSNET_BUSY:
    case MIPSNET_RX_DATA_COUNT:
    case MIPSNET_INTERRUPT_INFO:
    case MIPSNET_RX_DATA_BUFFER:
    default:
        break;
    }
}

static void mipsnet_save(QEMUFile *f, void *opaque)
{
    MIPSnetState *s = opaque;

    qemu_put_be32s(f, &s->busy);
    qemu_put_be32s(f, &s->rx_count);
    qemu_put_be32s(f, &s->rx_read);
    qemu_put_be32s(f, &s->tx_count);
    qemu_put_be32s(f, &s->tx_written);
    qemu_put_be32s(f, &s->intctl);
    qemu_put_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
    qemu_put_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
}

static int mipsnet_load(QEMUFile *f, void *opaque, int version_id)
{
    MIPSnetState *s = opaque;

    if (version_id > 0)
        return -EINVAL;

    qemu_get_be32s(f, &s->busy);
    qemu_get_be32s(f, &s->rx_count);
    qemu_get_be32s(f, &s->rx_read);
    qemu_get_be32s(f, &s->tx_count);
    qemu_get_be32s(f, &s->tx_written);
    qemu_get_be32s(f, &s->intctl);
    qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
    qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);

    return 0;
}

void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
{
    MIPSnetState *s;

    s = qemu_mallocz(sizeof(MIPSnetState));
    if (!s)
        return;

    register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
    register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
    register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
    register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
    register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
    register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);

    s->irq = irq;
    s->nd = nd;
    if (nd && nd->vlan) {
        s->vc = qemu_new_vlan_client(nd->vlan, mipsnet_receive,
                                     mipsnet_can_receive, s);
    } else {
        s->vc = NULL;
    }

    snprintf(s->vc->info_str, sizeof(s->vc->info_str),
             "mipsnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
              s->nd->macaddr[0],
              s->nd->macaddr[1],
              s->nd->macaddr[2],
              s->nd->macaddr[3],
              s->nd->macaddr[4],
              s->nd->macaddr[5]);

    mipsnet_reset(s);
    register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
}
Commit	Line	Data
87ecb68b PB	1	#include "hw.h"
	2	#include "mips.h"
	3	#include "net.h"
	4	#include "isa.h"
f0fc6f8f	5
57ba97de TS	6	//#define DEBUG_MIPSNET_SEND
57ba97de TS	7	//#define DEBUG_MIPSNET_RECEIVE
f0fc6f8f	8	//#define DEBUG_MIPSNET_DATA
57ba97de	9	//#define DEBUG_MIPSNET_IRQ
f0fc6f8f TS	10
	11	/* MIPSnet register offsets */
	12
	13	#define MIPSNET_DEV_ID 0x00
	14	# define MIPSNET_DEV_ID_STRING "MIPSNET0"
	15	#define MIPSNET_BUSY 0x08
	16	#define MIPSNET_RX_DATA_COUNT 0x0c
	17	#define MIPSNET_TX_DATA_COUNT 0x10
	18	#define MIPSNET_INT_CTL 0x14
	19	# define MIPSNET_INTCTL_TXDONE 0x00000001
	20	# define MIPSNET_INTCTL_RXDONE 0x00000002
	21	# define MIPSNET_INTCTL_TESTBIT 0x80000000
	22	#define MIPSNET_INTERRUPT_INFO 0x18
	23	#define MIPSNET_RX_DATA_BUFFER 0x1c
	24	#define MIPSNET_TX_DATA_BUFFER 0x20
	25
	26	#define MAX_ETH_FRAME_SIZE 1514
	27
	28	typedef struct MIPSnetState {
	29	uint32_t busy;
	30	uint32_t rx_count;
	31	uint32_t rx_read;
	32	uint32_t tx_count;
	33	uint32_t tx_written;
	34	uint32_t intctl;
	35	uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
	36	uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
	37	qemu_irq irq;
	38	VLANClientState *vc;
	39	NICInfo *nd;
	40	} MIPSnetState;
	41
	42	static void mipsnet_reset(MIPSnetState *s)
	43	{
	44	s->busy = 1;
	45	s->rx_count = 0;
	46	s->rx_read = 0;
	47	s->tx_count = 0;
	48	s->tx_written = 0;
	49	s->intctl = 0;
	50	memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
	51	memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
	52	}
	53
	54	static void mipsnet_update_irq(MIPSnetState *s)
	55	{
	56	int isr = !!s->intctl;
	57	#ifdef DEBUG_MIPSNET_IRQ
	58	printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
	59	#endif
	60	qemu_set_irq(s->irq, isr);
	61	}
	62
	63	static int mipsnet_buffer_full(MIPSnetState *s)
	64	{
	65	if (s->rx_count >= MAX_ETH_FRAME_SIZE)
	66	return 1;
	67	return 0;
	68	}
	69
	70	static int mipsnet_can_receive(void *opaque)
	71	{
	72	MIPSnetState *s = opaque;
	73
74	if (s->busy)
75	return 0;
76	return !mipsnet_buffer_full(s);
77	}
78
79	static void mipsnet_receive(void opaque, const uint8_t buf, int size)
80	{
81	MIPSnetState *s = opaque;
82
83	#ifdef DEBUG_MIPSNET_RECEIVE
84	printf("mipsnet: receiving len=%d\n", size);
85	#endif
86	if (!mipsnet_can_receive(opaque))
87	return;
88
89	s->busy = 1;
90
91	/* Just accept everything. */
92
93	/* Write packet data. */
94	memcpy(s->rx_buffer, buf, size);
95
96	s->rx_count = size;
97	s->rx_read = 0;
98
99	/* Now we can signal we have received something. */
100	s->intctl \|= MIPSNET_INTCTL_RXDONE;
101	mipsnet_update_irq(s);
102	}
103
104	static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr)
105	{
106	MIPSnetState *s = opaque;
107	int ret = 0;
108	const char *devid = MIPSNET_DEV_ID_STRING;
109
110	addr &= 0x3f;
111	switch (addr) {
112	case MIPSNET_DEV_ID:
113	ret = ((uint32_t )&devid);
114	break;
115	case MIPSNET_DEV_ID + 4:
116	ret = ((uint32_t )(&devid + 4));
117	break;
118	case MIPSNET_BUSY:
119	ret = s->busy;
120	break;
121	case MIPSNET_RX_DATA_COUNT:
122	ret = s->rx_count;
123	break;
124	case MIPSNET_TX_DATA_COUNT:
125	ret = s->tx_count;
126	break;
127	case MIPSNET_INT_CTL:
128	ret = s->intctl;
129	s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
130	break;
131	case MIPSNET_INTERRUPT_INFO:
132	/* XXX: This seems to be a per-VPE interrupt number. */
133	ret = 0;
134	break;
135	case MIPSNET_RX_DATA_BUFFER:
136	if (s->rx_count) {
137	s->rx_count--;
138	ret = s->rx_buffer[s->rx_read++];
139	}
140	break;
141	/* Reads as zero. */
142	case MIPSNET_TX_DATA_BUFFER:
143	default:
144	break;
145	}
146	#ifdef DEBUG_MIPSNET_DATA
147	printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
148	#endif
149	return ret;
150	}
151
152	static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val)
153	{
154	MIPSnetState *s = opaque;
155
156	addr &= 0x3f;
157	#ifdef DEBUG_MIPSNET_DATA
158	printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
159	#endif
160	switch (addr) {
161	case MIPSNET_TX_DATA_COUNT:
162	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
163	s->tx_written = 0;
164	break;
165	case MIPSNET_INT_CTL:
166	if (val & MIPSNET_INTCTL_TXDONE) {
167	s->intctl &= ~MIPSNET_INTCTL_TXDONE;
168	} else if (val & MIPSNET_INTCTL_RXDONE) {
169	s->intctl &= ~MIPSNET_INTCTL_RXDONE;
170	} else if (val & MIPSNET_INTCTL_TESTBIT) {
171	mipsnet_reset(s);
172	s->intctl \|= MIPSNET_INTCTL_TESTBIT;
173	} else if (!val) {
174	/* ACK testbit interrupt, flag was cleared on read. */
175	}
176	s->busy = !!s->intctl;
177	mipsnet_update_irq(s);
178	break;
179	case MIPSNET_TX_DATA_BUFFER:
180	s->tx_buffer[s->tx_written++] = val;
181	if (s->tx_written == s->tx_count) {
182	/* Send buffer. */
183	#ifdef DEBUG_MIPSNET_SEND
184	printf("mipsnet: sending len=%d\n", s->tx_count);
185	#endif
186	qemu_send_packet(s->vc, s->tx_buffer, s->tx_count);
187	s->tx_count = s->tx_written = 0;
188	s->intctl \|= MIPSNET_INTCTL_TXDONE;
189	s->busy = 1;
190	mipsnet_update_irq(s);
191	}
192	break;
193	/* Read-only registers */
194	case MIPSNET_DEV_ID:
195	case MIPSNET_BUSY:
196	case MIPSNET_RX_DATA_COUNT:
197	case MIPSNET_INTERRUPT_INFO:
198	case MIPSNET_RX_DATA_BUFFER:
199	default:
200	break;
201	}
202	}
203
204	static void mipsnet_save(QEMUFile f, void opaque)
205	{
206	MIPSnetState *s = opaque;
207
208	qemu_put_be32s(f, &s->busy);
209	qemu_put_be32s(f, &s->rx_count);
210	qemu_put_be32s(f, &s->rx_read);
211	qemu_put_be32s(f, &s->tx_count);
212	qemu_put_be32s(f, &s->tx_written);
213	qemu_put_be32s(f, &s->intctl);
214	qemu_put_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
215	qemu_put_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
216	}
217
218	static int mipsnet_load(QEMUFile f, void opaque, int version_id)
219	{
220	MIPSnetState *s = opaque;
221
222	if (version_id > 0)
223	return -EINVAL;
224
225	qemu_get_be32s(f, &s->busy);
226	qemu_get_be32s(f, &s->rx_count);
227	qemu_get_be32s(f, &s->rx_read);
228	qemu_get_be32s(f, &s->tx_count);
229	qemu_get_be32s(f, &s->tx_written);
230	qemu_get_be32s(f, &s->intctl);
231	qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
232	qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
233
234	return 0;
235	}
236
237	void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
238	{
239	MIPSnetState *s;
240
241	s = qemu_mallocz(sizeof(MIPSnetState));
242	if (!s)
243	return;
244
245	register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
246	register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
247	register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
248	register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
249	register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
250	register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
251
252	s->irq = irq;
253	s->nd = nd;
254	if (nd && nd->vlan) {
255	s->vc = qemu_new_vlan_client(nd->vlan, mipsnet_receive,
256	mipsnet_can_receive, s);
257	} else {
258	s->vc = NULL;
259	}
260
261	snprintf(s->vc->info_str, sizeof(s->vc->info_str),
262	"mipsnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
263	s->nd->macaddr[0],
264	s->nd->macaddr[1],
265	s->nd->macaddr[2],
266	s->nd->macaddr[3],
267	s->nd->macaddr[4],
268	s->nd->macaddr[5]);
269
270	mipsnet_reset(s);
271	register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
272	}