[mirror_qemu.git] / hw / mipsnet.c

#include "hw.h"
#include "net.h"
#include "sysbus.h"

//#define DEBUG_MIPSNET_SEND
//#define DEBUG_MIPSNET_RECEIVE
//#define DEBUG_MIPSNET_DATA
//#define DEBUG_MIPSNET_IRQ

/* MIPSnet register offsets */

#define MIPSNET_DEV_ID		0x00
#define MIPSNET_BUSY		0x08
#define MIPSNET_RX_DATA_COUNT	0x0c
#define MIPSNET_TX_DATA_COUNT	0x10
#define MIPSNET_INT_CTL		0x14
# define MIPSNET_INTCTL_TXDONE		0x00000001
# define MIPSNET_INTCTL_RXDONE		0x00000002
# define MIPSNET_INTCTL_TESTBIT		0x80000000
#define MIPSNET_INTERRUPT_INFO	0x18
#define MIPSNET_RX_DATA_BUFFER	0x1c
#define MIPSNET_TX_DATA_BUFFER	0x20

#define MAX_ETH_FRAME_SIZE	1514

typedef struct MIPSnetState {
    SysBusDevice busdev;

    uint32_t busy;
    uint32_t rx_count;
    uint32_t rx_read;
    uint32_t tx_count;
    uint32_t tx_written;
    uint32_t intctl;
    uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
    uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
    MemoryRegion io;
    qemu_irq irq;
    NICState *nic;
    NICConf conf;
} MIPSnetState;

static void mipsnet_reset(MIPSnetState *s)
{
    s->busy = 1;
    s->rx_count = 0;
    s->rx_read = 0;
    s->tx_count = 0;
    s->tx_written = 0;
    s->intctl = 0;
    memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
    memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
}

static void mipsnet_update_irq(MIPSnetState *s)
{
    int isr = !!s->intctl;
#ifdef DEBUG_MIPSNET_IRQ
    printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
#endif
    qemu_set_irq(s->irq, isr);
}

static int mipsnet_buffer_full(MIPSnetState *s)
{
    if (s->rx_count >= MAX_ETH_FRAME_SIZE)
        return 1;
    return 0;
}

static int mipsnet_can_receive(VLANClientState *nc)
{
    MIPSnetState *s = DO_UPCAST(NICState, nc, nc)->opaque;

    if (s->busy)
        return 0;
    return !mipsnet_buffer_full(s);
}

static ssize_t mipsnet_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
{
    MIPSnetState *s = DO_UPCAST(NICState, nc, nc)->opaque;

#ifdef DEBUG_MIPSNET_RECEIVE
    printf("mipsnet: receiving len=%zu\n", size);
#endif
    if (!mipsnet_can_receive(nc))
        return -1;

    s->busy = 1;

    /* Just accept everything. */

    /* Write packet data. */
    memcpy(s->rx_buffer, buf, size);

    s->rx_count = size;
    s->rx_read = 0;

    /* Now we can signal we have received something. */
    s->intctl |= MIPSNET_INTCTL_RXDONE;
    mipsnet_update_irq(s);

    return size;
}

static uint64_t mipsnet_ioport_read(void *opaque, target_phys_addr_t addr,
                                    unsigned int size)
{
    MIPSnetState *s = opaque;
    int ret = 0;

    addr &= 0x3f;
    switch (addr) {
    case MIPSNET_DEV_ID:
	ret = be32_to_cpu(0x4d495053);		/* MIPS */
        break;
    case MIPSNET_DEV_ID + 4:
	ret = be32_to_cpu(0x4e455430);		/* NET0 */
        break;
    case MIPSNET_BUSY:
	ret = s->busy;
        break;
    case MIPSNET_RX_DATA_COUNT:
	ret = s->rx_count;
        break;
    case MIPSNET_TX_DATA_COUNT:
	ret = s->tx_count;
        break;
    case MIPSNET_INT_CTL:
	ret = s->intctl;
        s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
        break;
    case MIPSNET_INTERRUPT_INFO:
        /* XXX: This seems to be a per-VPE interrupt number. */
	ret = 0;
        break;
    case MIPSNET_RX_DATA_BUFFER:
        if (s->rx_count) {
            s->rx_count--;
            ret = s->rx_buffer[s->rx_read++];
        }
        break;
    /* Reads as zero. */
    case MIPSNET_TX_DATA_BUFFER:
    default:
        break;
    }
#ifdef DEBUG_MIPSNET_DATA
    printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
    return ret;
}

static void mipsnet_ioport_write(void *opaque, target_phys_addr_t addr,
                                 uint64_t val, unsigned int size)
{
    MIPSnetState *s = opaque;

    addr &= 0x3f;
#ifdef DEBUG_MIPSNET_DATA
    printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
    switch (addr) {
    case MIPSNET_TX_DATA_COUNT:
	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
        s->tx_written = 0;
        break;
    case MIPSNET_INT_CTL:
        if (val & MIPSNET_INTCTL_TXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_TXDONE;
        } else if (val & MIPSNET_INTCTL_RXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_RXDONE;
        } else if (val & MIPSNET_INTCTL_TESTBIT) {
            mipsnet_reset(s);
            s->intctl |= MIPSNET_INTCTL_TESTBIT;
        } else if (!val) {
            /* ACK testbit interrupt, flag was cleared on read. */
        }
        s->busy = !!s->intctl;
        mipsnet_update_irq(s);
        break;
    case MIPSNET_TX_DATA_BUFFER:
        s->tx_buffer[s->tx_written++] = val;
        if (s->tx_written == s->tx_count) {
            /* Send buffer. */
#ifdef DEBUG_MIPSNET_SEND
            printf("mipsnet: sending len=%d\n", s->tx_count);
#endif
            qemu_send_packet(&s->nic->nc, s->tx_buffer, s->tx_count);
            s->tx_count = s->tx_written = 0;
            s->intctl |= MIPSNET_INTCTL_TXDONE;
            s->busy = 1;
            mipsnet_update_irq(s);
        }
        break;
    /* Read-only registers */
    case MIPSNET_DEV_ID:
    case MIPSNET_BUSY:
    case MIPSNET_RX_DATA_COUNT:
    case MIPSNET_INTERRUPT_INFO:
    case MIPSNET_RX_DATA_BUFFER:
    default:
        break;
    }
}

static const VMStateDescription vmstate_mipsnet = {
    .name = "mipsnet",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(busy, MIPSnetState),
        VMSTATE_UINT32(rx_count, MIPSnetState),
        VMSTATE_UINT32(rx_read, MIPSnetState),
        VMSTATE_UINT32(tx_count, MIPSnetState),
        VMSTATE_UINT32(tx_written, MIPSnetState),
        VMSTATE_UINT32(intctl, MIPSnetState),
        VMSTATE_BUFFER(rx_buffer, MIPSnetState),
        VMSTATE_BUFFER(tx_buffer, MIPSnetState),
        VMSTATE_END_OF_LIST()
    }
};

static void mipsnet_cleanup(VLANClientState *nc)
{
    MIPSnetState *s = DO_UPCAST(NICState, nc, nc)->opaque;

    s->nic = NULL;
}

static NetClientInfo net_mipsnet_info = {
    .type = NET_CLIENT_TYPE_NIC,
    .size = sizeof(NICState),
    .can_receive = mipsnet_can_receive,
    .receive = mipsnet_receive,
    .cleanup = mipsnet_cleanup,
};

static MemoryRegionOps mipsnet_ioport_ops = {
    .read = mipsnet_ioport_read,
    .write = mipsnet_ioport_write,
    .impl.min_access_size = 1,
    .impl.max_access_size = 4,
};

static int mipsnet_sysbus_init(SysBusDevice *dev)
{
    MIPSnetState *s = DO_UPCAST(MIPSnetState, busdev, dev);

    memory_region_init_io(&s->io, &mipsnet_ioport_ops, s, "mipsnet-io", 36);
    sysbus_init_mmio_region(dev, &s->io);
    sysbus_init_irq(dev, &s->irq);

    s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
                          dev->qdev.info->name, dev->qdev.id, s);
    qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);

    return 0;
}

static void mipsnet_sysbus_reset(DeviceState *dev)
{
    MIPSnetState *s = DO_UPCAST(MIPSnetState, busdev.qdev, dev);
    mipsnet_reset(s);
}

static SysBusDeviceInfo mipsnet_info = {
    .init = mipsnet_sysbus_init,
    .qdev.name = "mipsnet",
    .qdev.desc = "MIPS Simulator network device",
    .qdev.size = sizeof(MIPSnetState),
    .qdev.vmsd = &vmstate_mipsnet,
    .qdev.reset = mipsnet_sysbus_reset,
    .qdev.props = (Property[]) {
        DEFINE_NIC_PROPERTIES(MIPSnetState, conf),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void mipsnet_register_devices(void)
{
    sysbus_register_withprop(&mipsnet_info);
}

device_init(mipsnet_register_devices)
Commit	Line	Data
87ecb68b	1	#include "hw.h"
87ecb68b	2	#include "net.h"
d118d64a	3	#include "sysbus.h"
f0fc6f8f	4
57ba97de TS	5	//#define DEBUG_MIPSNET_SEND
57ba97de TS	6	//#define DEBUG_MIPSNET_RECEIVE
f0fc6f8f	7	//#define DEBUG_MIPSNET_DATA
57ba97de	8	//#define DEBUG_MIPSNET_IRQ
f0fc6f8f TS	9
	10	/* MIPSnet register offsets */
	11
	12	#define MIPSNET_DEV_ID 0x00
f0fc6f8f TS	13	#define MIPSNET_BUSY 0x08
	14	#define MIPSNET_RX_DATA_COUNT 0x0c
	15	#define MIPSNET_TX_DATA_COUNT 0x10
	16	#define MIPSNET_INT_CTL 0x14
	17	# define MIPSNET_INTCTL_TXDONE 0x00000001
	18	# define MIPSNET_INTCTL_RXDONE 0x00000002
	19	# define MIPSNET_INTCTL_TESTBIT 0x80000000
	20	#define MIPSNET_INTERRUPT_INFO 0x18
	21	#define MIPSNET_RX_DATA_BUFFER 0x1c
	22	#define MIPSNET_TX_DATA_BUFFER 0x20
	23
	24	#define MAX_ETH_FRAME_SIZE 1514
	25
	26	typedef struct MIPSnetState {
d118d64a HP	27	SysBusDevice busdev;
d118d64a HP	28
f0fc6f8f TS	29	uint32_t busy;
	30	uint32_t rx_count;
	31	uint32_t rx_read;
	32	uint32_t tx_count;
	33	uint32_t tx_written;
	34	uint32_t intctl;
	35	uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
	36	uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
d118d64a	37	MemoryRegion io;
f0fc6f8f	38	qemu_irq irq;
1f30d10a MM	39	NICState *nic;
1f30d10a MM	40	NICConf conf;
f0fc6f8f TS	41	} MIPSnetState;
	42
	43	static void mipsnet_reset(MIPSnetState *s)
	44	{
	45	s->busy = 1;
	46	s->rx_count = 0;
	47	s->rx_read = 0;
	48	s->tx_count = 0;
	49	s->tx_written = 0;
	50	s->intctl = 0;
	51	memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
	52	memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
	53	}
	54
	55	static void mipsnet_update_irq(MIPSnetState *s)
	56	{
	57	int isr = !!s->intctl;
	58	#ifdef DEBUG_MIPSNET_IRQ
	59	printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
	60	#endif
	61	qemu_set_irq(s->irq, isr);
	62	}
	63
	64	static int mipsnet_buffer_full(MIPSnetState *s)
	65	{
	66	if (s->rx_count >= MAX_ETH_FRAME_SIZE)
	67	return 1;
	68	return 0;
	69	}
	70
1f30d10a	71	static int mipsnet_can_receive(VLANClientState *nc)
f0fc6f8f	72	{
1f30d10a	73	MIPSnetState *s = DO_UPCAST(NICState, nc, nc)->opaque;
f0fc6f8f TS	74
	75	if (s->busy)
	76	return 0;
	77	return !mipsnet_buffer_full(s);
	78	}
	79
1f30d10a	80	static ssize_t mipsnet_receive(VLANClientState nc, const uint8_t buf, size_t size)
f0fc6f8f	81	{
1f30d10a	82	MIPSnetState *s = DO_UPCAST(NICState, nc, nc)->opaque;
f0fc6f8f TS	83
f0fc6f8f TS	84	#ifdef DEBUG_MIPSNET_RECEIVE
a4a77677	85	printf("mipsnet: receiving len=%zu\n", size);
f0fc6f8f	86	#endif
1f30d10a	87	if (!mipsnet_can_receive(nc))
4f1c942b	88	return -1;
f0fc6f8f TS	89
	90	s->busy = 1;
	91
	92	/* Just accept everything. */
	93
	94	/* Write packet data. */
	95	memcpy(s->rx_buffer, buf, size);
	96
	97	s->rx_count = size;
	98	s->rx_read = 0;
	99
	100	/* Now we can signal we have received something. */
	101	s->intctl \|= MIPSNET_INTCTL_RXDONE;
	102	mipsnet_update_irq(s);
4f1c942b MM	103
4f1c942b MM	104	return size;
f0fc6f8f TS	105	}
f0fc6f8f TS	106
d118d64a HP	107	static uint64_t mipsnet_ioport_read(void *opaque, target_phys_addr_t addr,
d118d64a HP	108	unsigned int size)
f0fc6f8f TS	109	{
	110	MIPSnetState *s = opaque;
	111	int ret = 0;
f0fc6f8f TS	112
	113	addr &= 0x3f;
	114	switch (addr) {
	115	case MIPSNET_DEV_ID:
9b595395	116	ret = be32_to_cpu(0x4d495053); /* MIPS */
f0fc6f8f TS	117	break;
f0fc6f8f TS	118	case MIPSNET_DEV_ID + 4:
9b595395	119	ret = be32_to_cpu(0x4e455430); /* NET0 */
f0fc6f8f TS	120	break;
	121	case MIPSNET_BUSY:
	122	ret = s->busy;
	123	break;
	124	case MIPSNET_RX_DATA_COUNT:
	125	ret = s->rx_count;
	126	break;
	127	case MIPSNET_TX_DATA_COUNT:
	128	ret = s->tx_count;
	129	break;
	130	case MIPSNET_INT_CTL:
	131	ret = s->intctl;
	132	s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
	133	break;
	134	case MIPSNET_INTERRUPT_INFO:
	135	/* XXX: This seems to be a per-VPE interrupt number. */
	136	ret = 0;
	137	break;
	138	case MIPSNET_RX_DATA_BUFFER:
	139	if (s->rx_count) {
	140	s->rx_count--;
	141	ret = s->rx_buffer[s->rx_read++];
	142	}
	143	break;
	144	/* Reads as zero. */
	145	case MIPSNET_TX_DATA_BUFFER:
	146	default:
	147	break;
	148	}
	149	#ifdef DEBUG_MIPSNET_DATA
	150	printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
	151	#endif
	152	return ret;
	153	}
	154
d118d64a HP	155	static void mipsnet_ioport_write(void *opaque, target_phys_addr_t addr,
d118d64a HP	156	uint64_t val, unsigned int size)
f0fc6f8f TS	157	{
	158	MIPSnetState *s = opaque;
	159
	160	addr &= 0x3f;
	161	#ifdef DEBUG_MIPSNET_DATA
	162	printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
	163	#endif
	164	switch (addr) {
	165	case MIPSNET_TX_DATA_COUNT:
	166	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
	167	s->tx_written = 0;
	168	break;
	169	case MIPSNET_INT_CTL:
	170	if (val & MIPSNET_INTCTL_TXDONE) {
	171	s->intctl &= ~MIPSNET_INTCTL_TXDONE;
	172	} else if (val & MIPSNET_INTCTL_RXDONE) {
	173	s->intctl &= ~MIPSNET_INTCTL_RXDONE;
	174	} else if (val & MIPSNET_INTCTL_TESTBIT) {
	175	mipsnet_reset(s);
	176	s->intctl \|= MIPSNET_INTCTL_TESTBIT;
	177	} else if (!val) {
	178	/* ACK testbit interrupt, flag was cleared on read. */
	179	}
	180	s->busy = !!s->intctl;
	181	mipsnet_update_irq(s);
	182	break;
	183	case MIPSNET_TX_DATA_BUFFER:
	184	s->tx_buffer[s->tx_written++] = val;
	185	if (s->tx_written == s->tx_count) {
	186	/* Send buffer. */
	187	#ifdef DEBUG_MIPSNET_SEND
	188	printf("mipsnet: sending len=%d\n", s->tx_count);
	189	#endif
1f30d10a	190	qemu_send_packet(&s->nic->nc, s->tx_buffer, s->tx_count);
f0fc6f8f TS	191	s->tx_count = s->tx_written = 0;
	192	s->intctl \|= MIPSNET_INTCTL_TXDONE;
	193	s->busy = 1;
	194	mipsnet_update_irq(s);
	195	}
	196	break;
	197	/* Read-only registers */
	198	case MIPSNET_DEV_ID:
	199	case MIPSNET_BUSY:
	200	case MIPSNET_RX_DATA_COUNT:
	201	case MIPSNET_INTERRUPT_INFO:
	202	case MIPSNET_RX_DATA_BUFFER:
	203	default:
	204	break;
	205	}
	206	}
	207
c7298ab2 JQ	208	static const VMStateDescription vmstate_mipsnet = {
	209	.name = "mipsnet",
	210	.version_id = 0,
	211	.minimum_version_id = 0,
	212	.minimum_version_id_old = 0,
	213	.fields = (VMStateField[]) {
	214	VMSTATE_UINT32(busy, MIPSnetState),
	215	VMSTATE_UINT32(rx_count, MIPSnetState),
	216	VMSTATE_UINT32(rx_read, MIPSnetState),
	217	VMSTATE_UINT32(tx_count, MIPSnetState),
	218	VMSTATE_UINT32(tx_written, MIPSnetState),
	219	VMSTATE_UINT32(intctl, MIPSnetState),
	220	VMSTATE_BUFFER(rx_buffer, MIPSnetState),
	221	VMSTATE_BUFFER(tx_buffer, MIPSnetState),
	222	VMSTATE_END_OF_LIST()
	223	}
	224	};
f0fc6f8f	225
1f30d10a	226	static void mipsnet_cleanup(VLANClientState *nc)
b946a153	227	{
1f30d10a	228	MIPSnetState *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153	229
d118d64a	230	s->nic = NULL;
b946a153 AL	231	}
b946a153 AL	232
1f30d10a MM	233	static NetClientInfo net_mipsnet_info = {
	234	.type = NET_CLIENT_TYPE_NIC,
	235	.size = sizeof(NICState),
	236	.can_receive = mipsnet_can_receive,
	237	.receive = mipsnet_receive,
	238	.cleanup = mipsnet_cleanup,
	239	};
	240
d118d64a HP	241	static MemoryRegionOps mipsnet_ioport_ops = {
	242	.read = mipsnet_ioport_read,
	243	.write = mipsnet_ioport_write,
	244	.impl.min_access_size = 1,
	245	.impl.max_access_size = 4,
	246	};
0ae18cee	247
d118d64a HP	248	static int mipsnet_sysbus_init(SysBusDevice *dev)
	249	{
	250	MIPSnetState *s = DO_UPCAST(MIPSnetState, busdev, dev);
f0fc6f8f	251
d118d64a HP	252	memory_region_init_io(&s->io, &mipsnet_ioport_ops, s, "mipsnet-io", 36);
	253	sysbus_init_mmio_region(dev, &s->io);
	254	sysbus_init_irq(dev, &s->irq);
f0fc6f8f	255
d118d64a HP	256	s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
	257	dev->qdev.info->name, dev->qdev.id, s);
	258	qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1f30d10a	259
d118d64a HP	260	return 0;
d118d64a HP	261	}
f0fc6f8f	262
d118d64a HP	263	static void mipsnet_sysbus_reset(DeviceState *dev)
	264	{
	265	MIPSnetState *s = DO_UPCAST(MIPSnetState, busdev.qdev, dev);
	266	mipsnet_reset(s);
	267	}
1f30d10a	268
d118d64a HP	269	static SysBusDeviceInfo mipsnet_info = {
	270	.init = mipsnet_sysbus_init,
	271	.qdev.name = "mipsnet",
	272	.qdev.desc = "MIPS Simulator network device",
	273	.qdev.size = sizeof(MIPSnetState),
	274	.qdev.vmsd = &vmstate_mipsnet,
	275	.qdev.reset = mipsnet_sysbus_reset,
	276	.qdev.props = (Property[]) {
	277	DEFINE_NIC_PROPERTIES(MIPSnetState, conf),
	278	DEFINE_PROP_END_OF_LIST(),
1f30d10a	279	}
d118d64a	280	};
f0fc6f8f	281
d118d64a HP	282	static void mipsnet_register_devices(void)
	283	{
	284	sysbus_register_withprop(&mipsnet_info);
f0fc6f8f	285	}
d118d64a HP	286
d118d64a HP	287	device_init(mipsnet_register_devices)