[mirror_qemu.git] / hw / misc / aspeed_scu.c

/*
 * ASPEED System Control Unit
 *
 * Andrew Jeffery <andrew@aj.id.au>
 *
 * Copyright 2016 IBM Corp.
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "hw/misc/aspeed_scu.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "qemu/bitops.h"
#include "qemu/log.h"
#include "qemu/guest-random.h"
#include "qemu/module.h"
#include "trace.h"

#define TO_REG(offset) ((offset) >> 2)

#define PROT_KEY             TO_REG(0x00)
#define SYS_RST_CTRL         TO_REG(0x04)
#define CLK_SEL              TO_REG(0x08)
#define CLK_STOP_CTRL        TO_REG(0x0C)
#define FREQ_CNTR_CTRL       TO_REG(0x10)
#define FREQ_CNTR_EVAL       TO_REG(0x14)
#define IRQ_CTRL             TO_REG(0x18)
#define D2PLL_PARAM          TO_REG(0x1C)
#define MPLL_PARAM           TO_REG(0x20)
#define HPLL_PARAM           TO_REG(0x24)
#define FREQ_CNTR_RANGE      TO_REG(0x28)
#define MISC_CTRL1           TO_REG(0x2C)
#define PCI_CTRL1            TO_REG(0x30)
#define PCI_CTRL2            TO_REG(0x34)
#define PCI_CTRL3            TO_REG(0x38)
#define SYS_RST_STATUS       TO_REG(0x3C)
#define SOC_SCRATCH1         TO_REG(0x40)
#define SOC_SCRATCH2         TO_REG(0x44)
#define MAC_CLK_DELAY        TO_REG(0x48)
#define MISC_CTRL2           TO_REG(0x4C)
#define VGA_SCRATCH1         TO_REG(0x50)
#define VGA_SCRATCH2         TO_REG(0x54)
#define VGA_SCRATCH3         TO_REG(0x58)
#define VGA_SCRATCH4         TO_REG(0x5C)
#define VGA_SCRATCH5         TO_REG(0x60)
#define VGA_SCRATCH6         TO_REG(0x64)
#define VGA_SCRATCH7         TO_REG(0x68)
#define VGA_SCRATCH8         TO_REG(0x6C)
#define HW_STRAP1            TO_REG(0x70)
#define RNG_CTRL             TO_REG(0x74)
#define RNG_DATA             TO_REG(0x78)
#define SILICON_REV          TO_REG(0x7C)
#define PINMUX_CTRL1         TO_REG(0x80)
#define PINMUX_CTRL2         TO_REG(0x84)
#define PINMUX_CTRL3         TO_REG(0x88)
#define PINMUX_CTRL4         TO_REG(0x8C)
#define PINMUX_CTRL5         TO_REG(0x90)
#define PINMUX_CTRL6         TO_REG(0x94)
#define WDT_RST_CTRL         TO_REG(0x9C)
#define PINMUX_CTRL7         TO_REG(0xA0)
#define PINMUX_CTRL8         TO_REG(0xA4)
#define PINMUX_CTRL9         TO_REG(0xA8)
#define WAKEUP_EN            TO_REG(0xC0)
#define WAKEUP_CTRL          TO_REG(0xC4)
#define HW_STRAP2            TO_REG(0xD0)
#define FREE_CNTR4           TO_REG(0xE0)
#define FREE_CNTR4_EXT       TO_REG(0xE4)
#define CPU2_CTRL            TO_REG(0x100)
#define CPU2_BASE_SEG1       TO_REG(0x104)
#define CPU2_BASE_SEG2       TO_REG(0x108)
#define CPU2_BASE_SEG3       TO_REG(0x10C)
#define CPU2_BASE_SEG4       TO_REG(0x110)
#define CPU2_BASE_SEG5       TO_REG(0x114)
#define CPU2_CACHE_CTRL      TO_REG(0x118)
#define UART_HPLL_CLK        TO_REG(0x160)
#define PCIE_CTRL            TO_REG(0x180)
#define BMC_MMIO_CTRL        TO_REG(0x184)
#define RELOC_DECODE_BASE1   TO_REG(0x188)
#define RELOC_DECODE_BASE2   TO_REG(0x18C)
#define MAILBOX_DECODE_BASE  TO_REG(0x190)
#define SRAM_DECODE_BASE1    TO_REG(0x194)
#define SRAM_DECODE_BASE2    TO_REG(0x198)
#define BMC_REV              TO_REG(0x19C)
#define BMC_DEV_ID           TO_REG(0x1A4)

#define SCU_IO_REGION_SIZE 0x1000

static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
     [SYS_RST_CTRL]    = 0xFFCFFEDCU,
     [CLK_SEL]         = 0xF3F40000U,
     [CLK_STOP_CTRL]   = 0x19FC3E8BU,
     [D2PLL_PARAM]     = 0x00026108U,
     [MPLL_PARAM]      = 0x00030291U,
     [HPLL_PARAM]      = 0x00000291U,
     [MISC_CTRL1]      = 0x00000010U,
     [PCI_CTRL1]       = 0x20001A03U,
     [PCI_CTRL2]       = 0x20001A03U,
     [PCI_CTRL3]       = 0x04000030U,
     [SYS_RST_STATUS]  = 0x00000001U,
     [SOC_SCRATCH1]    = 0x000000C0U, /* SoC completed DRAM init */
     [MISC_CTRL2]      = 0x00000023U,
     [RNG_CTRL]        = 0x0000000EU,
     [PINMUX_CTRL2]    = 0x0000F000U,
     [PINMUX_CTRL3]    = 0x01000000U,
     [PINMUX_CTRL4]    = 0x000000FFU,
     [PINMUX_CTRL5]    = 0x0000A000U,
     [WDT_RST_CTRL]    = 0x003FFFF3U,
     [PINMUX_CTRL8]    = 0xFFFF0000U,
     [PINMUX_CTRL9]    = 0x000FFFFFU,
     [FREE_CNTR4]      = 0x000000FFU,
     [FREE_CNTR4_EXT]  = 0x000000FFU,
     [CPU2_BASE_SEG1]  = 0x80000000U,
     [CPU2_BASE_SEG4]  = 0x1E600000U,
     [CPU2_BASE_SEG5]  = 0xC0000000U,
     [UART_HPLL_CLK]   = 0x00001903U,
     [PCIE_CTRL]       = 0x0000007BU,
     [BMC_DEV_ID]      = 0x00002402U
};

/* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
/* AST2500 revision A1 */

static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
     [SYS_RST_CTRL]    = 0xFFCFFEDCU,
     [CLK_SEL]         = 0xF3F40000U,
     [CLK_STOP_CTRL]   = 0x19FC3E8BU,
     [D2PLL_PARAM]     = 0x00026108U,
     [MPLL_PARAM]      = 0x00030291U,
     [HPLL_PARAM]      = 0x93000400U,
     [MISC_CTRL1]      = 0x00000010U,
     [PCI_CTRL1]       = 0x20001A03U,
     [PCI_CTRL2]       = 0x20001A03U,
     [PCI_CTRL3]       = 0x04000030U,
     [SYS_RST_STATUS]  = 0x00000001U,
     [SOC_SCRATCH1]    = 0x000000C0U, /* SoC completed DRAM init */
     [MISC_CTRL2]      = 0x00000023U,
     [RNG_CTRL]        = 0x0000000EU,
     [PINMUX_CTRL2]    = 0x0000F000U,
     [PINMUX_CTRL3]    = 0x03000000U,
     [PINMUX_CTRL4]    = 0x00000000U,
     [PINMUX_CTRL5]    = 0x0000A000U,
     [WDT_RST_CTRL]    = 0x023FFFF3U,
     [PINMUX_CTRL8]    = 0xFFFF0000U,
     [PINMUX_CTRL9]    = 0x000FFFFFU,
     [FREE_CNTR4]      = 0x000000FFU,
     [FREE_CNTR4_EXT]  = 0x000000FFU,
     [CPU2_BASE_SEG1]  = 0x80000000U,
     [CPU2_BASE_SEG4]  = 0x1E600000U,
     [CPU2_BASE_SEG5]  = 0xC0000000U,
     [UART_HPLL_CLK]   = 0x00001903U,
     [PCIE_CTRL]       = 0x0000007BU,
     [BMC_DEV_ID]      = 0x00002402U
};

static uint32_t aspeed_scu_get_random(void)
{
    uint32_t num;
    qemu_guest_getrandom_nofail(&num, sizeof(num));
    return num;
}

static void aspeed_scu_set_apb_freq(AspeedSCUState *s)
{
    uint32_t apb_divider;

    switch (s->silicon_rev) {
    case AST2400_A0_SILICON_REV:
    case AST2400_A1_SILICON_REV:
        apb_divider = 2;
        break;
    case AST2500_A0_SILICON_REV:
    case AST2500_A1_SILICON_REV:
        apb_divider = 4;
        break;
    default:
        g_assert_not_reached();
    }

    s->apb_freq = s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
        / apb_divider;
}

static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
{
    AspeedSCUState *s = ASPEED_SCU(opaque);
    int reg = TO_REG(offset);

    if (reg >= ARRAY_SIZE(s->regs)) {
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
        return 0;
    }

    switch (reg) {
    case RNG_DATA:
        /* On hardware, RNG_DATA works regardless of
         * the state of the enable bit in RNG_CTRL
         */
        s->regs[RNG_DATA] = aspeed_scu_get_random();
        break;
    case WAKEUP_EN:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
        break;
    }

    return s->regs[reg];
}

static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
                             unsigned size)
{
    AspeedSCUState *s = ASPEED_SCU(opaque);
    int reg = TO_REG(offset);

    if (reg >= ARRAY_SIZE(s->regs)) {
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
        return;
    }

    if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
            !s->regs[PROT_KEY]) {
        qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
        return;
    }

    trace_aspeed_scu_write(offset, size, data);

    switch (reg) {
    case PROT_KEY:
        s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
        return;
    case CLK_SEL:
        s->regs[reg] = data;
        aspeed_scu_set_apb_freq(s);
        break;
    case HW_STRAP1:
        if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
            s->regs[HW_STRAP1] |= data;
            return;
        }
        /* Jump to assignment below */
        break;
    case SILICON_REV:
        if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
            s->regs[HW_STRAP1] &= ~data;
        } else {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
                          __func__, offset);
        }
        /* Avoid assignment below, we've handled everything */
        return;
    case FREQ_CNTR_EVAL:
    case VGA_SCRATCH1 ... VGA_SCRATCH8:
    case RNG_DATA:
    case FREE_CNTR4:
    case FREE_CNTR4_EXT:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
        return;
    }

    s->regs[reg] = data;
}

static const MemoryRegionOps aspeed_scu_ops = {
    .read = aspeed_scu_read,
    .write = aspeed_scu_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
    .valid.unaligned = false,
};

static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s)
{
    if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) {
        return 25000000;
    } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) {
        return 48000000;
    } else {
        return 24000000;
    }
}

/*
 * Strapped frequencies for the AST2400 in MHz. They depend on the
 * clkin frequency.
 */
static const uint32_t hpll_ast2400_freqs[][4] = {
    { 384, 360, 336, 408 }, /* 24MHz or 48MHz */
    { 400, 375, 350, 425 }, /* 25MHz */
};

static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s)
{
    uint32_t hpll_reg = s->regs[HPLL_PARAM];
    uint8_t freq_select;
    bool clk_25m_in;

    if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
        return 0;
    }

    if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) {
        uint32_t multiplier = 1;

        if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) {
            uint32_t n  = (hpll_reg >> 5) & 0x3f;
            uint32_t od = (hpll_reg >> 4) & 0x1;
            uint32_t d  = hpll_reg & 0xf;

            multiplier = (2 - od) * ((n + 2) / (d + 1));
        }

        return s->clkin * multiplier;
    }

    /* HW strapping */
    clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN);
    freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1);

    return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
}

static uint32_t aspeed_scu_calc_hpll_ast2500(AspeedSCUState *s)
{
    uint32_t hpll_reg   = s->regs[HPLL_PARAM];
    uint32_t multiplier = 1;

    if (hpll_reg & SCU_H_PLL_OFF) {
        return 0;
    }

    if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) {
        uint32_t p = (hpll_reg >> 13) & 0x3f;
        uint32_t m = (hpll_reg >> 5) & 0xff;
        uint32_t n = hpll_reg & 0x1f;

        multiplier = ((m + 1) / (n + 1)) / (p + 1);
    }

    return s->clkin * multiplier;
}

static void aspeed_scu_reset(DeviceState *dev)
{
    AspeedSCUState *s = ASPEED_SCU(dev);
    const uint32_t *reset;
    uint32_t (*calc_hpll)(AspeedSCUState *s);

    switch (s->silicon_rev) {
    case AST2400_A0_SILICON_REV:
    case AST2400_A1_SILICON_REV:
        reset = ast2400_a0_resets;
        calc_hpll = aspeed_scu_calc_hpll_ast2400;
        break;
    case AST2500_A0_SILICON_REV:
    case AST2500_A1_SILICON_REV:
        reset = ast2500_a1_resets;
        calc_hpll = aspeed_scu_calc_hpll_ast2500;
        break;
    default:
        g_assert_not_reached();
    }

    memcpy(s->regs, reset, sizeof(s->regs));
    s->regs[SILICON_REV] = s->silicon_rev;
    s->regs[HW_STRAP1] = s->hw_strap1;
    s->regs[HW_STRAP2] = s->hw_strap2;
    s->regs[PROT_KEY] = s->hw_prot_key;

    /*
     * All registers are set. Now compute the frequencies of the main clocks
     */
    s->clkin = aspeed_scu_get_clkin(s);
    s->hpll = calc_hpll(s);
    aspeed_scu_set_apb_freq(s);
}

static uint32_t aspeed_silicon_revs[] = {
    AST2400_A0_SILICON_REV,
    AST2400_A1_SILICON_REV,
    AST2500_A0_SILICON_REV,
    AST2500_A1_SILICON_REV,
};

bool is_supported_silicon_rev(uint32_t silicon_rev)
{
    int i;

    for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
        if (silicon_rev == aspeed_silicon_revs[i]) {
            return true;
        }
    }

    return false;
}

static void aspeed_scu_realize(DeviceState *dev, Error **errp)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    AspeedSCUState *s = ASPEED_SCU(dev);

    if (!is_supported_silicon_rev(s->silicon_rev)) {
        error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
                s->silicon_rev);
        return;
    }

    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s,
                          TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);

    sysbus_init_mmio(sbd, &s->iomem);
}

static const VMStateDescription vmstate_aspeed_scu = {
    .name = "aspeed.scu",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS),
        VMSTATE_END_OF_LIST()
    }
};

static Property aspeed_scu_properties[] = {
    DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
    DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
    DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
    DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void aspeed_scu_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    dc->realize = aspeed_scu_realize;
    dc->reset = aspeed_scu_reset;
    dc->desc = "ASPEED System Control Unit";
    dc->vmsd = &vmstate_aspeed_scu;
    dc->props = aspeed_scu_properties;
}

static const TypeInfo aspeed_scu_info = {
    .name = TYPE_ASPEED_SCU,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(AspeedSCUState),
    .class_init = aspeed_scu_class_init,
};

static void aspeed_scu_register_types(void)
{
    type_register_static(&aspeed_scu_info);
}

type_init(aspeed_scu_register_types);
Commit	Line	Data
1c8a2388 AJ	1	/*
	2	* ASPEED System Control Unit
	3	*
	4	* Andrew Jeffery <andrew@aj.id.au>
	5	*
	6	* Copyright 2016 IBM Corp.
	7	*
	8	* This code is licensed under the GPL version 2 or later. See
	9	* the COPYING file in the top-level directory.
	10	*/
	11
	12	#include "qemu/osdep.h"
	13	#include "hw/misc/aspeed_scu.h"
	14	#include "hw/qdev-properties.h"
	15	#include "qapi/error.h"
	16	#include "qapi/visitor.h"
	17	#include "qemu/bitops.h"
aa4b04a0	18	#include "qemu/log.h"
9d44cb5b	19	#include "qemu/guest-random.h"
0b8fa32f	20	#include "qemu/module.h"
1c8a2388 AJ	21	#include "trace.h"
	22
	23	#define TO_REG(offset) ((offset) >> 2)
	24
	25	#define PROT_KEY TO_REG(0x00)
	26	#define SYS_RST_CTRL TO_REG(0x04)
	27	#define CLK_SEL TO_REG(0x08)
	28	#define CLK_STOP_CTRL TO_REG(0x0C)
	29	#define FREQ_CNTR_CTRL TO_REG(0x10)
	30	#define FREQ_CNTR_EVAL TO_REG(0x14)
	31	#define IRQ_CTRL TO_REG(0x18)
	32	#define D2PLL_PARAM TO_REG(0x1C)
	33	#define MPLL_PARAM TO_REG(0x20)
	34	#define HPLL_PARAM TO_REG(0x24)
	35	#define FREQ_CNTR_RANGE TO_REG(0x28)
	36	#define MISC_CTRL1 TO_REG(0x2C)
	37	#define PCI_CTRL1 TO_REG(0x30)
	38	#define PCI_CTRL2 TO_REG(0x34)
	39	#define PCI_CTRL3 TO_REG(0x38)
	40	#define SYS_RST_STATUS TO_REG(0x3C)
	41	#define SOC_SCRATCH1 TO_REG(0x40)
	42	#define SOC_SCRATCH2 TO_REG(0x44)
	43	#define MAC_CLK_DELAY TO_REG(0x48)
	44	#define MISC_CTRL2 TO_REG(0x4C)
	45	#define VGA_SCRATCH1 TO_REG(0x50)
	46	#define VGA_SCRATCH2 TO_REG(0x54)
	47	#define VGA_SCRATCH3 TO_REG(0x58)
	48	#define VGA_SCRATCH4 TO_REG(0x5C)
	49	#define VGA_SCRATCH5 TO_REG(0x60)
	50	#define VGA_SCRATCH6 TO_REG(0x64)
	51	#define VGA_SCRATCH7 TO_REG(0x68)
	52	#define VGA_SCRATCH8 TO_REG(0x6C)
	53	#define HW_STRAP1 TO_REG(0x70)
	54	#define RNG_CTRL TO_REG(0x74)
	55	#define RNG_DATA TO_REG(0x78)
	56	#define SILICON_REV TO_REG(0x7C)
	57	#define PINMUX_CTRL1 TO_REG(0x80)
	58	#define PINMUX_CTRL2 TO_REG(0x84)
	59	#define PINMUX_CTRL3 TO_REG(0x88)
	60	#define PINMUX_CTRL4 TO_REG(0x8C)
	61	#define PINMUX_CTRL5 TO_REG(0x90)
	62	#define PINMUX_CTRL6 TO_REG(0x94)
	63	#define WDT_RST_CTRL TO_REG(0x9C)
	64	#define PINMUX_CTRL7 TO_REG(0xA0)
	65	#define PINMUX_CTRL8 TO_REG(0xA4)
	66	#define PINMUX_CTRL9 TO_REG(0xA8)
	67	#define WAKEUP_EN TO_REG(0xC0)
	68	#define WAKEUP_CTRL TO_REG(0xC4)
	69	#define HW_STRAP2 TO_REG(0xD0)
	70	#define FREE_CNTR4 TO_REG(0xE0)
	71	#define FREE_CNTR4_EXT TO_REG(0xE4)
	72	#define CPU2_CTRL TO_REG(0x100)
	73	#define CPU2_BASE_SEG1 TO_REG(0x104)
	74	#define CPU2_BASE_SEG2 TO_REG(0x108)
	75	#define CPU2_BASE_SEG3 TO_REG(0x10C)
	76	#define CPU2_BASE_SEG4 TO_REG(0x110)
	77	#define CPU2_BASE_SEG5 TO_REG(0x114)
	78	#define CPU2_CACHE_CTRL TO_REG(0x118)
	79	#define UART_HPLL_CLK TO_REG(0x160)
	80	#define PCIE_CTRL TO_REG(0x180)
	81	#define BMC_MMIO_CTRL TO_REG(0x184)
	82	#define RELOC_DECODE_BASE1 TO_REG(0x188)
	83	#define RELOC_DECODE_BASE2 TO_REG(0x18C)
	84	#define MAILBOX_DECODE_BASE TO_REG(0x190)
85	#define SRAM_DECODE_BASE1 TO_REG(0x194)
86	#define SRAM_DECODE_BASE2 TO_REG(0x198)
87	#define BMC_REV TO_REG(0x19C)
88	#define BMC_DEV_ID TO_REG(0x1A4)
89
c491e152	90	#define SCU_IO_REGION_SIZE 0x1000
1c8a2388	91
1c8a2388 AJ	92	static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
	93	[SYS_RST_CTRL] = 0xFFCFFEDCU,
	94	[CLK_SEL] = 0xF3F40000U,
	95	[CLK_STOP_CTRL] = 0x19FC3E8BU,
	96	[D2PLL_PARAM] = 0x00026108U,
	97	[MPLL_PARAM] = 0x00030291U,
	98	[HPLL_PARAM] = 0x00000291U,
	99	[MISC_CTRL1] = 0x00000010U,
	100	[PCI_CTRL1] = 0x20001A03U,
	101	[PCI_CTRL2] = 0x20001A03U,
	102	[PCI_CTRL3] = 0x04000030U,
	103	[SYS_RST_STATUS] = 0x00000001U,
	104	[SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
	105	[MISC_CTRL2] = 0x00000023U,
	106	[RNG_CTRL] = 0x0000000EU,
	107	[PINMUX_CTRL2] = 0x0000F000U,
	108	[PINMUX_CTRL3] = 0x01000000U,
	109	[PINMUX_CTRL4] = 0x000000FFU,
	110	[PINMUX_CTRL5] = 0x0000A000U,
	111	[WDT_RST_CTRL] = 0x003FFFF3U,
	112	[PINMUX_CTRL8] = 0xFFFF0000U,
	113	[PINMUX_CTRL9] = 0x000FFFFFU,
	114	[FREE_CNTR4] = 0x000000FFU,
	115	[FREE_CNTR4_EXT] = 0x000000FFU,
	116	[CPU2_BASE_SEG1] = 0x80000000U,
	117	[CPU2_BASE_SEG4] = 0x1E600000U,
	118	[CPU2_BASE_SEG5] = 0xC0000000U,
	119	[UART_HPLL_CLK] = 0x00001903U,
	120	[PCIE_CTRL] = 0x0000007BU,
	121	[BMC_DEV_ID] = 0x00002402U
	122	};
	123
365aff1e CLG	124	/* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
	125	/* AST2500 revision A1 */
	126
	127	static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
	128	[SYS_RST_CTRL] = 0xFFCFFEDCU,
	129	[CLK_SEL] = 0xF3F40000U,
	130	[CLK_STOP_CTRL] = 0x19FC3E8BU,
	131	[D2PLL_PARAM] = 0x00026108U,
	132	[MPLL_PARAM] = 0x00030291U,
	133	[HPLL_PARAM] = 0x93000400U,
	134	[MISC_CTRL1] = 0x00000010U,
	135	[PCI_CTRL1] = 0x20001A03U,
	136	[PCI_CTRL2] = 0x20001A03U,
	137	[PCI_CTRL3] = 0x04000030U,
	138	[SYS_RST_STATUS] = 0x00000001U,
	139	[SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
	140	[MISC_CTRL2] = 0x00000023U,
	141	[RNG_CTRL] = 0x0000000EU,
	142	[PINMUX_CTRL2] = 0x0000F000U,
	143	[PINMUX_CTRL3] = 0x03000000U,
	144	[PINMUX_CTRL4] = 0x00000000U,
	145	[PINMUX_CTRL5] = 0x0000A000U,
	146	[WDT_RST_CTRL] = 0x023FFFF3U,
	147	[PINMUX_CTRL8] = 0xFFFF0000U,
	148	[PINMUX_CTRL9] = 0x000FFFFFU,
	149	[FREE_CNTR4] = 0x000000FFU,
	150	[FREE_CNTR4_EXT] = 0x000000FFU,
	151	[CPU2_BASE_SEG1] = 0x80000000U,
	152	[CPU2_BASE_SEG4] = 0x1E600000U,
	153	[CPU2_BASE_SEG5] = 0xC0000000U,
	154	[UART_HPLL_CLK] = 0x00001903U,
	155	[PCIE_CTRL] = 0x0000007BU,
	156	[BMC_DEV_ID] = 0x00002402U
	157	};
	158
acd9575e JS	159	static uint32_t aspeed_scu_get_random(void)
acd9575e JS	160	{
acd9575e	161	uint32_t num;
9d44cb5b	162	qemu_guest_getrandom_nofail(&num, sizeof(num));
acd9575e JS	163	return num;
	164	}
	165
fda9aaa6 CLG	166	static void aspeed_scu_set_apb_freq(AspeedSCUState *s)
	167	{
	168	uint32_t apb_divider;
	169
	170	switch (s->silicon_rev) {
	171	case AST2400_A0_SILICON_REV:
	172	case AST2400_A1_SILICON_REV:
	173	apb_divider = 2;
	174	break;
	175	case AST2500_A0_SILICON_REV:
	176	case AST2500_A1_SILICON_REV:
	177	apb_divider = 4;
	178	break;
	179	default:
	180	g_assert_not_reached();
	181	}
	182
	183	s->apb_freq = s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
	184	/ apb_divider;
	185	}
	186
1c8a2388 AJ	187	static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
	188	{
	189	AspeedSCUState *s = ASPEED_SCU(opaque);
	190	int reg = TO_REG(offset);
	191
	192	if (reg >= ARRAY_SIZE(s->regs)) {
	193	qemu_log_mask(LOG_GUEST_ERROR,
	194	"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
	195	__func__, offset);
	196	return 0;
	197	}
	198
	199	switch (reg) {
acd9575e JS	200	case RNG_DATA:
	201	/* On hardware, RNG_DATA works regardless of
	202	* the state of the enable bit in RNG_CTRL
	203	*/
	204	s->regs[RNG_DATA] = aspeed_scu_get_random();
	205	break;
1c8a2388 AJ	206	case WAKEUP_EN:
	207	qemu_log_mask(LOG_GUEST_ERROR,
	208	"%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
	209	__func__, offset);
	210	break;
	211	}
	212
	213	return s->regs[reg];
	214	}
	215
	216	static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
	217	unsigned size)
	218	{
	219	AspeedSCUState *s = ASPEED_SCU(opaque);
	220	int reg = TO_REG(offset);
	221
	222	if (reg >= ARRAY_SIZE(s->regs)) {
	223	qemu_log_mask(LOG_GUEST_ERROR,
	224	"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
	225	__func__, offset);
	226	return;
	227	}
	228
	229	if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
5c1d3a2b	230	!s->regs[PROT_KEY]) {
1c8a2388 AJ	231	qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
	232	return;
	233	}
	234
	235	trace_aspeed_scu_write(offset, size, data);
	236
	237	switch (reg) {
5c1d3a2b HL	238	case PROT_KEY:
	239	s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
	240	return;
fda9aaa6 CLG	241	case CLK_SEL:
	242	s->regs[reg] = data;
	243	aspeed_scu_set_apb_freq(s);
	244	break;
333b9c8a AJ	245	case HW_STRAP1:
	246	if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
	247	s->regs[HW_STRAP1] \|= data;
	248	return;
	249	}
	250	/* Jump to assignment below */
	251	break;
	252	case SILICON_REV:
	253	if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
	254	s->regs[HW_STRAP1] &= ~data;
	255	} else {
	256	qemu_log_mask(LOG_GUEST_ERROR,
	257	"%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
	258	__func__, offset);
	259	}
	260	/* Avoid assignment below, we've handled everything */
	261	return;
1c8a2388 AJ	262	case FREQ_CNTR_EVAL:
	263	case VGA_SCRATCH1 ... VGA_SCRATCH8:
	264	case RNG_DATA:
1c8a2388 AJ	265	case FREE_CNTR4:
	266	case FREE_CNTR4_EXT:
	267	qemu_log_mask(LOG_GUEST_ERROR,
	268	"%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
	269	__func__, offset);
	270	return;
	271	}
	272
	273	s->regs[reg] = data;
	274	}
	275
	276	static const MemoryRegionOps aspeed_scu_ops = {
	277	.read = aspeed_scu_read,
	278	.write = aspeed_scu_write,
	279	.endianness = DEVICE_LITTLE_ENDIAN,
	280	.valid.min_access_size = 4,
	281	.valid.max_access_size = 4,
	282	.valid.unaligned = false,
	283	};
	284
fda9aaa6 CLG	285	static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s)
	286	{
	287	if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) {
	288	return 25000000;
	289	} else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) {
	290	return 48000000;
	291	} else {
	292	return 24000000;
	293	}
	294	}
	295
	296	/*
	297	* Strapped frequencies for the AST2400 in MHz. They depend on the
	298	* clkin frequency.
	299	*/
	300	static const uint32_t hpll_ast2400_freqs[][4] = {
	301	{ 384, 360, 336, 408 }, /* 24MHz or 48MHz */
	302	{ 400, 375, 350, 425 }, /* 25MHz */
	303	};
	304
	305	static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s)
	306	{
	307	uint32_t hpll_reg = s->regs[HPLL_PARAM];
	308	uint8_t freq_select;
	309	bool clk_25m_in;
	310
	311	if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
	312	return 0;
	313	}
	314
	315	if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) {
	316	uint32_t multiplier = 1;
	317
	318	if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) {
	319	uint32_t n = (hpll_reg >> 5) & 0x3f;
	320	uint32_t od = (hpll_reg >> 4) & 0x1;
	321	uint32_t d = hpll_reg & 0xf;
	322
	323	multiplier = (2 - od) * ((n + 2) / (d + 1));
	324	}
	325
	326	return s->clkin * multiplier;
	327	}
	328
	329	/* HW strapping */
	330	clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN);
	331	freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1);
	332
	333	return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
	334	}
	335
	336	static uint32_t aspeed_scu_calc_hpll_ast2500(AspeedSCUState *s)
	337	{
	338	uint32_t hpll_reg = s->regs[HPLL_PARAM];
	339	uint32_t multiplier = 1;
	340
	341	if (hpll_reg & SCU_H_PLL_OFF) {
	342	return 0;
	343	}
	344
	345	if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) {
	346	uint32_t p = (hpll_reg >> 13) & 0x3f;
	347	uint32_t m = (hpll_reg >> 5) & 0xff;
	348	uint32_t n = hpll_reg & 0x1f;
349
350	multiplier = ((m + 1) / (n + 1)) / (p + 1);
351	}
352
353	return s->clkin * multiplier;
354	}
355
1c8a2388 AJ	356	static void aspeed_scu_reset(DeviceState *dev)
	357	{
	358	AspeedSCUState *s = ASPEED_SCU(dev);
	359	const uint32_t *reset;
fda9aaa6	360	uint32_t (calc_hpll)(AspeedSCUState s);
1c8a2388 AJ	361
	362	switch (s->silicon_rev) {
	363	case AST2400_A0_SILICON_REV:
6efbac90	364	case AST2400_A1_SILICON_REV:
1c8a2388	365	reset = ast2400_a0_resets;
fda9aaa6	366	calc_hpll = aspeed_scu_calc_hpll_ast2400;
1c8a2388	367	break;
365aff1e CLG	368	case AST2500_A0_SILICON_REV:
	369	case AST2500_A1_SILICON_REV:
	370	reset = ast2500_a1_resets;
fda9aaa6	371	calc_hpll = aspeed_scu_calc_hpll_ast2500;
365aff1e	372	break;
1c8a2388 AJ	373	default:
	374	g_assert_not_reached();
	375	}
	376
	377	memcpy(s->regs, reset, sizeof(s->regs));
	378	s->regs[SILICON_REV] = s->silicon_rev;
	379	s->regs[HW_STRAP1] = s->hw_strap1;
	380	s->regs[HW_STRAP2] = s->hw_strap2;
b6e70d1d	381	s->regs[PROT_KEY] = s->hw_prot_key;
fda9aaa6 CLG	382
	383	/*
	384	* All registers are set. Now compute the frequencies of the main clocks
	385	*/
	386	s->clkin = aspeed_scu_get_clkin(s);
	387	s->hpll = calc_hpll(s);
	388	aspeed_scu_set_apb_freq(s);
1c8a2388 AJ	389	}
1c8a2388 AJ	390
365aff1e CLG	391	static uint32_t aspeed_silicon_revs[] = {
365aff1e CLG	392	AST2400_A0_SILICON_REV,
6efbac90	393	AST2400_A1_SILICON_REV,
365aff1e CLG	394	AST2500_A0_SILICON_REV,
	395	AST2500_A1_SILICON_REV,
	396	};
1c8a2388	397
79a9f323	398	bool is_supported_silicon_rev(uint32_t silicon_rev)
1c8a2388 AJ	399	{
	400	int i;
	401
	402	for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
	403	if (silicon_rev == aspeed_silicon_revs[i]) {
	404	return true;
	405	}
	406	}
	407
	408	return false;
	409	}
	410
	411	static void aspeed_scu_realize(DeviceState dev, Error *errp)
	412	{
	413	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
	414	AspeedSCUState *s = ASPEED_SCU(dev);
	415
	416	if (!is_supported_silicon_rev(s->silicon_rev)) {
	417	error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
	418	s->silicon_rev);
	419	return;
	420	}
	421
	422	memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s,
	423	TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
	424
	425	sysbus_init_mmio(sbd, &s->iomem);
	426	}
	427
	428	static const VMStateDescription vmstate_aspeed_scu = {
	429	.name = "aspeed.scu",
	430	.version_id = 1,
	431	.minimum_version_id = 1,
	432	.fields = (VMStateField[]) {
	433	VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS),
	434	VMSTATE_END_OF_LIST()
	435	}
	436	};
	437
	438	static Property aspeed_scu_properties[] = {
	439	DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
	440	DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
2ddfa281	441	DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
b6e70d1d	442	DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
1c8a2388 AJ	443	DEFINE_PROP_END_OF_LIST(),
	444	};
	445
	446	static void aspeed_scu_class_init(ObjectClass klass, void data)
	447	{
	448	DeviceClass *dc = DEVICE_CLASS(klass);
	449	dc->realize = aspeed_scu_realize;
	450	dc->reset = aspeed_scu_reset;
	451	dc->desc = "ASPEED System Control Unit";
	452	dc->vmsd = &vmstate_aspeed_scu;
	453	dc->props = aspeed_scu_properties;
	454	}
	455
	456	static const TypeInfo aspeed_scu_info = {
	457	.name = TYPE_ASPEED_SCU,
	458	.parent = TYPE_SYS_BUS_DEVICE,
	459	.instance_size = sizeof(AspeedSCUState),
	460	.class_init = aspeed_scu_class_init,
	461	};
	462
	463	static void aspeed_scu_register_types(void)
	464	{
	465	type_register_static(&aspeed_scu_info);
	466	}
	467
	468	type_init(aspeed_scu_register_types);