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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200221' into staging
[mirror_qemu.git] / hw / misc / aspeed_scu.c
CommitLineData
1c8a2388
AJ		 1/*
2 * ASPEED System Control Unit
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12#include "qemu/osdep.h"
13#include "hw/misc/aspeed_scu.h"
14#include "hw/qdev-properties.h"
d6454270 15#include "migration/vmstate.h"
1c8a2388
AJ		 16#include "qapi/error.h"
17#include "qapi/visitor.h"
18#include "qemu/bitops.h"
aa4b04a0 19#include "qemu/log.h"
9d44cb5b 20#include "qemu/guest-random.h"
0b8fa32f 21#include "qemu/module.h"
1c8a2388
AJ		 22#include "trace.h"
23
24#define TO_REG(offset) ((offset) >> 2)
25
26#define PROT_KEY TO_REG(0x00)
27#define SYS_RST_CTRL TO_REG(0x04)
28#define CLK_SEL TO_REG(0x08)
29#define CLK_STOP_CTRL TO_REG(0x0C)
30#define FREQ_CNTR_CTRL TO_REG(0x10)
31#define FREQ_CNTR_EVAL TO_REG(0x14)
32#define IRQ_CTRL TO_REG(0x18)
33#define D2PLL_PARAM TO_REG(0x1C)
34#define MPLL_PARAM TO_REG(0x20)
35#define HPLL_PARAM TO_REG(0x24)
36#define FREQ_CNTR_RANGE TO_REG(0x28)
37#define MISC_CTRL1 TO_REG(0x2C)
38#define PCI_CTRL1 TO_REG(0x30)
39#define PCI_CTRL2 TO_REG(0x34)
40#define PCI_CTRL3 TO_REG(0x38)
41#define SYS_RST_STATUS TO_REG(0x3C)
42#define SOC_SCRATCH1 TO_REG(0x40)
43#define SOC_SCRATCH2 TO_REG(0x44)
44#define MAC_CLK_DELAY TO_REG(0x48)
45#define MISC_CTRL2 TO_REG(0x4C)
46#define VGA_SCRATCH1 TO_REG(0x50)
47#define VGA_SCRATCH2 TO_REG(0x54)
48#define VGA_SCRATCH3 TO_REG(0x58)
49#define VGA_SCRATCH4 TO_REG(0x5C)
50#define VGA_SCRATCH5 TO_REG(0x60)
51#define VGA_SCRATCH6 TO_REG(0x64)
52#define VGA_SCRATCH7 TO_REG(0x68)
53#define VGA_SCRATCH8 TO_REG(0x6C)
54#define HW_STRAP1 TO_REG(0x70)
55#define RNG_CTRL TO_REG(0x74)
56#define RNG_DATA TO_REG(0x78)
57#define SILICON_REV TO_REG(0x7C)
58#define PINMUX_CTRL1 TO_REG(0x80)
59#define PINMUX_CTRL2 TO_REG(0x84)
60#define PINMUX_CTRL3 TO_REG(0x88)
61#define PINMUX_CTRL4 TO_REG(0x8C)
62#define PINMUX_CTRL5 TO_REG(0x90)
63#define PINMUX_CTRL6 TO_REG(0x94)
64#define WDT_RST_CTRL TO_REG(0x9C)
65#define PINMUX_CTRL7 TO_REG(0xA0)
66#define PINMUX_CTRL8 TO_REG(0xA4)
67#define PINMUX_CTRL9 TO_REG(0xA8)
68#define WAKEUP_EN TO_REG(0xC0)
69#define WAKEUP_CTRL TO_REG(0xC4)
70#define HW_STRAP2 TO_REG(0xD0)
71#define FREE_CNTR4 TO_REG(0xE0)
72#define FREE_CNTR4_EXT TO_REG(0xE4)
73#define CPU2_CTRL TO_REG(0x100)
74#define CPU2_BASE_SEG1 TO_REG(0x104)
75#define CPU2_BASE_SEG2 TO_REG(0x108)
76#define CPU2_BASE_SEG3 TO_REG(0x10C)
77#define CPU2_BASE_SEG4 TO_REG(0x110)
78#define CPU2_BASE_SEG5 TO_REG(0x114)
79#define CPU2_CACHE_CTRL TO_REG(0x118)
80#define UART_HPLL_CLK TO_REG(0x160)
81#define PCIE_CTRL TO_REG(0x180)
82#define BMC_MMIO_CTRL TO_REG(0x184)
83#define RELOC_DECODE_BASE1 TO_REG(0x188)
84#define RELOC_DECODE_BASE2 TO_REG(0x18C)
85#define MAILBOX_DECODE_BASE TO_REG(0x190)
86#define SRAM_DECODE_BASE1 TO_REG(0x194)
87#define SRAM_DECODE_BASE2 TO_REG(0x198)
88#define BMC_REV TO_REG(0x19C)
89#define BMC_DEV_ID TO_REG(0x1A4)
90
e09cf363
JS		 91#define AST2600_PROT_KEY TO_REG(0x00)
92#define AST2600_SILICON_REV TO_REG(0x04)
93#define AST2600_SILICON_REV2 TO_REG(0x14)
94#define AST2600_SYS_RST_CTRL TO_REG(0x40)
95#define AST2600_SYS_RST_CTRL_CLR TO_REG(0x44)
96#define AST2600_SYS_RST_CTRL2 TO_REG(0x50)
97#define AST2600_SYS_RST_CTRL2_CLR TO_REG(0x54)
98#define AST2600_CLK_STOP_CTRL TO_REG(0x80)
99#define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84)
100#define AST2600_CLK_STOP_CTRL2 TO_REG(0x90)
310b5bc6 101#define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94)
1550d726 102#define AST2600_SDRAM_HANDSHAKE TO_REG(0x100)
e09cf363
JS		 103#define AST2600_HPLL_PARAM TO_REG(0x200)
104#define AST2600_HPLL_EXT TO_REG(0x204)
105#define AST2600_MPLL_EXT TO_REG(0x224)
106#define AST2600_EPLL_EXT TO_REG(0x244)
107#define AST2600_CLK_SEL TO_REG(0x300)
108#define AST2600_CLK_SEL2 TO_REG(0x304)
109#define AST2600_CLK_SEL3 TO_REG(0x310)
110#define AST2600_HW_STRAP1 TO_REG(0x500)
111#define AST2600_HW_STRAP1_CLR TO_REG(0x504)
112#define AST2600_HW_STRAP1_PROT TO_REG(0x508)
113#define AST2600_HW_STRAP2 TO_REG(0x510)
114#define AST2600_HW_STRAP2_CLR TO_REG(0x514)
115#define AST2600_HW_STRAP2_PROT TO_REG(0x518)
116#define AST2600_RNG_CTRL TO_REG(0x524)
117#define AST2600_RNG_DATA TO_REG(0x540)
118
119#define AST2600_CLK TO_REG(0x40)
120
c491e152 121#define SCU_IO_REGION_SIZE 0x1000
1c8a2388 122
1c8a2388
AJ		 123static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
124 [SYS_RST_CTRL] = 0xFFCFFEDCU,
125 [CLK_SEL] = 0xF3F40000U,
126 [CLK_STOP_CTRL] = 0x19FC3E8BU,
127 [D2PLL_PARAM] = 0x00026108U,
128 [MPLL_PARAM] = 0x00030291U,
129 [HPLL_PARAM] = 0x00000291U,
130 [MISC_CTRL1] = 0x00000010U,
131 [PCI_CTRL1] = 0x20001A03U,
132 [PCI_CTRL2] = 0x20001A03U,
133 [PCI_CTRL3] = 0x04000030U,
134 [SYS_RST_STATUS] = 0x00000001U,
135 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
136 [MISC_CTRL2] = 0x00000023U,
137 [RNG_CTRL] = 0x0000000EU,
138 [PINMUX_CTRL2] = 0x0000F000U,
139 [PINMUX_CTRL3] = 0x01000000U,
140 [PINMUX_CTRL4] = 0x000000FFU,
141 [PINMUX_CTRL5] = 0x0000A000U,
142 [WDT_RST_CTRL] = 0x003FFFF3U,
143 [PINMUX_CTRL8] = 0xFFFF0000U,
144 [PINMUX_CTRL9] = 0x000FFFFFU,
145 [FREE_CNTR4] = 0x000000FFU,
146 [FREE_CNTR4_EXT] = 0x000000FFU,
147 [CPU2_BASE_SEG1] = 0x80000000U,
148 [CPU2_BASE_SEG4] = 0x1E600000U,
149 [CPU2_BASE_SEG5] = 0xC0000000U,
150 [UART_HPLL_CLK] = 0x00001903U,
151 [PCIE_CTRL] = 0x0000007BU,
152 [BMC_DEV_ID] = 0x00002402U
153};
154
365aff1e
CLG		 155/* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
156/* AST2500 revision A1 */
157
158static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
159 [SYS_RST_CTRL] = 0xFFCFFEDCU,
160 [CLK_SEL] = 0xF3F40000U,
161 [CLK_STOP_CTRL] = 0x19FC3E8BU,
162 [D2PLL_PARAM] = 0x00026108U,
163 [MPLL_PARAM] = 0x00030291U,
164 [HPLL_PARAM] = 0x93000400U,
165 [MISC_CTRL1] = 0x00000010U,
166 [PCI_CTRL1] = 0x20001A03U,
167 [PCI_CTRL2] = 0x20001A03U,
168 [PCI_CTRL3] = 0x04000030U,
169 [SYS_RST_STATUS] = 0x00000001U,
170 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
171 [MISC_CTRL2] = 0x00000023U,
172 [RNG_CTRL] = 0x0000000EU,
173 [PINMUX_CTRL2] = 0x0000F000U,
174 [PINMUX_CTRL3] = 0x03000000U,
175 [PINMUX_CTRL4] = 0x00000000U,
176 [PINMUX_CTRL5] = 0x0000A000U,
177 [WDT_RST_CTRL] = 0x023FFFF3U,
178 [PINMUX_CTRL8] = 0xFFFF0000U,
179 [PINMUX_CTRL9] = 0x000FFFFFU,
180 [FREE_CNTR4] = 0x000000FFU,
181 [FREE_CNTR4_EXT] = 0x000000FFU,
182 [CPU2_BASE_SEG1] = 0x80000000U,
183 [CPU2_BASE_SEG4] = 0x1E600000U,
184 [CPU2_BASE_SEG5] = 0xC0000000U,
185 [UART_HPLL_CLK] = 0x00001903U,
186 [PCIE_CTRL] = 0x0000007BU,
187 [BMC_DEV_ID] = 0x00002402U
188};
189
acd9575e
JS		 190static uint32_t aspeed_scu_get_random(void)
191{
acd9575e 192 uint32_t num;
9d44cb5b 193 qemu_guest_getrandom_nofail(&num, sizeof(num));
acd9575e
JS		 194 return num;
195}
196
a8f07376 197uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s)
fda9aaa6 198{
9a937f6c 199 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
a8f07376 200 uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]);
fda9aaa6 201
a8f07376 202 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
9a937f6c 203 / asc->apb_divider;
fda9aaa6
CLG		 204}
205
1c8a2388
AJ		 206static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
207{
208 AspeedSCUState *s = ASPEED_SCU(opaque);
209 int reg = TO_REG(offset);
210
e09cf363 211 if (reg >= ASPEED_SCU_NR_REGS) {
1c8a2388
AJ		 212 qemu_log_mask(LOG_GUEST_ERROR,
213 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
214 __func__, offset);
215 return 0;
216 }
217
218 switch (reg) {
acd9575e
JS		 219 case RNG_DATA:
220 /* On hardware, RNG_DATA works regardless of
221 * the state of the enable bit in RNG_CTRL
222 */
223 s->regs[RNG_DATA] = aspeed_scu_get_random();
224 break;
1c8a2388
AJ		 225 case WAKEUP_EN:
226 qemu_log_mask(LOG_GUEST_ERROR,
227 "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
228 __func__, offset);
229 break;
230 }
231
232 return s->regs[reg];
233}
234
235static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
236 unsigned size)
237{
238 AspeedSCUState *s = ASPEED_SCU(opaque);
239 int reg = TO_REG(offset);
240
e09cf363 241 if (reg >= ASPEED_SCU_NR_REGS) {
1c8a2388
AJ		 242 qemu_log_mask(LOG_GUEST_ERROR,
243 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
244 __func__, offset);
245 return;
246 }
247
248 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
5c1d3a2b 249 !s->regs[PROT_KEY]) {
1c8a2388
AJ		 250 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
251 return;
252 }
253
254 trace_aspeed_scu_write(offset, size, data);
255
256 switch (reg) {
5c1d3a2b
HL		 257 case PROT_KEY:
258 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
259 return;
fda9aaa6
CLG		 260 case CLK_SEL:
261 s->regs[reg] = data;
fda9aaa6 262 break;
333b9c8a
AJ		 263 case HW_STRAP1:
264 if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
265 s->regs[HW_STRAP1] |= data;
266 return;
267 }
268 /* Jump to assignment below */
269 break;
270 case SILICON_REV:
271 if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
272 s->regs[HW_STRAP1] &= ~data;
273 } else {
274 qemu_log_mask(LOG_GUEST_ERROR,
275 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
276 __func__, offset);
277 }
278 /* Avoid assignment below, we've handled everything */
279 return;
1c8a2388
AJ		 280 case FREQ_CNTR_EVAL:
281 case VGA_SCRATCH1 ... VGA_SCRATCH8:
282 case RNG_DATA:
1c8a2388
AJ		 283 case FREE_CNTR4:
284 case FREE_CNTR4_EXT:
285 qemu_log_mask(LOG_GUEST_ERROR,
286 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
287 __func__, offset);
288 return;
289 }
290
291 s->regs[reg] = data;
292}
293
294static const MemoryRegionOps aspeed_scu_ops = {
295 .read = aspeed_scu_read,
296 .write = aspeed_scu_write,
297 .endianness = DEVICE_LITTLE_ENDIAN,
298 .valid.min_access_size = 4,
299 .valid.max_access_size = 4,
300 .valid.unaligned = false,
301};
302
fda9aaa6
CLG		 303static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s)
304{
305 if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) {
306 return 25000000;
307 } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) {
308 return 48000000;
309 } else {
310 return 24000000;
311 }
312}
313
314/*
315 * Strapped frequencies for the AST2400 in MHz. They depend on the
316 * clkin frequency.
317 */
318static const uint32_t hpll_ast2400_freqs[][4] = {
319 { 384, 360, 336, 408 }, /* 24MHz or 48MHz */
320 { 400, 375, 350, 425 }, /* 25MHz */
321};
322
a8f07376 323static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
fda9aaa6 324{
fda9aaa6
CLG		 325 uint8_t freq_select;
326 bool clk_25m_in;
a8f07376 327 uint32_t clkin = aspeed_scu_get_clkin(s);
fda9aaa6
CLG		 328
329 if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
330 return 0;
331 }
332
333 if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) {
334 uint32_t multiplier = 1;
335
336 if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) {
337 uint32_t n = (hpll_reg >> 5) & 0x3f;
338 uint32_t od = (hpll_reg >> 4) & 0x1;
339 uint32_t d = hpll_reg & 0xf;
340
341 multiplier = (2 - od) * ((n + 2) / (d + 1));
342 }
343
a8f07376 344 return clkin * multiplier;
fda9aaa6
CLG		 345 }
346
347 /* HW strapping */
348 clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN);
349 freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1);
350
351 return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
352}
353
a8f07376 354static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
fda9aaa6 355{
fda9aaa6 356 uint32_t multiplier = 1;
a8f07376 357 uint32_t clkin = aspeed_scu_get_clkin(s);
fda9aaa6
CLG		 358
359 if (hpll_reg & SCU_H_PLL_OFF) {
360 return 0;
361 }
362
363 if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) {
364 uint32_t p = (hpll_reg >> 13) & 0x3f;
365 uint32_t m = (hpll_reg >> 5) & 0xff;
366 uint32_t n = hpll_reg & 0x1f;
367
368 multiplier = ((m + 1) / (n + 1)) / (p + 1);
369 }
370
a8f07376 371 return clkin * multiplier;
fda9aaa6
CLG		 372}
373
1c8a2388
AJ		 374static void aspeed_scu_reset(DeviceState *dev)
375{
376 AspeedSCUState *s = ASPEED_SCU(dev);
9a937f6c 377 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
1c8a2388 378
e09cf363 379 memcpy(s->regs, asc->resets, asc->nr_regs * 4);
1c8a2388
AJ		 380 s->regs[SILICON_REV] = s->silicon_rev;
381 s->regs[HW_STRAP1] = s->hw_strap1;
382 s->regs[HW_STRAP2] = s->hw_strap2;
b6e70d1d 383 s->regs[PROT_KEY] = s->hw_prot_key;
1c8a2388
AJ		 384}
385
365aff1e
CLG		 386static uint32_t aspeed_silicon_revs[] = {
387 AST2400_A0_SILICON_REV,
6efbac90 388 AST2400_A1_SILICON_REV,
365aff1e
CLG		 389 AST2500_A0_SILICON_REV,
390 AST2500_A1_SILICON_REV,
e09cf363 391 AST2600_A0_SILICON_REV,
365aff1e 392};
1c8a2388 393
79a9f323 394bool is_supported_silicon_rev(uint32_t silicon_rev)
1c8a2388
AJ		 395{
396 int i;
397
398 for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
399 if (silicon_rev == aspeed_silicon_revs[i]) {
400 return true;
401 }
402 }
403
404 return false;
405}
406
407static void aspeed_scu_realize(DeviceState *dev, Error **errp)
408{
409 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
410 AspeedSCUState *s = ASPEED_SCU(dev);
e09cf363 411 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
1c8a2388
AJ		 412
413 if (!is_supported_silicon_rev(s->silicon_rev)) {
414 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
415 s->silicon_rev);
416 return;
417 }
418
e09cf363 419 memory_region_init_io(&s->iomem, OBJECT(s), asc->ops, s,
1c8a2388
AJ		 420 TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
421
422 sysbus_init_mmio(sbd, &s->iomem);
423}
424
425static const VMStateDescription vmstate_aspeed_scu = {
426 .name = "aspeed.scu",
e09cf363
JS		 427 .version_id = 2,
428 .minimum_version_id = 2,
1c8a2388 429 .fields = (VMStateField[]) {
e09cf363 430 VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS),
1c8a2388
AJ		 431 VMSTATE_END_OF_LIST()
432 }
433};
434
435static Property aspeed_scu_properties[] = {
436 DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
437 DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
2ddfa281 438 DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
b6e70d1d 439 DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
1c8a2388
AJ		 440 DEFINE_PROP_END_OF_LIST(),
441};
442
443static void aspeed_scu_class_init(ObjectClass *klass, void *data)
444{
445 DeviceClass *dc = DEVICE_CLASS(klass);
446 dc->realize = aspeed_scu_realize;
447 dc->reset = aspeed_scu_reset;
448 dc->desc = "ASPEED System Control Unit";
449 dc->vmsd = &vmstate_aspeed_scu;
4f67d30b 450 device_class_set_props(dc, aspeed_scu_properties);
1c8a2388
AJ		 451}
452
453static const TypeInfo aspeed_scu_info = {
454 .name = TYPE_ASPEED_SCU,
455 .parent = TYPE_SYS_BUS_DEVICE,
456 .instance_size = sizeof(AspeedSCUState),
457 .class_init = aspeed_scu_class_init,
9a937f6c
CLG		 458 .class_size = sizeof(AspeedSCUClass),
459 .abstract = true,
460};
461
462static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data)
463{
464 DeviceClass *dc = DEVICE_CLASS(klass);
465 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
466
467 dc->desc = "ASPEED 2400 System Control Unit";
468 asc->resets = ast2400_a0_resets;
469 asc->calc_hpll = aspeed_2400_scu_calc_hpll;
470 asc->apb_divider = 2;
e09cf363
JS		 471 asc->nr_regs = ASPEED_SCU_NR_REGS;
472 asc->ops = &aspeed_scu_ops;
9a937f6c
CLG		 473}
474
475static const TypeInfo aspeed_2400_scu_info = {
476 .name = TYPE_ASPEED_2400_SCU,
477 .parent = TYPE_ASPEED_SCU,
478 .instance_size = sizeof(AspeedSCUState),
479 .class_init = aspeed_2400_scu_class_init,
480};
481
482static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data)
483{
484 DeviceClass *dc = DEVICE_CLASS(klass);
485 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
486
487 dc->desc = "ASPEED 2500 System Control Unit";
488 asc->resets = ast2500_a1_resets;
489 asc->calc_hpll = aspeed_2500_scu_calc_hpll;
490 asc->apb_divider = 4;
e09cf363
JS		 491 asc->nr_regs = ASPEED_SCU_NR_REGS;
492 asc->ops = &aspeed_scu_ops;
9a937f6c
CLG		 493}
494
495static const TypeInfo aspeed_2500_scu_info = {
496 .name = TYPE_ASPEED_2500_SCU,
497 .parent = TYPE_ASPEED_SCU,
498 .instance_size = sizeof(AspeedSCUState),
499 .class_init = aspeed_2500_scu_class_init,
1c8a2388
AJ		 500};
501
e09cf363
JS		 502static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset,
503 unsigned size)
504{
505 AspeedSCUState *s = ASPEED_SCU(opaque);
506 int reg = TO_REG(offset);
507
508 if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
509 qemu_log_mask(LOG_GUEST_ERROR,
510 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
511 __func__, offset);
512 return 0;
513 }
514
515 switch (reg) {
516 case AST2600_HPLL_EXT:
517 case AST2600_EPLL_EXT:
518 case AST2600_MPLL_EXT:
519 /* PLLs are always "locked" */
520 return s->regs[reg] | BIT(31);
521 case AST2600_RNG_DATA:
522 /*
523 * On hardware, RNG_DATA works regardless of the state of the
524 * enable bit in RNG_CTRL
525 *
526 * TODO: Check this is true for ast2600
527 */
528 s->regs[AST2600_RNG_DATA] = aspeed_scu_get_random();
529 break;
530 }
531
532 return s->regs[reg];
533}
534
310b5bc6
JS		 535static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset,
536 uint64_t data64, unsigned size)
e09cf363
JS		 537{
538 AspeedSCUState *s = ASPEED_SCU(opaque);
539 int reg = TO_REG(offset);
310b5bc6
JS		 540 /* Truncate here so bitwise operations below behave as expected */
541 uint32_t data = data64;
e09cf363
JS		 542
543 if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
544 qemu_log_mask(LOG_GUEST_ERROR,
545 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
546 __func__, offset);
547 return;
548 }
549
550 if (reg > PROT_KEY && !s->regs[PROT_KEY]) {
551 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
552 }
553
554 trace_aspeed_scu_write(offset, size, data);
555
556 switch (reg) {
557 case AST2600_PROT_KEY:
558 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
559 return;
560 case AST2600_HW_STRAP1:
561 case AST2600_HW_STRAP2:
562 if (s->regs[reg + 2]) {
563 return;
564 }
565 /* fall through */
566 case AST2600_SYS_RST_CTRL:
567 case AST2600_SYS_RST_CTRL2:
310b5bc6
JS		 568 case AST2600_CLK_STOP_CTRL:
569 case AST2600_CLK_STOP_CTRL2:
e09cf363
JS		 570 /* W1S (Write 1 to set) registers */
571 s->regs[reg] |= data;
572 return;
573 case AST2600_SYS_RST_CTRL_CLR:
574 case AST2600_SYS_RST_CTRL2_CLR:
310b5bc6
JS		 575 case AST2600_CLK_STOP_CTRL_CLR:
576 case AST2600_CLK_STOP_CTRL2_CLR:
e09cf363
JS		 577 case AST2600_HW_STRAP1_CLR:
578 case AST2600_HW_STRAP2_CLR:
310b5bc6
JS		 579 /*
580 * W1C (Write 1 to clear) registers are offset by one address from
581 * the data register
582 */
583 s->regs[reg - 1] &= ~data;
e09cf363
JS		 584 return;
585
586 case AST2600_RNG_DATA:
587 case AST2600_SILICON_REV:
588 case AST2600_SILICON_REV2:
589 /* Add read only registers here */
590 qemu_log_mask(LOG_GUEST_ERROR,
591 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
592 __func__, offset);
593 return;
594 }
595
596 s->regs[reg] = data;
597}
598
599static const MemoryRegionOps aspeed_ast2600_scu_ops = {
600 .read = aspeed_ast2600_scu_read,
601 .write = aspeed_ast2600_scu_write,
602 .endianness = DEVICE_LITTLE_ENDIAN,
603 .valid.min_access_size = 4,
604 .valid.max_access_size = 4,
605 .valid.unaligned = false,
606};
607
608static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = {
609 [AST2600_SILICON_REV] = AST2600_SILICON_REV,
610 [AST2600_SILICON_REV2] = AST2600_SILICON_REV,
611 [AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100,
612 [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
613 [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B,
614 [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
1550d726 615 [AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */
e09cf363
JS		 616 [AST2600_HPLL_PARAM] = 0x1000405F,
617};
618
619static void aspeed_ast2600_scu_reset(DeviceState *dev)
620{
621 AspeedSCUState *s = ASPEED_SCU(dev);
622 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
623
624 memcpy(s->regs, asc->resets, asc->nr_regs * 4);
625
626 s->regs[AST2600_SILICON_REV] = s->silicon_rev;
627 s->regs[AST2600_SILICON_REV2] = s->silicon_rev;
628 s->regs[AST2600_HW_STRAP1] = s->hw_strap1;
629 s->regs[AST2600_HW_STRAP2] = s->hw_strap2;
630 s->regs[PROT_KEY] = s->hw_prot_key;
631}
632
633static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
634{
635 DeviceClass *dc = DEVICE_CLASS(klass);
636 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
637
638 dc->desc = "ASPEED 2600 System Control Unit";
639 dc->reset = aspeed_ast2600_scu_reset;
640 asc->resets = ast2600_a0_resets;
641 asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
642 asc->apb_divider = 4;
643 asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
644 asc->ops = &aspeed_ast2600_scu_ops;
645}
646
647static const TypeInfo aspeed_2600_scu_info = {
648 .name = TYPE_ASPEED_2600_SCU,
649 .parent = TYPE_ASPEED_SCU,
650 .instance_size = sizeof(AspeedSCUState),
651 .class_init = aspeed_2600_scu_class_init,
652};
653
1c8a2388
AJ		 654static void aspeed_scu_register_types(void)
655{
656 type_register_static(&aspeed_scu_info);
9a937f6c
CLG		 657 type_register_static(&aspeed_2400_scu_info);
658 type_register_static(&aspeed_2500_scu_info);
e09cf363 659 type_register_static(&aspeed_2600_scu_info);
1c8a2388
AJ		 660}
661
662type_init(aspeed_scu_register_types);
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