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hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation function
[mirror_qemu.git] / hw / misc / aspeed_scu.c
CommitLineData
1c8a2388
AJ		 1/*
2 * ASPEED System Control Unit
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12#include "qemu/osdep.h"
13#include "hw/misc/aspeed_scu.h"
14#include "hw/qdev-properties.h"
d6454270 15#include "migration/vmstate.h"
1c8a2388
AJ		 16#include "qapi/error.h"
17#include "qapi/visitor.h"
18#include "qemu/bitops.h"
aa4b04a0 19#include "qemu/log.h"
9d44cb5b 20#include "qemu/guest-random.h"
0b8fa32f 21#include "qemu/module.h"
1c8a2388
AJ		 22#include "trace.h"
23
24#define TO_REG(offset) ((offset) >> 2)
25
26#define PROT_KEY TO_REG(0x00)
27#define SYS_RST_CTRL TO_REG(0x04)
28#define CLK_SEL TO_REG(0x08)
29#define CLK_STOP_CTRL TO_REG(0x0C)
30#define FREQ_CNTR_CTRL TO_REG(0x10)
31#define FREQ_CNTR_EVAL TO_REG(0x14)
32#define IRQ_CTRL TO_REG(0x18)
33#define D2PLL_PARAM TO_REG(0x1C)
34#define MPLL_PARAM TO_REG(0x20)
35#define HPLL_PARAM TO_REG(0x24)
36#define FREQ_CNTR_RANGE TO_REG(0x28)
37#define MISC_CTRL1 TO_REG(0x2C)
38#define PCI_CTRL1 TO_REG(0x30)
39#define PCI_CTRL2 TO_REG(0x34)
40#define PCI_CTRL3 TO_REG(0x38)
41#define SYS_RST_STATUS TO_REG(0x3C)
42#define SOC_SCRATCH1 TO_REG(0x40)
43#define SOC_SCRATCH2 TO_REG(0x44)
44#define MAC_CLK_DELAY TO_REG(0x48)
45#define MISC_CTRL2 TO_REG(0x4C)
46#define VGA_SCRATCH1 TO_REG(0x50)
47#define VGA_SCRATCH2 TO_REG(0x54)
48#define VGA_SCRATCH3 TO_REG(0x58)
49#define VGA_SCRATCH4 TO_REG(0x5C)
50#define VGA_SCRATCH5 TO_REG(0x60)
51#define VGA_SCRATCH6 TO_REG(0x64)
52#define VGA_SCRATCH7 TO_REG(0x68)
53#define VGA_SCRATCH8 TO_REG(0x6C)
54#define HW_STRAP1 TO_REG(0x70)
55#define RNG_CTRL TO_REG(0x74)
56#define RNG_DATA TO_REG(0x78)
57#define SILICON_REV TO_REG(0x7C)
58#define PINMUX_CTRL1 TO_REG(0x80)
59#define PINMUX_CTRL2 TO_REG(0x84)
60#define PINMUX_CTRL3 TO_REG(0x88)
61#define PINMUX_CTRL4 TO_REG(0x8C)
62#define PINMUX_CTRL5 TO_REG(0x90)
63#define PINMUX_CTRL6 TO_REG(0x94)
64#define WDT_RST_CTRL TO_REG(0x9C)
65#define PINMUX_CTRL7 TO_REG(0xA0)
66#define PINMUX_CTRL8 TO_REG(0xA4)
67#define PINMUX_CTRL9 TO_REG(0xA8)
68#define WAKEUP_EN TO_REG(0xC0)
69#define WAKEUP_CTRL TO_REG(0xC4)
70#define HW_STRAP2 TO_REG(0xD0)
71#define FREE_CNTR4 TO_REG(0xE0)
72#define FREE_CNTR4_EXT TO_REG(0xE4)
73#define CPU2_CTRL TO_REG(0x100)
74#define CPU2_BASE_SEG1 TO_REG(0x104)
75#define CPU2_BASE_SEG2 TO_REG(0x108)
76#define CPU2_BASE_SEG3 TO_REG(0x10C)
77#define CPU2_BASE_SEG4 TO_REG(0x110)
78#define CPU2_BASE_SEG5 TO_REG(0x114)
79#define CPU2_CACHE_CTRL TO_REG(0x118)
7ffe647f
JS		 80#define CHIP_ID0 TO_REG(0x150)
81#define CHIP_ID1 TO_REG(0x154)
1c8a2388
AJ		 82#define UART_HPLL_CLK TO_REG(0x160)
83#define PCIE_CTRL TO_REG(0x180)
84#define BMC_MMIO_CTRL TO_REG(0x184)
85#define RELOC_DECODE_BASE1 TO_REG(0x188)
86#define RELOC_DECODE_BASE2 TO_REG(0x18C)
87#define MAILBOX_DECODE_BASE TO_REG(0x190)
88#define SRAM_DECODE_BASE1 TO_REG(0x194)
89#define SRAM_DECODE_BASE2 TO_REG(0x198)
90#define BMC_REV TO_REG(0x19C)
91#define BMC_DEV_ID TO_REG(0x1A4)
92
e09cf363
JS		 93#define AST2600_PROT_KEY TO_REG(0x00)
94#define AST2600_SILICON_REV TO_REG(0x04)
95#define AST2600_SILICON_REV2 TO_REG(0x14)
96#define AST2600_SYS_RST_CTRL TO_REG(0x40)
97#define AST2600_SYS_RST_CTRL_CLR TO_REG(0x44)
98#define AST2600_SYS_RST_CTRL2 TO_REG(0x50)
99#define AST2600_SYS_RST_CTRL2_CLR TO_REG(0x54)
100#define AST2600_CLK_STOP_CTRL TO_REG(0x80)
101#define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84)
102#define AST2600_CLK_STOP_CTRL2 TO_REG(0x90)
310b5bc6 103#define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94)
c5811bb3
JS		 104#define AST2600_DEBUG_CTRL TO_REG(0xC8)
105#define AST2600_DEBUG_CTRL2 TO_REG(0xD8)
1550d726 106#define AST2600_SDRAM_HANDSHAKE TO_REG(0x100)
e09cf363
JS		 107#define AST2600_HPLL_PARAM TO_REG(0x200)
108#define AST2600_HPLL_EXT TO_REG(0x204)
c5811bb3
JS		 109#define AST2600_APLL_PARAM TO_REG(0x210)
110#define AST2600_APLL_EXT TO_REG(0x214)
111#define AST2600_MPLL_PARAM TO_REG(0x220)
e09cf363 112#define AST2600_MPLL_EXT TO_REG(0x224)
c5811bb3 113#define AST2600_EPLL_PARAM TO_REG(0x240)
e09cf363 114#define AST2600_EPLL_EXT TO_REG(0x244)
c5811bb3
JS		 115#define AST2600_DPLL_PARAM TO_REG(0x260)
116#define AST2600_DPLL_EXT TO_REG(0x264)
e09cf363
JS		 117#define AST2600_CLK_SEL TO_REG(0x300)
118#define AST2600_CLK_SEL2 TO_REG(0x304)
c5811bb3
JS		 119#define AST2600_CLK_SEL3 TO_REG(0x308)
120#define AST2600_CLK_SEL4 TO_REG(0x310)
121#define AST2600_CLK_SEL5 TO_REG(0x314)
9dca4556
PD		 122#define AST2600_UARTCLK TO_REG(0x338)
123#define AST2600_HUARTCLK TO_REG(0x33C)
e09cf363
JS		 124#define AST2600_HW_STRAP1 TO_REG(0x500)
125#define AST2600_HW_STRAP1_CLR TO_REG(0x504)
126#define AST2600_HW_STRAP1_PROT TO_REG(0x508)
127#define AST2600_HW_STRAP2 TO_REG(0x510)
128#define AST2600_HW_STRAP2_CLR TO_REG(0x514)
129#define AST2600_HW_STRAP2_PROT TO_REG(0x518)
130#define AST2600_RNG_CTRL TO_REG(0x524)
131#define AST2600_RNG_DATA TO_REG(0x540)
7ffe647f
JS		 132#define AST2600_CHIP_ID0 TO_REG(0x5B0)
133#define AST2600_CHIP_ID1 TO_REG(0x5B4)
e09cf363
JS		 134
135#define AST2600_CLK TO_REG(0x40)
136
c491e152 137#define SCU_IO_REGION_SIZE 0x1000
1c8a2388 138
1c8a2388
AJ		 139static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
140 [SYS_RST_CTRL] = 0xFFCFFEDCU,
141 [CLK_SEL] = 0xF3F40000U,
142 [CLK_STOP_CTRL] = 0x19FC3E8BU,
143 [D2PLL_PARAM] = 0x00026108U,
144 [MPLL_PARAM] = 0x00030291U,
145 [HPLL_PARAM] = 0x00000291U,
146 [MISC_CTRL1] = 0x00000010U,
147 [PCI_CTRL1] = 0x20001A03U,
148 [PCI_CTRL2] = 0x20001A03U,
149 [PCI_CTRL3] = 0x04000030U,
150 [SYS_RST_STATUS] = 0x00000001U,
151 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
152 [MISC_CTRL2] = 0x00000023U,
153 [RNG_CTRL] = 0x0000000EU,
154 [PINMUX_CTRL2] = 0x0000F000U,
155 [PINMUX_CTRL3] = 0x01000000U,
156 [PINMUX_CTRL4] = 0x000000FFU,
157 [PINMUX_CTRL5] = 0x0000A000U,
158 [WDT_RST_CTRL] = 0x003FFFF3U,
159 [PINMUX_CTRL8] = 0xFFFF0000U,
160 [PINMUX_CTRL9] = 0x000FFFFFU,
161 [FREE_CNTR4] = 0x000000FFU,
162 [FREE_CNTR4_EXT] = 0x000000FFU,
163 [CPU2_BASE_SEG1] = 0x80000000U,
164 [CPU2_BASE_SEG4] = 0x1E600000U,
165 [CPU2_BASE_SEG5] = 0xC0000000U,
166 [UART_HPLL_CLK] = 0x00001903U,
167 [PCIE_CTRL] = 0x0000007BU,
168 [BMC_DEV_ID] = 0x00002402U
169};
170
365aff1e
CLG		 171/* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
172/* AST2500 revision A1 */
173
174static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
175 [SYS_RST_CTRL] = 0xFFCFFEDCU,
176 [CLK_SEL] = 0xF3F40000U,
177 [CLK_STOP_CTRL] = 0x19FC3E8BU,
178 [D2PLL_PARAM] = 0x00026108U,
179 [MPLL_PARAM] = 0x00030291U,
180 [HPLL_PARAM] = 0x93000400U,
181 [MISC_CTRL1] = 0x00000010U,
182 [PCI_CTRL1] = 0x20001A03U,
183 [PCI_CTRL2] = 0x20001A03U,
184 [PCI_CTRL3] = 0x04000030U,
185 [SYS_RST_STATUS] = 0x00000001U,
186 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
187 [MISC_CTRL2] = 0x00000023U,
188 [RNG_CTRL] = 0x0000000EU,
189 [PINMUX_CTRL2] = 0x0000F000U,
190 [PINMUX_CTRL3] = 0x03000000U,
191 [PINMUX_CTRL4] = 0x00000000U,
192 [PINMUX_CTRL5] = 0x0000A000U,
193 [WDT_RST_CTRL] = 0x023FFFF3U,
194 [PINMUX_CTRL8] = 0xFFFF0000U,
195 [PINMUX_CTRL9] = 0x000FFFFFU,
196 [FREE_CNTR4] = 0x000000FFU,
197 [FREE_CNTR4_EXT] = 0x000000FFU,
198 [CPU2_BASE_SEG1] = 0x80000000U,
199 [CPU2_BASE_SEG4] = 0x1E600000U,
200 [CPU2_BASE_SEG5] = 0xC0000000U,
7ffe647f
JS		 201 [CHIP_ID0] = 0x1234ABCDU,
202 [CHIP_ID1] = 0x88884444U,
365aff1e
CLG		 203 [UART_HPLL_CLK] = 0x00001903U,
204 [PCIE_CTRL] = 0x0000007BU,
205 [BMC_DEV_ID] = 0x00002402U
206};
207
acd9575e
JS		 208static uint32_t aspeed_scu_get_random(void)
209{
acd9575e 210 uint32_t num;
9d44cb5b 211 qemu_guest_getrandom_nofail(&num, sizeof(num));
acd9575e
JS		 212 return num;
213}
214
a8f07376 215uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s)
dd7f19a9
SL		 216{
217 return ASPEED_SCU_GET_CLASS(s)->get_apb(s);
218}
219
220static uint32_t aspeed_2400_scu_get_apb_freq(AspeedSCUState *s)
fda9aaa6 221{
9a937f6c 222 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
a8f07376 223 uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]);
fda9aaa6 224
a8f07376 225 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
9a937f6c 226 / asc->apb_divider;
fda9aaa6
CLG		 227}
228
dd7f19a9
SL		 229static uint32_t aspeed_2600_scu_get_apb_freq(AspeedSCUState *s)
230{
231 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
232 uint32_t hpll = asc->calc_hpll(s, s->regs[AST2600_HPLL_PARAM]);
233
234 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[AST2600_CLK_SEL]) + 1)
235 / asc->apb_divider;
236}
237
1c8a2388
AJ		 238static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
239{
240 AspeedSCUState *s = ASPEED_SCU(opaque);
241 int reg = TO_REG(offset);
242
e09cf363 243 if (reg >= ASPEED_SCU_NR_REGS) {
1c8a2388
AJ		 244 qemu_log_mask(LOG_GUEST_ERROR,
245 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
246 __func__, offset);
247 return 0;
248 }
249
250 switch (reg) {
acd9575e
JS		 251 case RNG_DATA:
252 /* On hardware, RNG_DATA works regardless of
253 * the state of the enable bit in RNG_CTRL
254 */
255 s->regs[RNG_DATA] = aspeed_scu_get_random();
256 break;
1c8a2388
AJ		 257 case WAKEUP_EN:
258 qemu_log_mask(LOG_GUEST_ERROR,
259 "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
260 __func__, offset);
261 break;
262 }
263
264 return s->regs[reg];
265}
266
c7e1f572
JS		 267static void aspeed_ast2400_scu_write(void *opaque, hwaddr offset,
268 uint64_t data, unsigned size)
269{
270 AspeedSCUState *s = ASPEED_SCU(opaque);
271 int reg = TO_REG(offset);
272
273 if (reg >= ASPEED_SCU_NR_REGS) {
274 qemu_log_mask(LOG_GUEST_ERROR,
275 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
276 __func__, offset);
277 return;
278 }
279
280 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
281 !s->regs[PROT_KEY]) {
282 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
283 }
284
285 trace_aspeed_scu_write(offset, size, data);
286
287 switch (reg) {
288 case PROT_KEY:
289 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
290 return;
291 case SILICON_REV:
292 case FREQ_CNTR_EVAL:
293 case VGA_SCRATCH1 ... VGA_SCRATCH8:
294 case RNG_DATA:
295 case FREE_CNTR4:
296 case FREE_CNTR4_EXT:
297 qemu_log_mask(LOG_GUEST_ERROR,
298 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
299 __func__, offset);
300 return;
301 }
302
303 s->regs[reg] = data;
304}
305
306static void aspeed_ast2500_scu_write(void *opaque, hwaddr offset,
307 uint64_t data, unsigned size)
1c8a2388
AJ		 308{
309 AspeedSCUState *s = ASPEED_SCU(opaque);
310 int reg = TO_REG(offset);
311
e09cf363 312 if (reg >= ASPEED_SCU_NR_REGS) {
1c8a2388
AJ		 313 qemu_log_mask(LOG_GUEST_ERROR,
314 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
315 __func__, offset);
316 return;
317 }
318
319 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
5c1d3a2b 320 !s->regs[PROT_KEY]) {
1c8a2388
AJ		 321 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
322 return;
323 }
324
325 trace_aspeed_scu_write(offset, size, data);
326
327 switch (reg) {
5c1d3a2b
HL		 328 case PROT_KEY:
329 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
330 return;
333b9c8a 331 case HW_STRAP1:
c7e1f572
JS		 332 s->regs[HW_STRAP1] |= data;
333 return;
333b9c8a 334 case SILICON_REV:
c7e1f572 335 s->regs[HW_STRAP1] &= ~data;
333b9c8a 336 return;
1c8a2388
AJ		 337 case FREQ_CNTR_EVAL:
338 case VGA_SCRATCH1 ... VGA_SCRATCH8:
339 case RNG_DATA:
1c8a2388
AJ		 340 case FREE_CNTR4:
341 case FREE_CNTR4_EXT:
7ffe647f
JS		 342 case CHIP_ID0:
343 case CHIP_ID1:
1c8a2388
AJ		 344 qemu_log_mask(LOG_GUEST_ERROR,
345 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
346 __func__, offset);
347 return;
348 }
349
350 s->regs[reg] = data;
351}
352
c7e1f572
JS		 353static const MemoryRegionOps aspeed_ast2400_scu_ops = {
354 .read = aspeed_scu_read,
355 .write = aspeed_ast2400_scu_write,
356 .endianness = DEVICE_LITTLE_ENDIAN,
740bc3a7
CLG		 357 .valid = {
358 .min_access_size = 1,
359 .max_access_size = 4,
360 },
c7e1f572
JS		 361};
362
363static const MemoryRegionOps aspeed_ast2500_scu_ops = {
1c8a2388 364 .read = aspeed_scu_read,
c7e1f572 365 .write = aspeed_ast2500_scu_write,
1c8a2388
AJ		 366 .endianness = DEVICE_LITTLE_ENDIAN,
367 .valid.min_access_size = 4,
368 .valid.max_access_size = 4,
369 .valid.unaligned = false,
370};
371
fda9aaa6
CLG		 372static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s)
373{
374 if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) {
375 return 25000000;
376 } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) {
377 return 48000000;
378 } else {
379 return 24000000;
380 }
381}
382
383/*
384 * Strapped frequencies for the AST2400 in MHz. They depend on the
385 * clkin frequency.
386 */
387static const uint32_t hpll_ast2400_freqs[][4] = {
388 { 384, 360, 336, 408 }, /* 24MHz or 48MHz */
389 { 400, 375, 350, 425 }, /* 25MHz */
390};
391
a8f07376 392static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
fda9aaa6 393{
fda9aaa6
CLG		 394 uint8_t freq_select;
395 bool clk_25m_in;
a8f07376 396 uint32_t clkin = aspeed_scu_get_clkin(s);
fda9aaa6
CLG		 397
398 if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
399 return 0;
400 }
401
402 if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) {
403 uint32_t multiplier = 1;
404
405 if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) {
406 uint32_t n = (hpll_reg >> 5) & 0x3f;
407 uint32_t od = (hpll_reg >> 4) & 0x1;
408 uint32_t d = hpll_reg & 0xf;
409
410 multiplier = (2 - od) * ((n + 2) / (d + 1));
411 }
412
a8f07376 413 return clkin * multiplier;
fda9aaa6
CLG		 414 }
415
416 /* HW strapping */
417 clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN);
418 freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1);
419
420 return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
421}
422
a8f07376 423static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
fda9aaa6 424{
fda9aaa6 425 uint32_t multiplier = 1;
a8f07376 426 uint32_t clkin = aspeed_scu_get_clkin(s);
fda9aaa6
CLG		 427
428 if (hpll_reg & SCU_H_PLL_OFF) {
429 return 0;
430 }
431
432 if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) {
433 uint32_t p = (hpll_reg >> 13) & 0x3f;
434 uint32_t m = (hpll_reg >> 5) & 0xff;
435 uint32_t n = hpll_reg & 0x1f;
436
437 multiplier = ((m + 1) / (n + 1)) / (p + 1);
438 }
439
a8f07376 440 return clkin * multiplier;
fda9aaa6
CLG		 441}
442
dd7f19a9
SL		 443static uint32_t aspeed_2600_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
444{
445 uint32_t multiplier = 1;
446 uint32_t clkin = aspeed_scu_get_clkin(s);
447
448 if (hpll_reg & SCU_AST2600_H_PLL_OFF) {
449 return 0;
450 }
451
452 if (!(hpll_reg & SCU_AST2600_H_PLL_BYPASS_EN)) {
453 uint32_t p = (hpll_reg >> 19) & 0xf;
454 uint32_t n = (hpll_reg >> 13) & 0x3f;
455 uint32_t m = hpll_reg & 0x1fff;
456
457 multiplier = ((m + 1) / (n + 1)) / (p + 1);
458 }
459
460 return clkin * multiplier;
461}
462
1c8a2388
AJ		 463static void aspeed_scu_reset(DeviceState *dev)
464{
465 AspeedSCUState *s = ASPEED_SCU(dev);
9a937f6c 466 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
1c8a2388 467
e09cf363 468 memcpy(s->regs, asc->resets, asc->nr_regs * 4);
1c8a2388
AJ		 469 s->regs[SILICON_REV] = s->silicon_rev;
470 s->regs[HW_STRAP1] = s->hw_strap1;
471 s->regs[HW_STRAP2] = s->hw_strap2;
b6e70d1d 472 s->regs[PROT_KEY] = s->hw_prot_key;
1c8a2388
AJ		 473}
474
365aff1e
CLG		 475static uint32_t aspeed_silicon_revs[] = {
476 AST2400_A0_SILICON_REV,
6efbac90 477 AST2400_A1_SILICON_REV,
365aff1e
CLG		 478 AST2500_A0_SILICON_REV,
479 AST2500_A1_SILICON_REV,
e09cf363 480 AST2600_A0_SILICON_REV,
7582591a 481 AST2600_A1_SILICON_REV,
c5811bb3
JS		 482 AST2600_A2_SILICON_REV,
483 AST2600_A3_SILICON_REV,
365aff1e 484};
1c8a2388 485
79a9f323 486bool is_supported_silicon_rev(uint32_t silicon_rev)
1c8a2388
AJ		 487{
488 int i;
489
490 for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
491 if (silicon_rev == aspeed_silicon_revs[i]) {
492 return true;
493 }
494 }
495
496 return false;
497}
498
499static void aspeed_scu_realize(DeviceState *dev, Error **errp)
500{
501 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
502 AspeedSCUState *s = ASPEED_SCU(dev);
e09cf363 503 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
1c8a2388
AJ		 504
505 if (!is_supported_silicon_rev(s->silicon_rev)) {
506 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
507 s->silicon_rev);
508 return;
509 }
510
e09cf363 511 memory_region_init_io(&s->iomem, OBJECT(s), asc->ops, s,
1c8a2388
AJ		 512 TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
513
514 sysbus_init_mmio(sbd, &s->iomem);
515}
516
517static const VMStateDescription vmstate_aspeed_scu = {
518 .name = "aspeed.scu",
e09cf363
JS		 519 .version_id = 2,
520 .minimum_version_id = 2,
1c8a2388 521 .fields = (VMStateField[]) {
e09cf363 522 VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS),
1c8a2388
AJ		 523 VMSTATE_END_OF_LIST()
524 }
525};
526
527static Property aspeed_scu_properties[] = {
528 DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
529 DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
2ddfa281 530 DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
b6e70d1d 531 DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
1c8a2388
AJ		 532 DEFINE_PROP_END_OF_LIST(),
533};
534
535static void aspeed_scu_class_init(ObjectClass *klass, void *data)
536{
537 DeviceClass *dc = DEVICE_CLASS(klass);
538 dc->realize = aspeed_scu_realize;
539 dc->reset = aspeed_scu_reset;
540 dc->desc = "ASPEED System Control Unit";
541 dc->vmsd = &vmstate_aspeed_scu;
4f67d30b 542 device_class_set_props(dc, aspeed_scu_properties);
1c8a2388
AJ		 543}
544
545static const TypeInfo aspeed_scu_info = {
546 .name = TYPE_ASPEED_SCU,
547 .parent = TYPE_SYS_BUS_DEVICE,
548 .instance_size = sizeof(AspeedSCUState),
549 .class_init = aspeed_scu_class_init,
9a937f6c
CLG		 550 .class_size = sizeof(AspeedSCUClass),
551 .abstract = true,
552};
553
554static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data)
555{
556 DeviceClass *dc = DEVICE_CLASS(klass);
557 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
558
559 dc->desc = "ASPEED 2400 System Control Unit";
560 asc->resets = ast2400_a0_resets;
561 asc->calc_hpll = aspeed_2400_scu_calc_hpll;
dd7f19a9 562 asc->get_apb = aspeed_2400_scu_get_apb_freq;
9a937f6c 563 asc->apb_divider = 2;
e09cf363 564 asc->nr_regs = ASPEED_SCU_NR_REGS;
c7e1f572 565 asc->ops = &aspeed_ast2400_scu_ops;
9a937f6c
CLG		 566}
567
568static const TypeInfo aspeed_2400_scu_info = {
569 .name = TYPE_ASPEED_2400_SCU,
570 .parent = TYPE_ASPEED_SCU,
571 .instance_size = sizeof(AspeedSCUState),
572 .class_init = aspeed_2400_scu_class_init,
573};
574
575static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data)
576{
577 DeviceClass *dc = DEVICE_CLASS(klass);
578 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
579
580 dc->desc = "ASPEED 2500 System Control Unit";
581 asc->resets = ast2500_a1_resets;
582 asc->calc_hpll = aspeed_2500_scu_calc_hpll;
dd7f19a9 583 asc->get_apb = aspeed_2400_scu_get_apb_freq;
9a937f6c 584 asc->apb_divider = 4;
e09cf363 585 asc->nr_regs = ASPEED_SCU_NR_REGS;
c7e1f572 586 asc->ops = &aspeed_ast2500_scu_ops;
9a937f6c
CLG		 587}
588
589static const TypeInfo aspeed_2500_scu_info = {
590 .name = TYPE_ASPEED_2500_SCU,
591 .parent = TYPE_ASPEED_SCU,
592 .instance_size = sizeof(AspeedSCUState),
593 .class_init = aspeed_2500_scu_class_init,
1c8a2388
AJ		 594};
595
e09cf363
JS		 596static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset,
597 unsigned size)
598{
599 AspeedSCUState *s = ASPEED_SCU(opaque);
600 int reg = TO_REG(offset);
601
602 if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
603 qemu_log_mask(LOG_GUEST_ERROR,
604 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
605 __func__, offset);
606 return 0;
607 }
608
609 switch (reg) {
610 case AST2600_HPLL_EXT:
611 case AST2600_EPLL_EXT:
612 case AST2600_MPLL_EXT:
613 /* PLLs are always "locked" */
614 return s->regs[reg] | BIT(31);
615 case AST2600_RNG_DATA:
616 /*
617 * On hardware, RNG_DATA works regardless of the state of the
618 * enable bit in RNG_CTRL
619 *
620 * TODO: Check this is true for ast2600
621 */
622 s->regs[AST2600_RNG_DATA] = aspeed_scu_get_random();
623 break;
624 }
625
626 return s->regs[reg];
627}
628
310b5bc6
JS		 629static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset,
630 uint64_t data64, unsigned size)
e09cf363
JS		 631{
632 AspeedSCUState *s = ASPEED_SCU(opaque);
633 int reg = TO_REG(offset);
310b5bc6
JS		 634 /* Truncate here so bitwise operations below behave as expected */
635 uint32_t data = data64;
e09cf363
JS		 636
637 if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
638 qemu_log_mask(LOG_GUEST_ERROR,
639 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
640 __func__, offset);
641 return;
642 }
643
644 if (reg > PROT_KEY && !s->regs[PROT_KEY]) {
645 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
646 }
647
648 trace_aspeed_scu_write(offset, size, data);
649
650 switch (reg) {
651 case AST2600_PROT_KEY:
652 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
653 return;
654 case AST2600_HW_STRAP1:
655 case AST2600_HW_STRAP2:
656 if (s->regs[reg + 2]) {
657 return;
658 }
659 /* fall through */
660 case AST2600_SYS_RST_CTRL:
661 case AST2600_SYS_RST_CTRL2:
310b5bc6
JS		 662 case AST2600_CLK_STOP_CTRL:
663 case AST2600_CLK_STOP_CTRL2:
e09cf363
JS		 664 /* W1S (Write 1 to set) registers */
665 s->regs[reg] |= data;
666 return;
667 case AST2600_SYS_RST_CTRL_CLR:
668 case AST2600_SYS_RST_CTRL2_CLR:
310b5bc6
JS		 669 case AST2600_CLK_STOP_CTRL_CLR:
670 case AST2600_CLK_STOP_CTRL2_CLR:
e09cf363
JS		 671 case AST2600_HW_STRAP1_CLR:
672 case AST2600_HW_STRAP2_CLR:
310b5bc6
JS		 673 /*
674 * W1C (Write 1 to clear) registers are offset by one address from
675 * the data register
676 */
677 s->regs[reg - 1] &= ~data;
e09cf363
JS		 678 return;
679
680 case AST2600_RNG_DATA:
681 case AST2600_SILICON_REV:
682 case AST2600_SILICON_REV2:
7ffe647f
JS		 683 case AST2600_CHIP_ID0:
684 case AST2600_CHIP_ID1:
e09cf363
JS		 685 /* Add read only registers here */
686 qemu_log_mask(LOG_GUEST_ERROR,
687 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
688 __func__, offset);
689 return;
690 }
691
692 s->regs[reg] = data;
693}
694
695static const MemoryRegionOps aspeed_ast2600_scu_ops = {
696 .read = aspeed_ast2600_scu_read,
697 .write = aspeed_ast2600_scu_write,
698 .endianness = DEVICE_LITTLE_ENDIAN,
699 .valid.min_access_size = 4,
700 .valid.max_access_size = 4,
701 .valid.unaligned = false,
702};
703
c5811bb3 704static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = {
7582591a 705 [AST2600_SYS_RST_CTRL] = 0xF7C3FED8,
c5811bb3 706 [AST2600_SYS_RST_CTRL2] = 0x0DFFFFFC,
7582591a 707 [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
e09cf363 708 [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
c5811bb3
JS		 709 [AST2600_DEBUG_CTRL] = 0x00000FFF,
710 [AST2600_DEBUG_CTRL2] = 0x000000FF,
14c17954 711 [AST2600_SDRAM_HANDSHAKE] = 0x00000000,
c5811bb3
JS		 712 [AST2600_HPLL_PARAM] = 0x1000408F,
713 [AST2600_APLL_PARAM] = 0x1000405F,
714 [AST2600_MPLL_PARAM] = 0x1008405F,
715 [AST2600_EPLL_PARAM] = 0x1004077F,
716 [AST2600_DPLL_PARAM] = 0x1078405F,
717 [AST2600_CLK_SEL] = 0xF3940000,
718 [AST2600_CLK_SEL2] = 0x00700000,
719 [AST2600_CLK_SEL3] = 0x00000000,
720 [AST2600_CLK_SEL4] = 0xF3F40000,
721 [AST2600_CLK_SEL5] = 0x30000000,
9dca4556
PD		 722 [AST2600_UARTCLK] = 0x00014506,
723 [AST2600_HUARTCLK] = 0x000145C0,
7ffe647f
JS		 724 [AST2600_CHIP_ID0] = 0x1234ABCD,
725 [AST2600_CHIP_ID1] = 0x88884444,
e09cf363
JS		 726};
727
728static void aspeed_ast2600_scu_reset(DeviceState *dev)
729{
730 AspeedSCUState *s = ASPEED_SCU(dev);
731 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
732
733 memcpy(s->regs, asc->resets, asc->nr_regs * 4);
734
204dab83
JS		 735 /*
736 * A0 reports A0 in _REV, but subsequent revisions report A1 regardless
737 * of actual revision. QEMU and Linux only support A1 onwards so this is
738 * sufficient.
739 */
c5811bb3 740 s->regs[AST2600_SILICON_REV] = AST2600_A3_SILICON_REV;
e09cf363
JS		 741 s->regs[AST2600_SILICON_REV2] = s->silicon_rev;
742 s->regs[AST2600_HW_STRAP1] = s->hw_strap1;
743 s->regs[AST2600_HW_STRAP2] = s->hw_strap2;
744 s->regs[PROT_KEY] = s->hw_prot_key;
745}
746
747static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
748{
749 DeviceClass *dc = DEVICE_CLASS(klass);
750 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
751
752 dc->desc = "ASPEED 2600 System Control Unit";
753 dc->reset = aspeed_ast2600_scu_reset;
c5811bb3 754 asc->resets = ast2600_a3_resets;
dd7f19a9
SL		 755 asc->calc_hpll = aspeed_2600_scu_calc_hpll;
756 asc->get_apb = aspeed_2600_scu_get_apb_freq;
e09cf363
JS		 757 asc->apb_divider = 4;
758 asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
759 asc->ops = &aspeed_ast2600_scu_ops;
760}
761
762static const TypeInfo aspeed_2600_scu_info = {
763 .name = TYPE_ASPEED_2600_SCU,
764 .parent = TYPE_ASPEED_SCU,
765 .instance_size = sizeof(AspeedSCUState),
766 .class_init = aspeed_2600_scu_class_init,
767};
768
1c8a2388
AJ		 769static void aspeed_scu_register_types(void)
770{
771 type_register_static(&aspeed_scu_info);
9a937f6c
CLG		 772 type_register_static(&aspeed_2400_scu_info);
773 type_register_static(&aspeed_2500_scu_info);
e09cf363 774 type_register_static(&aspeed_2600_scu_info);
1c8a2388
AJ		 775}
776
777type_init(aspeed_scu_register_types);
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