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[mirror_qemu.git] / hw / misc / aspeed_sdmc.c
CommitLineData
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1/*
2 * ASPEED SDRAM Memory Controller
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10#include "qemu/osdep.h"
11#include "qemu/log.h"
0b8fa32f 12#include "qemu/module.h"
b2fd4545 13#include "qemu/error-report.h"
c2da8a8b 14#include "hw/misc/aspeed_sdmc.h"
c2da8a8b 15#include "hw/qdev-properties.h"
d6454270 16#include "migration/vmstate.h"
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17#include "qapi/error.h"
18#include "trace.h"
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19#include "qemu/units.h"
20#include "qemu/cutils.h"
21#include "qapi/visitor.h"
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22
23/* Protection Key Register */
24#define R_PROT (0x00 / 4)
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25#define PROT_UNLOCKED 0x01
26#define PROT_HARDLOCKED 0x10 /* AST2600 */
27#define PROT_SOFTLOCKED 0x00
28
c2da8a8b 29#define PROT_KEY_UNLOCK 0xFC600309
f4ab4f8e 30#define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */
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31
32/* Configuration Register */
33#define R_CONF (0x04 / 4)
34
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35/* Interrupt control/status */
36#define R_ISR (0x50 / 4)
37
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38/* Control/Status Register #1 (ast2500) */
39#define R_STATUS1 (0x60 / 4)
40#define PHY_BUSY_STATE BIT(0)
1550d726 41#define PHY_PLL_LOCK_STATUS BIT(4)
33883ce8 42
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43/* Reserved */
44#define R_MCR6C (0x6c / 4)
45
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46#define R_ECC_TEST_CTRL (0x70 / 4)
47#define ECC_TEST_FINISHED BIT(12)
48#define ECC_TEST_FAIL BIT(13)
49
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50#define R_TEST_START_LEN (0x74 / 4)
51#define R_TEST_FAIL_DQ (0x78 / 4)
52#define R_TEST_INIT_VAL (0x7c / 4)
53#define R_DRAM_SW (0x88 / 4)
54#define R_DRAM_TIME (0x8c / 4)
55#define R_ECC_ERR_INJECT (0xb4 / 4)
56
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57/*
58 * Configuration register Ox4 (for Aspeed AST2400 SOC)
59 *
60 * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
61 * what we care about right now as it is checked by U-Boot to
62 * determine the RAM size.
63 */
64
65#define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */
66#define ASPEED_SDMC_AST2300_COMPAT (1 << 10)
67#define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9)
68#define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8)
69#define ASPEED_SDMC_ECC_ENABLE (1 << 7)
70#define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */
71#define ASPEED_SDMC_DRAM_BANK (1 << 5)
72#define ASPEED_SDMC_DRAM_BURST (1 << 4)
73#define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */
74#define ASPEED_SDMC_VGA_8MB 0x0
75#define ASPEED_SDMC_VGA_16MB 0x1
76#define ASPEED_SDMC_VGA_32MB 0x2
77#define ASPEED_SDMC_VGA_64MB 0x3
78#define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3)
79#define ASPEED_SDMC_DRAM_64MB 0x0
80#define ASPEED_SDMC_DRAM_128MB 0x1
81#define ASPEED_SDMC_DRAM_256MB 0x2
82#define ASPEED_SDMC_DRAM_512MB 0x3
83
84#define ASPEED_SDMC_READONLY_MASK \
85 (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
86 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
87/*
88 * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
89 *
90 * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
91 * should be set to 1 for the AST2500 SOC.
92 */
93#define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */
94#define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20)
95#define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */
96#define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */
97#define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13)
98#define ASPEED_SDMC_CACHE_INITIAL (1 << 12)
99#define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11)
100#define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */
101#define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */
102
103/* DRAM size definitions differs */
104#define ASPEED_SDMC_AST2500_128MB 0x0
105#define ASPEED_SDMC_AST2500_256MB 0x1
106#define ASPEED_SDMC_AST2500_512MB 0x2
107#define ASPEED_SDMC_AST2500_1024MB 0x3
108
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109#define ASPEED_SDMC_AST2600_256MB 0x0
110#define ASPEED_SDMC_AST2600_512MB 0x1
111#define ASPEED_SDMC_AST2600_1024MB 0x2
112#define ASPEED_SDMC_AST2600_2048MB 0x3
113
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114#define ASPEED_SDMC_AST2500_READONLY_MASK \
115 (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \
116 ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
117 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
118
119static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
120{
121 AspeedSDMCState *s = ASPEED_SDMC(opaque);
122
123 addr >>= 2;
124
125 if (addr >= ARRAY_SIZE(s->regs)) {
126 qemu_log_mask(LOG_GUEST_ERROR,
127 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
14c17954 128 __func__, addr * 4);
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129 return 0;
130 }
131
3671342a 132 trace_aspeed_sdmc_read(addr, s->regs[addr]);
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133 return s->regs[addr];
134}
135
136static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
137 unsigned int size)
138{
139 AspeedSDMCState *s = ASPEED_SDMC(opaque);
8e00d1a9 140 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
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141
142 addr >>= 2;
143
144 if (addr >= ARRAY_SIZE(s->regs)) {
145 qemu_log_mask(LOG_GUEST_ERROR,
146 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
147 __func__, addr);
148 return;
149 }
150
3671342a 151 trace_aspeed_sdmc_write(addr, data);
8e00d1a9 152 asc->write(s, addr, data);
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153}
154
155static const MemoryRegionOps aspeed_sdmc_ops = {
156 .read = aspeed_sdmc_read,
157 .write = aspeed_sdmc_write,
158 .endianness = DEVICE_LITTLE_ENDIAN,
159 .valid.min_access_size = 4,
160 .valid.max_access_size = 4,
161};
162
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163static void aspeed_sdmc_reset(DeviceState *dev)
164{
165 AspeedSDMCState *s = ASPEED_SDMC(dev);
8e00d1a9 166 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
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167
168 memset(s->regs, 0, sizeof(s->regs));
169
170 /* Set ram size bit and defaults values */
8e00d1a9 171 s->regs[R_CONF] = asc->compute_conf(s, 0);
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172
173 /*
174 * PHY status:
175 * - set phy status ok (set bit 1)
176 * - initial PVT calibration ok (clear bit 3)
177 * - runtime calibration ok (clear bit 5)
178 */
179 s->regs[0x100] = BIT(1);
180
181 /* PHY eye window: set all as passing */
182 s->regs[0x100 | (0x68 / 4)] = 0xff;
183 s->regs[0x100 | (0x7c / 4)] = 0xff;
184 s->regs[0x100 | (0x50 / 4)] = 0xfffffff;
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185}
186
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187static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name,
188 void *opaque, Error **errp)
189{
190 AspeedSDMCState *s = ASPEED_SDMC(obj);
191 int64_t value = s->ram_size;
192
193 visit_type_int(v, name, &value, errp);
194}
195
196static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name,
197 void *opaque, Error **errp)
198{
199 int i;
200 char *sz;
201 int64_t value;
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202 AspeedSDMCState *s = ASPEED_SDMC(obj);
203 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
204
668f62ec 205 if (!visit_type_int(v, name, &value, errp)) {
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206 return;
207 }
208
209 for (i = 0; asc->valid_ram_sizes[i]; i++) {
210 if (value == asc->valid_ram_sizes[i]) {
211 s->ram_size = value;
212 return;
213 }
214 }
215
216 sz = size_to_str(value);
dcfe4805 217 error_setg(errp, "Invalid RAM size %s", sz);
533eb415 218 g_free(sz);
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219}
220
221static void aspeed_sdmc_initfn(Object *obj)
222{
223 object_property_add(obj, "ram-size", "int",
224 aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size,
d2623129 225 NULL, NULL);
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226}
227
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228static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
229{
230 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
231 AspeedSDMCState *s = ASPEED_SDMC(dev);
8e00d1a9 232 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
c2da8a8b 233
ca05a240 234 assert(asc->max_ram_size < 4 * GiB); /* 32-bit address bus */
8e00d1a9 235 s->max_ram_size = asc->max_ram_size;
3755f9e3 236
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237 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
238 TYPE_ASPEED_SDMC, 0x1000);
239 sysbus_init_mmio(sbd, &s->iomem);
240}
241
242static const VMStateDescription vmstate_aspeed_sdmc = {
243 .name = "aspeed.sdmc",
244 .version_id = 1,
245 .minimum_version_id = 1,
e4ea952f 246 .fields = (const VMStateField[]) {
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247 VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
248 VMSTATE_END_OF_LIST()
249 }
250};
251
252static Property aspeed_sdmc_properties[] = {
ebe31c0a 253 DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
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254 DEFINE_PROP_END_OF_LIST(),
255};
256
257static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
258{
259 DeviceClass *dc = DEVICE_CLASS(klass);
260 dc->realize = aspeed_sdmc_realize;
261 dc->reset = aspeed_sdmc_reset;
262 dc->desc = "ASPEED SDRAM Memory Controller";
263 dc->vmsd = &vmstate_aspeed_sdmc;
4f67d30b 264 device_class_set_props(dc, aspeed_sdmc_properties);
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265}
266
267static const TypeInfo aspeed_sdmc_info = {
268 .name = TYPE_ASPEED_SDMC,
269 .parent = TYPE_SYS_BUS_DEVICE,
270 .instance_size = sizeof(AspeedSDMCState),
533eb415 271 .instance_init = aspeed_sdmc_initfn,
c2da8a8b 272 .class_init = aspeed_sdmc_class_init,
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273 .class_size = sizeof(AspeedSDMCClass),
274 .abstract = true,
275};
276
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277static int aspeed_sdmc_get_ram_bits(AspeedSDMCState *s)
278{
279 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
280 int i;
281
282 /*
283 * The bitfield value encoding the RAM size is the index of the
284 * possible RAM size array
285 */
286 for (i = 0; asc->valid_ram_sizes[i]; i++) {
287 if (s->ram_size == asc->valid_ram_sizes[i]) {
288 return i;
289 }
290 }
291
292 /*
293 * Invalid RAM sizes should have been excluded when setting the
294 * SoC RAM size.
295 */
296 g_assert_not_reached();
297}
298
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299static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
300{
301 uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT |
9951133e 302 ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s));
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303
304 /* Make sure readonly bits are kept */
305 data &= ~ASPEED_SDMC_READONLY_MASK;
306
307 return data | fixed_conf;
308}
309
310static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
311 uint32_t data)
312{
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313 if (reg == R_PROT) {
314 s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
315 return;
316 }
317
318 if (!s->regs[R_PROT]) {
319 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
320 return;
321 }
322
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323 switch (reg) {
324 case R_CONF:
325 data = aspeed_2400_sdmc_compute_conf(s, data);
326 break;
327 default:
328 break;
329 }
330
331 s->regs[reg] = data;
332}
333
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334static const uint64_t
335aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0};
336
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337static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
338{
339 DeviceClass *dc = DEVICE_CLASS(klass);
340 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
341
342 dc->desc = "ASPEED 2400 SDRAM Memory Controller";
ca05a240 343 asc->max_ram_size = 512 * MiB;
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344 asc->compute_conf = aspeed_2400_sdmc_compute_conf;
345 asc->write = aspeed_2400_sdmc_write;
533eb415 346 asc->valid_ram_sizes = aspeed_2400_ram_sizes;
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347}
348
349static const TypeInfo aspeed_2400_sdmc_info = {
350 .name = TYPE_ASPEED_2400_SDMC,
351 .parent = TYPE_ASPEED_SDMC,
352 .class_init = aspeed_2400_sdmc_class_init,
353};
354
355static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
356{
357 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
358 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
359 ASPEED_SDMC_CACHE_INITIAL_DONE |
9951133e 360 ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s));
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361
362 /* Make sure readonly bits are kept */
363 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
364
365 return data | fixed_conf;
366}
367
368static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
369 uint32_t data)
370{
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371 if (reg == R_PROT) {
372 s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
373 return;
374 }
375
376 if (!s->regs[R_PROT]) {
377 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
378 return;
379 }
380
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381 switch (reg) {
382 case R_CONF:
383 data = aspeed_2500_sdmc_compute_conf(s, data);
384 break;
385 case R_STATUS1:
386 /* Will never return 'busy' */
387 data &= ~PHY_BUSY_STATE;
388 break;
389 case R_ECC_TEST_CTRL:
390 /* Always done, always happy */
391 data |= ECC_TEST_FINISHED;
392 data &= ~ECC_TEST_FAIL;
393 break;
394 default:
395 break;
396 }
397
398 s->regs[reg] = data;
399}
400
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401static const uint64_t
402aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0};
403
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404static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
405{
406 DeviceClass *dc = DEVICE_CLASS(klass);
407 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
408
409 dc->desc = "ASPEED 2500 SDRAM Memory Controller";
ca05a240 410 asc->max_ram_size = 1 * GiB;
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411 asc->compute_conf = aspeed_2500_sdmc_compute_conf;
412 asc->write = aspeed_2500_sdmc_write;
533eb415 413 asc->valid_ram_sizes = aspeed_2500_ram_sizes;
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414}
415
416static const TypeInfo aspeed_2500_sdmc_info = {
417 .name = TYPE_ASPEED_2500_SDMC,
418 .parent = TYPE_ASPEED_SDMC,
419 .class_init = aspeed_2500_sdmc_class_init,
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420};
421
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422static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
423{
424 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) |
425 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
9951133e 426 ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s));
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427
428 /* Make sure readonly bits are kept (use ast2500 mask) */
429 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
430
431 return data | fixed_conf;
432}
433
434static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
435 uint32_t data)
436{
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437 /* Unprotected registers */
438 switch (reg) {
439 case R_ISR:
440 case R_MCR6C:
441 case R_TEST_START_LEN:
442 case R_TEST_FAIL_DQ:
443 case R_TEST_INIT_VAL:
444 case R_DRAM_SW:
445 case R_DRAM_TIME:
446 case R_ECC_ERR_INJECT:
447 s->regs[reg] = data;
448 return;
449 }
450
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451 if (s->regs[R_PROT] == PROT_HARDLOCKED) {
452 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
453 __func__);
454 return;
455 }
456
457 if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) {
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458 qemu_log_mask(LOG_GUEST_ERROR,
459 "%s: SDMC is locked! (write to MCR%02x blocked)\n",
460 __func__, reg * 4);
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461 return;
462 }
463
1550d726 464 switch (reg) {
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465 case R_PROT:
466 if (data == PROT_KEY_UNLOCK) {
467 data = PROT_UNLOCKED;
468 } else if (data == PROT_KEY_HARDLOCK) {
469 data = PROT_HARDLOCKED;
470 } else {
471 data = PROT_SOFTLOCKED;
472 }
473 break;
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474 case R_CONF:
475 data = aspeed_2600_sdmc_compute_conf(s, data);
476 break;
477 case R_STATUS1:
478 /* Will never return 'busy'. 'lock status' is always set */
479 data &= ~PHY_BUSY_STATE;
480 data |= PHY_PLL_LOCK_STATUS;
481 break;
482 case R_ECC_TEST_CTRL:
483 /* Always done, always happy */
484 data |= ECC_TEST_FINISHED;
485 data &= ~ECC_TEST_FAIL;
486 break;
487 default:
488 break;
489 }
490
491 s->regs[reg] = data;
492}
493
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494static const uint64_t
495aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0};
496
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497static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data)
498{
499 DeviceClass *dc = DEVICE_CLASS(klass);
500 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
501
502 dc->desc = "ASPEED 2600 SDRAM Memory Controller";
ca05a240 503 asc->max_ram_size = 2 * GiB;
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504 asc->compute_conf = aspeed_2600_sdmc_compute_conf;
505 asc->write = aspeed_2600_sdmc_write;
533eb415 506 asc->valid_ram_sizes = aspeed_2600_ram_sizes;
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507}
508
509static const TypeInfo aspeed_2600_sdmc_info = {
510 .name = TYPE_ASPEED_2600_SDMC,
511 .parent = TYPE_ASPEED_SDMC,
512 .class_init = aspeed_2600_sdmc_class_init,
513};
514
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515static void aspeed_sdmc_register_types(void)
516{
517 type_register_static(&aspeed_sdmc_info);
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518 type_register_static(&aspeed_2400_sdmc_info);
519 type_register_static(&aspeed_2500_sdmc_info);
1550d726 520 type_register_static(&aspeed_2600_sdmc_info);
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521}
522
523type_init(aspeed_sdmc_register_types);