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Commit | Line | Data |
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c2da8a8b CLG |
1 | /* |
2 | * ASPEED SDRAM Memory Controller | |
3 | * | |
4 | * Copyright (C) 2016 IBM Corp. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See | |
7 | * the COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
11 | #include "qemu/log.h" | |
0b8fa32f | 12 | #include "qemu/module.h" |
b2fd4545 | 13 | #include "qemu/error-report.h" |
c2da8a8b CLG |
14 | #include "hw/misc/aspeed_sdmc.h" |
15 | #include "hw/misc/aspeed_scu.h" | |
16 | #include "hw/qdev-properties.h" | |
d6454270 | 17 | #include "migration/vmstate.h" |
c2da8a8b CLG |
18 | #include "qapi/error.h" |
19 | #include "trace.h" | |
533eb415 IM |
20 | #include "qemu/units.h" |
21 | #include "qemu/cutils.h" | |
22 | #include "qapi/visitor.h" | |
c2da8a8b CLG |
23 | |
24 | /* Protection Key Register */ | |
25 | #define R_PROT (0x00 / 4) | |
f4ab4f8e JS |
26 | #define PROT_UNLOCKED 0x01 |
27 | #define PROT_HARDLOCKED 0x10 /* AST2600 */ | |
28 | #define PROT_SOFTLOCKED 0x00 | |
29 | ||
c2da8a8b | 30 | #define PROT_KEY_UNLOCK 0xFC600309 |
f4ab4f8e | 31 | #define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */ |
c2da8a8b CLG |
32 | |
33 | /* Configuration Register */ | |
34 | #define R_CONF (0x04 / 4) | |
35 | ||
33883ce8 JS |
36 | /* Control/Status Register #1 (ast2500) */ |
37 | #define R_STATUS1 (0x60 / 4) | |
38 | #define PHY_BUSY_STATE BIT(0) | |
1550d726 | 39 | #define PHY_PLL_LOCK_STATUS BIT(4) |
33883ce8 | 40 | |
a7b4569a JS |
41 | #define R_ECC_TEST_CTRL (0x70 / 4) |
42 | #define ECC_TEST_FINISHED BIT(12) | |
43 | #define ECC_TEST_FAIL BIT(13) | |
44 | ||
c2da8a8b CLG |
45 | /* |
46 | * Configuration register Ox4 (for Aspeed AST2400 SOC) | |
47 | * | |
48 | * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is | |
49 | * what we care about right now as it is checked by U-Boot to | |
50 | * determine the RAM size. | |
51 | */ | |
52 | ||
53 | #define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */ | |
54 | #define ASPEED_SDMC_AST2300_COMPAT (1 << 10) | |
55 | #define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9) | |
56 | #define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8) | |
57 | #define ASPEED_SDMC_ECC_ENABLE (1 << 7) | |
58 | #define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */ | |
59 | #define ASPEED_SDMC_DRAM_BANK (1 << 5) | |
60 | #define ASPEED_SDMC_DRAM_BURST (1 << 4) | |
61 | #define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */ | |
62 | #define ASPEED_SDMC_VGA_8MB 0x0 | |
63 | #define ASPEED_SDMC_VGA_16MB 0x1 | |
64 | #define ASPEED_SDMC_VGA_32MB 0x2 | |
65 | #define ASPEED_SDMC_VGA_64MB 0x3 | |
66 | #define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3) | |
67 | #define ASPEED_SDMC_DRAM_64MB 0x0 | |
68 | #define ASPEED_SDMC_DRAM_128MB 0x1 | |
69 | #define ASPEED_SDMC_DRAM_256MB 0x2 | |
70 | #define ASPEED_SDMC_DRAM_512MB 0x3 | |
71 | ||
72 | #define ASPEED_SDMC_READONLY_MASK \ | |
73 | (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ | |
74 | ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB)) | |
75 | /* | |
76 | * Configuration register Ox4 (for Aspeed AST2500 SOC and higher) | |
77 | * | |
78 | * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION | |
79 | * should be set to 1 for the AST2500 SOC. | |
80 | */ | |
81 | #define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */ | |
82 | #define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20) | |
83 | #define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */ | |
84 | #define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */ | |
85 | #define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13) | |
86 | #define ASPEED_SDMC_CACHE_INITIAL (1 << 12) | |
87 | #define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11) | |
88 | #define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */ | |
89 | #define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */ | |
90 | ||
91 | /* DRAM size definitions differs */ | |
92 | #define ASPEED_SDMC_AST2500_128MB 0x0 | |
93 | #define ASPEED_SDMC_AST2500_256MB 0x1 | |
94 | #define ASPEED_SDMC_AST2500_512MB 0x2 | |
95 | #define ASPEED_SDMC_AST2500_1024MB 0x3 | |
96 | ||
1550d726 JS |
97 | #define ASPEED_SDMC_AST2600_256MB 0x0 |
98 | #define ASPEED_SDMC_AST2600_512MB 0x1 | |
99 | #define ASPEED_SDMC_AST2600_1024MB 0x2 | |
100 | #define ASPEED_SDMC_AST2600_2048MB 0x3 | |
101 | ||
c2da8a8b CLG |
102 | #define ASPEED_SDMC_AST2500_READONLY_MASK \ |
103 | (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \ | |
104 | ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ | |
105 | ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB)) | |
106 | ||
107 | static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size) | |
108 | { | |
109 | AspeedSDMCState *s = ASPEED_SDMC(opaque); | |
110 | ||
111 | addr >>= 2; | |
112 | ||
113 | if (addr >= ARRAY_SIZE(s->regs)) { | |
114 | qemu_log_mask(LOG_GUEST_ERROR, | |
115 | "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", | |
116 | __func__, addr); | |
117 | return 0; | |
118 | } | |
119 | ||
120 | return s->regs[addr]; | |
121 | } | |
122 | ||
123 | static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, | |
124 | unsigned int size) | |
125 | { | |
126 | AspeedSDMCState *s = ASPEED_SDMC(opaque); | |
8e00d1a9 | 127 | AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); |
c2da8a8b CLG |
128 | |
129 | addr >>= 2; | |
130 | ||
131 | if (addr >= ARRAY_SIZE(s->regs)) { | |
132 | qemu_log_mask(LOG_GUEST_ERROR, | |
133 | "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", | |
134 | __func__, addr); | |
135 | return; | |
136 | } | |
137 | ||
8e00d1a9 | 138 | asc->write(s, addr, data); |
c2da8a8b CLG |
139 | } |
140 | ||
141 | static const MemoryRegionOps aspeed_sdmc_ops = { | |
142 | .read = aspeed_sdmc_read, | |
143 | .write = aspeed_sdmc_write, | |
144 | .endianness = DEVICE_LITTLE_ENDIAN, | |
145 | .valid.min_access_size = 4, | |
146 | .valid.max_access_size = 4, | |
147 | }; | |
148 | ||
c6c7cfb0 | 149 | static int ast2400_rambits(AspeedSDMCState *s) |
c2da8a8b | 150 | { |
c6c7cfb0 | 151 | switch (s->ram_size >> 20) { |
c2da8a8b CLG |
152 | case 64: |
153 | return ASPEED_SDMC_DRAM_64MB; | |
154 | case 128: | |
155 | return ASPEED_SDMC_DRAM_128MB; | |
156 | case 256: | |
157 | return ASPEED_SDMC_DRAM_256MB; | |
158 | case 512: | |
159 | return ASPEED_SDMC_DRAM_512MB; | |
160 | default: | |
533eb415 | 161 | g_assert_not_reached(); |
c2da8a8b CLG |
162 | break; |
163 | } | |
c2da8a8b CLG |
164 | } |
165 | ||
c6c7cfb0 | 166 | static int ast2500_rambits(AspeedSDMCState *s) |
c2da8a8b | 167 | { |
c6c7cfb0 | 168 | switch (s->ram_size >> 20) { |
c2da8a8b CLG |
169 | case 128: |
170 | return ASPEED_SDMC_AST2500_128MB; | |
171 | case 256: | |
172 | return ASPEED_SDMC_AST2500_256MB; | |
173 | case 512: | |
174 | return ASPEED_SDMC_AST2500_512MB; | |
175 | case 1024: | |
176 | return ASPEED_SDMC_AST2500_1024MB; | |
177 | default: | |
533eb415 | 178 | g_assert_not_reached(); |
c2da8a8b CLG |
179 | break; |
180 | } | |
c2da8a8b CLG |
181 | } |
182 | ||
1550d726 JS |
183 | static int ast2600_rambits(AspeedSDMCState *s) |
184 | { | |
185 | switch (s->ram_size >> 20) { | |
186 | case 256: | |
187 | return ASPEED_SDMC_AST2600_256MB; | |
188 | case 512: | |
189 | return ASPEED_SDMC_AST2600_512MB; | |
190 | case 1024: | |
191 | return ASPEED_SDMC_AST2600_1024MB; | |
192 | case 2048: | |
193 | return ASPEED_SDMC_AST2600_2048MB; | |
194 | default: | |
533eb415 | 195 | g_assert_not_reached(); |
1550d726 JS |
196 | break; |
197 | } | |
1550d726 JS |
198 | } |
199 | ||
c2da8a8b CLG |
200 | static void aspeed_sdmc_reset(DeviceState *dev) |
201 | { | |
202 | AspeedSDMCState *s = ASPEED_SDMC(dev); | |
8e00d1a9 | 203 | AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); |
c2da8a8b CLG |
204 | |
205 | memset(s->regs, 0, sizeof(s->regs)); | |
206 | ||
207 | /* Set ram size bit and defaults values */ | |
8e00d1a9 | 208 | s->regs[R_CONF] = asc->compute_conf(s, 0); |
c2da8a8b CLG |
209 | } |
210 | ||
533eb415 IM |
211 | static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name, |
212 | void *opaque, Error **errp) | |
213 | { | |
214 | AspeedSDMCState *s = ASPEED_SDMC(obj); | |
215 | int64_t value = s->ram_size; | |
216 | ||
217 | visit_type_int(v, name, &value, errp); | |
218 | } | |
219 | ||
220 | static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name, | |
221 | void *opaque, Error **errp) | |
222 | { | |
223 | int i; | |
224 | char *sz; | |
225 | int64_t value; | |
533eb415 IM |
226 | AspeedSDMCState *s = ASPEED_SDMC(obj); |
227 | AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); | |
228 | ||
668f62ec | 229 | if (!visit_type_int(v, name, &value, errp)) { |
533eb415 IM |
230 | return; |
231 | } | |
232 | ||
233 | for (i = 0; asc->valid_ram_sizes[i]; i++) { | |
234 | if (value == asc->valid_ram_sizes[i]) { | |
235 | s->ram_size = value; | |
236 | return; | |
237 | } | |
238 | } | |
239 | ||
240 | sz = size_to_str(value); | |
dcfe4805 | 241 | error_setg(errp, "Invalid RAM size %s", sz); |
533eb415 | 242 | g_free(sz); |
533eb415 IM |
243 | } |
244 | ||
245 | static void aspeed_sdmc_initfn(Object *obj) | |
246 | { | |
247 | object_property_add(obj, "ram-size", "int", | |
248 | aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size, | |
d2623129 | 249 | NULL, NULL); |
533eb415 IM |
250 | } |
251 | ||
c2da8a8b CLG |
252 | static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) |
253 | { | |
254 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
255 | AspeedSDMCState *s = ASPEED_SDMC(dev); | |
8e00d1a9 | 256 | AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); |
c2da8a8b | 257 | |
8e00d1a9 | 258 | s->max_ram_size = asc->max_ram_size; |
3755f9e3 | 259 | |
c2da8a8b CLG |
260 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s, |
261 | TYPE_ASPEED_SDMC, 0x1000); | |
262 | sysbus_init_mmio(sbd, &s->iomem); | |
263 | } | |
264 | ||
265 | static const VMStateDescription vmstate_aspeed_sdmc = { | |
266 | .name = "aspeed.sdmc", | |
267 | .version_id = 1, | |
268 | .minimum_version_id = 1, | |
269 | .fields = (VMStateField[]) { | |
270 | VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS), | |
271 | VMSTATE_END_OF_LIST() | |
272 | } | |
273 | }; | |
274 | ||
275 | static Property aspeed_sdmc_properties[] = { | |
ebe31c0a | 276 | DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0), |
c2da8a8b CLG |
277 | DEFINE_PROP_END_OF_LIST(), |
278 | }; | |
279 | ||
280 | static void aspeed_sdmc_class_init(ObjectClass *klass, void *data) | |
281 | { | |
282 | DeviceClass *dc = DEVICE_CLASS(klass); | |
283 | dc->realize = aspeed_sdmc_realize; | |
284 | dc->reset = aspeed_sdmc_reset; | |
285 | dc->desc = "ASPEED SDRAM Memory Controller"; | |
286 | dc->vmsd = &vmstate_aspeed_sdmc; | |
4f67d30b | 287 | device_class_set_props(dc, aspeed_sdmc_properties); |
c2da8a8b CLG |
288 | } |
289 | ||
290 | static const TypeInfo aspeed_sdmc_info = { | |
291 | .name = TYPE_ASPEED_SDMC, | |
292 | .parent = TYPE_SYS_BUS_DEVICE, | |
293 | .instance_size = sizeof(AspeedSDMCState), | |
533eb415 | 294 | .instance_init = aspeed_sdmc_initfn, |
c2da8a8b | 295 | .class_init = aspeed_sdmc_class_init, |
8e00d1a9 CLG |
296 | .class_size = sizeof(AspeedSDMCClass), |
297 | .abstract = true, | |
298 | }; | |
299 | ||
300 | static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) | |
301 | { | |
302 | uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT | | |
303 | ASPEED_SDMC_DRAM_SIZE(ast2400_rambits(s)); | |
304 | ||
305 | /* Make sure readonly bits are kept */ | |
306 | data &= ~ASPEED_SDMC_READONLY_MASK; | |
307 | ||
308 | return data | fixed_conf; | |
309 | } | |
310 | ||
311 | static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg, | |
312 | uint32_t data) | |
313 | { | |
f4ab4f8e JS |
314 | if (reg == R_PROT) { |
315 | s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED; | |
316 | return; | |
317 | } | |
318 | ||
319 | if (!s->regs[R_PROT]) { | |
320 | qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__); | |
321 | return; | |
322 | } | |
323 | ||
8e00d1a9 CLG |
324 | switch (reg) { |
325 | case R_CONF: | |
326 | data = aspeed_2400_sdmc_compute_conf(s, data); | |
327 | break; | |
328 | default: | |
329 | break; | |
330 | } | |
331 | ||
332 | s->regs[reg] = data; | |
333 | } | |
334 | ||
533eb415 IM |
335 | static const uint64_t |
336 | aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0}; | |
337 | ||
8e00d1a9 CLG |
338 | static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data) |
339 | { | |
340 | DeviceClass *dc = DEVICE_CLASS(klass); | |
341 | AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); | |
342 | ||
343 | dc->desc = "ASPEED 2400 SDRAM Memory Controller"; | |
344 | asc->max_ram_size = 512 << 20; | |
345 | asc->compute_conf = aspeed_2400_sdmc_compute_conf; | |
346 | asc->write = aspeed_2400_sdmc_write; | |
533eb415 | 347 | asc->valid_ram_sizes = aspeed_2400_ram_sizes; |
8e00d1a9 CLG |
348 | } |
349 | ||
350 | static const TypeInfo aspeed_2400_sdmc_info = { | |
351 | .name = TYPE_ASPEED_2400_SDMC, | |
352 | .parent = TYPE_ASPEED_SDMC, | |
353 | .class_init = aspeed_2400_sdmc_class_init, | |
354 | }; | |
355 | ||
356 | static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) | |
357 | { | |
358 | uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) | | |
359 | ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | | |
360 | ASPEED_SDMC_CACHE_INITIAL_DONE | | |
361 | ASPEED_SDMC_DRAM_SIZE(ast2500_rambits(s)); | |
362 | ||
363 | /* Make sure readonly bits are kept */ | |
364 | data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; | |
365 | ||
366 | return data | fixed_conf; | |
367 | } | |
368 | ||
369 | static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg, | |
370 | uint32_t data) | |
371 | { | |
f4ab4f8e JS |
372 | if (reg == R_PROT) { |
373 | s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED; | |
374 | return; | |
375 | } | |
376 | ||
377 | if (!s->regs[R_PROT]) { | |
378 | qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__); | |
379 | return; | |
380 | } | |
381 | ||
8e00d1a9 CLG |
382 | switch (reg) { |
383 | case R_CONF: | |
384 | data = aspeed_2500_sdmc_compute_conf(s, data); | |
385 | break; | |
386 | case R_STATUS1: | |
387 | /* Will never return 'busy' */ | |
388 | data &= ~PHY_BUSY_STATE; | |
389 | break; | |
390 | case R_ECC_TEST_CTRL: | |
391 | /* Always done, always happy */ | |
392 | data |= ECC_TEST_FINISHED; | |
393 | data &= ~ECC_TEST_FAIL; | |
394 | break; | |
395 | default: | |
396 | break; | |
397 | } | |
398 | ||
399 | s->regs[reg] = data; | |
400 | } | |
401 | ||
533eb415 IM |
402 | static const uint64_t |
403 | aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0}; | |
404 | ||
8e00d1a9 CLG |
405 | static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data) |
406 | { | |
407 | DeviceClass *dc = DEVICE_CLASS(klass); | |
408 | AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); | |
409 | ||
410 | dc->desc = "ASPEED 2500 SDRAM Memory Controller"; | |
411 | asc->max_ram_size = 1024 << 20; | |
412 | asc->compute_conf = aspeed_2500_sdmc_compute_conf; | |
413 | asc->write = aspeed_2500_sdmc_write; | |
533eb415 | 414 | asc->valid_ram_sizes = aspeed_2500_ram_sizes; |
8e00d1a9 CLG |
415 | } |
416 | ||
417 | static const TypeInfo aspeed_2500_sdmc_info = { | |
418 | .name = TYPE_ASPEED_2500_SDMC, | |
419 | .parent = TYPE_ASPEED_SDMC, | |
420 | .class_init = aspeed_2500_sdmc_class_init, | |
c2da8a8b CLG |
421 | }; |
422 | ||
1550d726 JS |
423 | static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) |
424 | { | |
425 | uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) | | |
426 | ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | | |
427 | ASPEED_SDMC_DRAM_SIZE(ast2600_rambits(s)); | |
428 | ||
429 | /* Make sure readonly bits are kept (use ast2500 mask) */ | |
430 | data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; | |
431 | ||
432 | return data | fixed_conf; | |
433 | } | |
434 | ||
435 | static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg, | |
436 | uint32_t data) | |
437 | { | |
f4ab4f8e JS |
438 | if (s->regs[R_PROT] == PROT_HARDLOCKED) { |
439 | qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n", | |
440 | __func__); | |
441 | return; | |
442 | } | |
443 | ||
444 | if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) { | |
445 | qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__); | |
446 | return; | |
447 | } | |
448 | ||
1550d726 | 449 | switch (reg) { |
f4ab4f8e JS |
450 | case R_PROT: |
451 | if (data == PROT_KEY_UNLOCK) { | |
452 | data = PROT_UNLOCKED; | |
453 | } else if (data == PROT_KEY_HARDLOCK) { | |
454 | data = PROT_HARDLOCKED; | |
455 | } else { | |
456 | data = PROT_SOFTLOCKED; | |
457 | } | |
458 | break; | |
1550d726 JS |
459 | case R_CONF: |
460 | data = aspeed_2600_sdmc_compute_conf(s, data); | |
461 | break; | |
462 | case R_STATUS1: | |
463 | /* Will never return 'busy'. 'lock status' is always set */ | |
464 | data &= ~PHY_BUSY_STATE; | |
465 | data |= PHY_PLL_LOCK_STATUS; | |
466 | break; | |
467 | case R_ECC_TEST_CTRL: | |
468 | /* Always done, always happy */ | |
469 | data |= ECC_TEST_FINISHED; | |
470 | data &= ~ECC_TEST_FAIL; | |
471 | break; | |
472 | default: | |
473 | break; | |
474 | } | |
475 | ||
476 | s->regs[reg] = data; | |
477 | } | |
478 | ||
533eb415 IM |
479 | static const uint64_t |
480 | aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0}; | |
481 | ||
1550d726 JS |
482 | static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data) |
483 | { | |
484 | DeviceClass *dc = DEVICE_CLASS(klass); | |
485 | AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); | |
486 | ||
487 | dc->desc = "ASPEED 2600 SDRAM Memory Controller"; | |
488 | asc->max_ram_size = 2048 << 20; | |
489 | asc->compute_conf = aspeed_2600_sdmc_compute_conf; | |
490 | asc->write = aspeed_2600_sdmc_write; | |
533eb415 | 491 | asc->valid_ram_sizes = aspeed_2600_ram_sizes; |
1550d726 JS |
492 | } |
493 | ||
494 | static const TypeInfo aspeed_2600_sdmc_info = { | |
495 | .name = TYPE_ASPEED_2600_SDMC, | |
496 | .parent = TYPE_ASPEED_SDMC, | |
497 | .class_init = aspeed_2600_sdmc_class_init, | |
498 | }; | |
499 | ||
c2da8a8b CLG |
500 | static void aspeed_sdmc_register_types(void) |
501 | { | |
502 | type_register_static(&aspeed_sdmc_info); | |
8e00d1a9 CLG |
503 | type_register_static(&aspeed_2400_sdmc_info); |
504 | type_register_static(&aspeed_2500_sdmc_info); | |
1550d726 | 505 | type_register_static(&aspeed_2600_sdmc_info); |
c2da8a8b CLG |
506 | } |
507 | ||
508 | type_init(aspeed_sdmc_register_types); |