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dc288de0 MR |
1 | /* |
2 | * AVR Power Reduction Management | |
3 | * | |
4 | * Copyright (c) 2019-2020 Michael Rolnik | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "qemu/osdep.h" | |
26 | #include "hw/misc/avr_power.h" | |
27 | #include "qemu/log.h" | |
28 | #include "hw/qdev-properties.h" | |
29 | #include "hw/irq.h" | |
30 | #include "trace.h" | |
31 | ||
32 | static void avr_mask_reset(DeviceState *dev) | |
33 | { | |
34 | AVRMaskState *s = AVR_MASK(dev); | |
35 | ||
36 | s->val = 0x00; | |
37 | ||
38 | for (int i = 0; i < 8; i++) { | |
39 | qemu_set_irq(s->irq[i], 0); | |
40 | } | |
41 | } | |
42 | ||
43 | static uint64_t avr_mask_read(void *opaque, hwaddr offset, unsigned size) | |
44 | { | |
45 | assert(size == 1); | |
46 | assert(offset == 0); | |
47 | AVRMaskState *s = opaque; | |
48 | ||
49 | trace_avr_power_read(s->val); | |
50 | ||
51 | return (uint64_t)s->val; | |
52 | } | |
53 | ||
54 | static void avr_mask_write(void *opaque, hwaddr offset, | |
55 | uint64_t val64, unsigned size) | |
56 | { | |
57 | assert(size == 1); | |
58 | assert(offset == 0); | |
59 | AVRMaskState *s = opaque; | |
60 | uint8_t val8 = val64; | |
61 | ||
62 | trace_avr_power_write(val8); | |
63 | s->val = val8; | |
64 | for (int i = 0; i < 8; i++) { | |
65 | qemu_set_irq(s->irq[i], (val8 & (1 << i)) != 0); | |
66 | } | |
67 | } | |
68 | ||
69 | static const MemoryRegionOps avr_mask_ops = { | |
70 | .read = avr_mask_read, | |
71 | .write = avr_mask_write, | |
72 | .endianness = DEVICE_NATIVE_ENDIAN, | |
73 | .impl = { | |
74 | .max_access_size = 1, | |
75 | }, | |
76 | }; | |
77 | ||
78 | static void avr_mask_init(Object *dev) | |
79 | { | |
80 | AVRMaskState *s = AVR_MASK(dev); | |
81 | SysBusDevice *busdev = SYS_BUS_DEVICE(dev); | |
82 | ||
83 | memory_region_init_io(&s->iomem, dev, &avr_mask_ops, s, TYPE_AVR_MASK, | |
84 | 0x01); | |
85 | sysbus_init_mmio(busdev, &s->iomem); | |
86 | ||
87 | for (int i = 0; i < 8; i++) { | |
88 | sysbus_init_irq(busdev, &s->irq[i]); | |
89 | } | |
90 | s->val = 0x00; | |
91 | } | |
92 | ||
93 | static void avr_mask_class_init(ObjectClass *klass, void *data) | |
94 | { | |
95 | DeviceClass *dc = DEVICE_CLASS(klass); | |
96 | ||
97 | dc->reset = avr_mask_reset; | |
98 | } | |
99 | ||
100 | static const TypeInfo avr_mask_info = { | |
101 | .name = TYPE_AVR_MASK, | |
102 | .parent = TYPE_SYS_BUS_DEVICE, | |
103 | .instance_size = sizeof(AVRMaskState), | |
104 | .class_init = avr_mask_class_init, | |
105 | .instance_init = avr_mask_init, | |
106 | }; | |
107 | ||
108 | static void avr_mask_register_types(void) | |
109 | { | |
110 | type_register_static(&avr_mask_info); | |
111 | } | |
112 | ||
113 | type_init(avr_mask_register_types) |