[mirror_qemu.git] / hw / misc / edu.c

/*
 * QEMU educational PCI device
 *
 * Copyright (c) 2012-2015 Jiri Slaby
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/pci/pci.h"
#include "hw/hw.h"
#include "hw/pci/msi.h"
#include "qemu/timer.h"
#include "qom/object.h"
#include "qemu/main-loop.h" /* iothread mutex */
#include "qemu/module.h"
#include "qapi/visitor.h"

#define TYPE_PCI_EDU_DEVICE "edu"
typedef struct EduState EduState;
DECLARE_INSTANCE_CHECKER(EduState, EDU,
                         TYPE_PCI_EDU_DEVICE)

#define FACT_IRQ        0x00000001
#define DMA_IRQ         0x00000100

#define DMA_START       0x40000
#define DMA_SIZE        4096

struct EduState {
    PCIDevice pdev;
    MemoryRegion mmio;

    QemuThread thread;
    QemuMutex thr_mutex;
    QemuCond thr_cond;
    bool stopping;

    uint32_t addr4;
    uint32_t fact;
#define EDU_STATUS_COMPUTING    0x01
#define EDU_STATUS_IRQFACT      0x80
    uint32_t status;

    uint32_t irq_status;

#define EDU_DMA_RUN             0x1
#define EDU_DMA_DIR(cmd)        (((cmd) & 0x2) >> 1)
# define EDU_DMA_FROM_PCI       0
# define EDU_DMA_TO_PCI         1
#define EDU_DMA_IRQ             0x4
    struct dma_state {
        dma_addr_t src;
        dma_addr_t dst;
        dma_addr_t cnt;
        dma_addr_t cmd;
    } dma;
    QEMUTimer dma_timer;
    char dma_buf[DMA_SIZE];
    uint64_t dma_mask;
};

static bool edu_msi_enabled(EduState *edu)
{
    return msi_enabled(&edu->pdev);
}

static void edu_raise_irq(EduState *edu, uint32_t val)
{
    edu->irq_status |= val;
    if (edu->irq_status) {
        if (edu_msi_enabled(edu)) {
            msi_notify(&edu->pdev, 0);
        } else {
            pci_set_irq(&edu->pdev, 1);
        }
    }
}

static void edu_lower_irq(EduState *edu, uint32_t val)
{
    edu->irq_status &= ~val;

    if (!edu->irq_status && !edu_msi_enabled(edu)) {
        pci_set_irq(&edu->pdev, 0);
    }
}

static bool within(uint64_t addr, uint64_t start, uint64_t end)
{
    return start <= addr && addr < end;
}

static void edu_check_range(uint64_t addr, uint64_t size1, uint64_t start,
                uint64_t size2)
{
    uint64_t end1 = addr + size1;
    uint64_t end2 = start + size2;

    if (within(addr, start, end2) &&
            end1 > addr && within(end1, start, end2)) {
        return;
    }

    hw_error("EDU: DMA range 0x%016"PRIx64"-0x%016"PRIx64
             " out of bounds (0x%016"PRIx64"-0x%016"PRIx64")!",
            addr, end1 - 1, start, end2 - 1);
}

static dma_addr_t edu_clamp_addr(const EduState *edu, dma_addr_t addr)
{
    dma_addr_t res = addr & edu->dma_mask;

    if (addr != res) {
        printf("EDU: clamping DMA %#.16"PRIx64" to %#.16"PRIx64"!\n", addr, res);
    }

    return res;
}

static void edu_dma_timer(void *opaque)
{
    EduState *edu = opaque;
    bool raise_irq = false;

    if (!(edu->dma.cmd & EDU_DMA_RUN)) {
        return;
    }

    if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) {
        uint64_t dst = edu->dma.dst;
        edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE);
        dst -= DMA_START;
        pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src),
                edu->dma_buf + dst, edu->dma.cnt);
    } else {
        uint64_t src = edu->dma.src;
        edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE);
        src -= DMA_START;
        pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst),
                edu->dma_buf + src, edu->dma.cnt);
    }

    edu->dma.cmd &= ~EDU_DMA_RUN;
    if (edu->dma.cmd & EDU_DMA_IRQ) {
        raise_irq = true;
    }

    if (raise_irq) {
        edu_raise_irq(edu, DMA_IRQ);
    }
}

static void dma_rw(EduState *edu, bool write, dma_addr_t *val, dma_addr_t *dma,
                bool timer)
{
    if (write && (edu->dma.cmd & EDU_DMA_RUN)) {
        return;
    }

    if (write) {
        *dma = *val;
    } else {
        *val = *dma;
    }

    if (timer) {
        timer_mod(&edu->dma_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100);
    }
}

static uint64_t edu_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
    EduState *edu = opaque;
    uint64_t val = ~0ULL;

    if (addr < 0x80 && size != 4) {
        return val;
    }

    if (addr >= 0x80 && size != 4 && size != 8) {
        return val;
    }

    switch (addr) {
    case 0x00:
        val = 0x010000edu;
        break;
    case 0x04:
        val = edu->addr4;
        break;
    case 0x08:
        qemu_mutex_lock(&edu->thr_mutex);
        val = edu->fact;
        qemu_mutex_unlock(&edu->thr_mutex);
        break;
    case 0x20:
        val = qatomic_read(&edu->status);
        break;
    case 0x24:
        val = edu->irq_status;
        break;
    case 0x80:
        dma_rw(edu, false, &val, &edu->dma.src, false);
        break;
    case 0x88:
        dma_rw(edu, false, &val, &edu->dma.dst, false);
        break;
    case 0x90:
        dma_rw(edu, false, &val, &edu->dma.cnt, false);
        break;
    case 0x98:
        dma_rw(edu, false, &val, &edu->dma.cmd, false);
        break;
    }

    return val;
}

static void edu_mmio_write(void *opaque, hwaddr addr, uint64_t val,
                unsigned size)
{
    EduState *edu = opaque;

    if (addr < 0x80 && size != 4) {
        return;
    }

    if (addr >= 0x80 && size != 4 && size != 8) {
        return;
    }

    switch (addr) {
    case 0x04:
        edu->addr4 = ~val;
        break;
    case 0x08:
        if (qatomic_read(&edu->status) & EDU_STATUS_COMPUTING) {
            break;
        }
        /* EDU_STATUS_COMPUTING cannot go 0->1 concurrently, because it is only
         * set in this function and it is under the iothread mutex.
         */
        qemu_mutex_lock(&edu->thr_mutex);
        edu->fact = val;
        qatomic_or(&edu->status, EDU_STATUS_COMPUTING);
        qemu_cond_signal(&edu->thr_cond);
        qemu_mutex_unlock(&edu->thr_mutex);
        break;
    case 0x20:
        if (val & EDU_STATUS_IRQFACT) {
            qatomic_or(&edu->status, EDU_STATUS_IRQFACT);
            /* Order check of the COMPUTING flag after setting IRQFACT.  */
            smp_mb__after_rmw();
        } else {
            qatomic_and(&edu->status, ~EDU_STATUS_IRQFACT);
        }
        break;
    case 0x60:
        edu_raise_irq(edu, val);
        break;
    case 0x64:
        edu_lower_irq(edu, val);
        break;
    case 0x80:
        dma_rw(edu, true, &val, &edu->dma.src, false);
        break;
    case 0x88:
        dma_rw(edu, true, &val, &edu->dma.dst, false);
        break;
    case 0x90:
        dma_rw(edu, true, &val, &edu->dma.cnt, false);
        break;
    case 0x98:
        if (!(val & EDU_DMA_RUN)) {
            break;
        }
        dma_rw(edu, true, &val, &edu->dma.cmd, true);
        break;
    }
}

static const MemoryRegionOps edu_mmio_ops = {
    .read = edu_mmio_read,
    .write = edu_mmio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 8,
    },
    .impl = {
        .min_access_size = 4,
        .max_access_size = 8,
    },

};

/*
 * We purposely use a thread, so that users are forced to wait for the status
 * register.
 */
static void *edu_fact_thread(void *opaque)
{
    EduState *edu = opaque;

    while (1) {
        uint32_t val, ret = 1;

        qemu_mutex_lock(&edu->thr_mutex);
        while ((qatomic_read(&edu->status) & EDU_STATUS_COMPUTING) == 0 &&
                        !edu->stopping) {
            qemu_cond_wait(&edu->thr_cond, &edu->thr_mutex);
        }

        if (edu->stopping) {
            qemu_mutex_unlock(&edu->thr_mutex);
            break;
        }

        val = edu->fact;
        qemu_mutex_unlock(&edu->thr_mutex);

        while (val > 0) {
            ret *= val--;
        }

        /*
         * We should sleep for a random period here, so that students are
         * forced to check the status properly.
         */

        qemu_mutex_lock(&edu->thr_mutex);
        edu->fact = ret;
        qemu_mutex_unlock(&edu->thr_mutex);
        qatomic_and(&edu->status, ~EDU_STATUS_COMPUTING);

        /* Clear COMPUTING flag before checking IRQFACT.  */
        smp_mb__after_rmw();

        if (qatomic_read(&edu->status) & EDU_STATUS_IRQFACT) {
            qemu_mutex_lock_iothread();
            edu_raise_irq(edu, FACT_IRQ);
            qemu_mutex_unlock_iothread();
        }
    }

    return NULL;
}

static void pci_edu_realize(PCIDevice *pdev, Error **errp)
{
    EduState *edu = EDU(pdev);
    uint8_t *pci_conf = pdev->config;

    pci_config_set_interrupt_pin(pci_conf, 1);

    if (msi_init(pdev, 0, 1, true, false, errp)) {
        return;
    }

    timer_init_ms(&edu->dma_timer, QEMU_CLOCK_VIRTUAL, edu_dma_timer, edu);

    qemu_mutex_init(&edu->thr_mutex);
    qemu_cond_init(&edu->thr_cond);
    qemu_thread_create(&edu->thread, "edu", edu_fact_thread,
                       edu, QEMU_THREAD_JOINABLE);

    memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
                    "edu-mmio", 1 * MiB);
    pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);
}

static void pci_edu_uninit(PCIDevice *pdev)
{
    EduState *edu = EDU(pdev);

    qemu_mutex_lock(&edu->thr_mutex);
    edu->stopping = true;
    qemu_mutex_unlock(&edu->thr_mutex);
    qemu_cond_signal(&edu->thr_cond);
    qemu_thread_join(&edu->thread);

    qemu_cond_destroy(&edu->thr_cond);
    qemu_mutex_destroy(&edu->thr_mutex);

    timer_del(&edu->dma_timer);
    msi_uninit(pdev);
}

static void edu_instance_init(Object *obj)
{
    EduState *edu = EDU(obj);

    edu->dma_mask = (1UL << 28) - 1;
    object_property_add_uint64_ptr(obj, "dma_mask",
                                   &edu->dma_mask, OBJ_PROP_FLAG_READWRITE);
}

static void edu_class_init(ObjectClass *class, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(class);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(class);

    k->realize = pci_edu_realize;
    k->exit = pci_edu_uninit;
    k->vendor_id = PCI_VENDOR_ID_QEMU;
    k->device_id = 0x11e8;
    k->revision = 0x10;
    k->class_id = PCI_CLASS_OTHERS;
    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}

static void pci_edu_register_types(void)
{
    static InterfaceInfo interfaces[] = {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    };
    static const TypeInfo edu_info = {
        .name          = TYPE_PCI_EDU_DEVICE,
        .parent        = TYPE_PCI_DEVICE,
        .instance_size = sizeof(EduState),
        .instance_init = edu_instance_init,
        .class_init    = edu_class_init,
        .interfaces = interfaces,
    };

    type_register_static(&edu_info);
}
type_init(pci_edu_register_types)
Commit	Line	Data
b30934cb JS	1	/*
	2	* QEMU educational PCI device
	3	*
	4	* Copyright (c) 2012-2015 Jiri Slaby
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	19	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*/
	24
0d1c9782	25	#include "qemu/osdep.h"
de9b602e	26	#include "qemu/units.h"
b30934cb	27	#include "hw/pci/pci.h"
650d103d	28	#include "hw/hw.h"
eabb5782	29	#include "hw/pci/msi.h"
b30934cb	30	#include "qemu/timer.h"
db1015e9	31	#include "qom/object.h"
b30934cb	32	#include "qemu/main-loop.h" /* iothread mutex */
0b8fa32f	33	#include "qemu/module.h"
b30934cb JS	34	#include "qapi/visitor.h"
b30934cb JS	35
8371158b	36	#define TYPE_PCI_EDU_DEVICE "edu"
db1015e9	37	typedef struct EduState EduState;
8110fa1d EH	38	DECLARE_INSTANCE_CHECKER(EduState, EDU,
8110fa1d EH	39	TYPE_PCI_EDU_DEVICE)
b30934cb JS	40
	41	#define FACT_IRQ 0x00000001
	42	#define DMA_IRQ 0x00000100
	43
	44	#define DMA_START 0x40000
	45	#define DMA_SIZE 4096
	46
db1015e9	47	struct EduState {
b30934cb JS	48	PCIDevice pdev;
	49	MemoryRegion mmio;
	50
	51	QemuThread thread;
	52	QemuMutex thr_mutex;
	53	QemuCond thr_cond;
	54	bool stopping;
	55
	56	uint32_t addr4;
	57	uint32_t fact;
	58	#define EDU_STATUS_COMPUTING 0x01
	59	#define EDU_STATUS_IRQFACT 0x80
	60	uint32_t status;
	61
	62	uint32_t irq_status;
	63
	64	#define EDU_DMA_RUN 0x1
	65	#define EDU_DMA_DIR(cmd) (((cmd) & 0x2) >> 1)
	66	# define EDU_DMA_FROM_PCI 0
	67	# define EDU_DMA_TO_PCI 1
	68	#define EDU_DMA_IRQ 0x4
	69	struct dma_state {
	70	dma_addr_t src;
	71	dma_addr_t dst;
	72	dma_addr_t cnt;
	73	dma_addr_t cmd;
	74	} dma;
	75	QEMUTimer dma_timer;
	76	char dma_buf[DMA_SIZE];
	77	uint64_t dma_mask;
db1015e9	78	};
b30934cb	79
eabb5782 PX	80	static bool edu_msi_enabled(EduState *edu)
	81	{
	82	return msi_enabled(&edu->pdev);
	83	}
	84
b30934cb JS	85	static void edu_raise_irq(EduState *edu, uint32_t val)
	86	{
	87	edu->irq_status \|= val;
	88	if (edu->irq_status) {
eabb5782 PX	89	if (edu_msi_enabled(edu)) {
	90	msi_notify(&edu->pdev, 0);
	91	} else {
	92	pci_set_irq(&edu->pdev, 1);
	93	}
b30934cb JS	94	}
	95	}
	96
	97	static void edu_lower_irq(EduState *edu, uint32_t val)
	98	{
	99	edu->irq_status &= ~val;
	100
eabb5782	101	if (!edu->irq_status && !edu_msi_enabled(edu)) {
b30934cb JS	102	pci_set_irq(&edu->pdev, 0);
	103	}
	104	}
	105
7fca21c8	106	static bool within(uint64_t addr, uint64_t start, uint64_t end)
b30934cb JS	107	{
	108	return start <= addr && addr < end;
	109	}
	110
7fca21c8 LQ	111	static void edu_check_range(uint64_t addr, uint64_t size1, uint64_t start,
7fca21c8 LQ	112	uint64_t size2)
b30934cb	113	{
7fca21c8 LQ	114	uint64_t end1 = addr + size1;
7fca21c8 LQ	115	uint64_t end2 = start + size2;
b30934cb JS	116
	117	if (within(addr, start, end2) &&
	118	end1 > addr && within(end1, start, end2)) {
	119	return;
	120	}
	121
7fca21c8 LQ	122	hw_error("EDU: DMA range 0x%016"PRIx64"-0x%016"PRIx64
7fca21c8 LQ	123	" out of bounds (0x%016"PRIx64"-0x%016"PRIx64")!",
b30934cb JS	124	addr, end1 - 1, start, end2 - 1);
	125	}
	126
	127	static dma_addr_t edu_clamp_addr(const EduState *edu, dma_addr_t addr)
	128	{
	129	dma_addr_t res = addr & edu->dma_mask;
	130
	131	if (addr != res) {
	132	printf("EDU: clamping DMA %#.16"PRIx64" to %#.16"PRIx64"!\n", addr, res);
	133	}
	134
	135	return res;
	136	}
	137
	138	static void edu_dma_timer(void *opaque)
	139	{
	140	EduState *edu = opaque;
	141	bool raise_irq = false;
	142
	143	if (!(edu->dma.cmd & EDU_DMA_RUN)) {
	144	return;
	145	}
	146
	147	if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) {
7fca21c8	148	uint64_t dst = edu->dma.dst;
b30934cb JS	149	edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE);
	150	dst -= DMA_START;
	151	pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src),
	152	edu->dma_buf + dst, edu->dma.cnt);
	153	} else {
7fca21c8	154	uint64_t src = edu->dma.src;
b30934cb JS	155	edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE);
	156	src -= DMA_START;
	157	pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst),
	158	edu->dma_buf + src, edu->dma.cnt);
	159	}
	160
	161	edu->dma.cmd &= ~EDU_DMA_RUN;
	162	if (edu->dma.cmd & EDU_DMA_IRQ) {
	163	raise_irq = true;
	164	}
	165
	166	if (raise_irq) {
	167	edu_raise_irq(edu, DMA_IRQ);
	168	}
	169	}
	170
	171	static void dma_rw(EduState edu, bool write, dma_addr_t val, dma_addr_t *dma,
	172	bool timer)
	173	{
	174	if (write && (edu->dma.cmd & EDU_DMA_RUN)) {
	175	return;
	176	}
	177
	178	if (write) {
	179	dma = val;
	180	} else {
	181	val = dma;
	182	}
	183
	184	if (timer) {
	185	timer_mod(&edu->dma_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100);
	186	}
	187	}
	188
	189	static uint64_t edu_mmio_read(void *opaque, hwaddr addr, unsigned size)
	190	{
	191	EduState *edu = opaque;
	192	uint64_t val = ~0ULL;
	193
c45eb53a LQ	194	if (addr < 0x80 && size != 4) {
	195	return val;
	196	}
	197
	198	if (addr >= 0x80 && size != 4 && size != 8) {
b30934cb JS	199	return val;
	200	}
	201
	202	switch (addr) {
	203	case 0x00:
	204	val = 0x010000edu;
	205	break;
	206	case 0x04:
	207	val = edu->addr4;
	208	break;
	209	case 0x08:
	210	qemu_mutex_lock(&edu->thr_mutex);
	211	val = edu->fact;
	212	qemu_mutex_unlock(&edu->thr_mutex);
	213	break;
	214	case 0x20:
d73415a3	215	val = qatomic_read(&edu->status);
b30934cb JS	216	break;
	217	case 0x24:
	218	val = edu->irq_status;
	219	break;
	220	case 0x80:
	221	dma_rw(edu, false, &val, &edu->dma.src, false);
	222	break;
	223	case 0x88:
	224	dma_rw(edu, false, &val, &edu->dma.dst, false);
	225	break;
	226	case 0x90:
	227	dma_rw(edu, false, &val, &edu->dma.cnt, false);
	228	break;
	229	case 0x98:
	230	dma_rw(edu, false, &val, &edu->dma.cmd, false);
	231	break;
	232	}
	233
	234	return val;
	235	}
	236
	237	static void edu_mmio_write(void *opaque, hwaddr addr, uint64_t val,
	238	unsigned size)
	239	{
	240	EduState *edu = opaque;
	241
	242	if (addr < 0x80 && size != 4) {
	243	return;
	244	}
	245
	246	if (addr >= 0x80 && size != 4 && size != 8) {
	247	return;
	248	}
	249
	250	switch (addr) {
	251	case 0x04:
	252	edu->addr4 = ~val;
	253	break;
	254	case 0x08:
d73415a3	255	if (qatomic_read(&edu->status) & EDU_STATUS_COMPUTING) {
b30934cb JS	256	break;
	257	}
	258	/* EDU_STATUS_COMPUTING cannot go 0->1 concurrently, because it is only
	259	* set in this function and it is under the iothread mutex.
	260	*/
	261	qemu_mutex_lock(&edu->thr_mutex);
	262	edu->fact = val;
d73415a3	263	qatomic_or(&edu->status, EDU_STATUS_COMPUTING);
b30934cb JS	264	qemu_cond_signal(&edu->thr_cond);
	265	qemu_mutex_unlock(&edu->thr_mutex);
	266	break;
	267	case 0x20:
	268	if (val & EDU_STATUS_IRQFACT) {
d73415a3	269	qatomic_or(&edu->status, EDU_STATUS_IRQFACT);
2482aeea PB	270	/* Order check of the COMPUTING flag after setting IRQFACT. */
2482aeea PB	271	smp_mb__after_rmw();
b30934cb	272	} else {
d73415a3	273	qatomic_and(&edu->status, ~EDU_STATUS_IRQFACT);
b30934cb JS	274	}
	275	break;
	276	case 0x60:
	277	edu_raise_irq(edu, val);
	278	break;
	279	case 0x64:
	280	edu_lower_irq(edu, val);
	281	break;
	282	case 0x80:
	283	dma_rw(edu, true, &val, &edu->dma.src, false);
	284	break;
	285	case 0x88:
	286	dma_rw(edu, true, &val, &edu->dma.dst, false);
	287	break;
	288	case 0x90:
	289	dma_rw(edu, true, &val, &edu->dma.cnt, false);
	290	break;
	291	case 0x98:
	292	if (!(val & EDU_DMA_RUN)) {
	293	break;
	294	}
	295	dma_rw(edu, true, &val, &edu->dma.cmd, true);
	296	break;
	297	}
	298	}
	299
	300	static const MemoryRegionOps edu_mmio_ops = {
	301	.read = edu_mmio_read,
	302	.write = edu_mmio_write,
	303	.endianness = DEVICE_NATIVE_ENDIAN,
20fb3105 LQ	304	.valid = {
	305	.min_access_size = 4,
	306	.max_access_size = 8,
	307	},
	308	.impl = {
	309	.min_access_size = 4,
	310	.max_access_size = 8,
	311	},
	312
b30934cb JS	313	};
	314
	315	/*
631b22ea	316	* We purposely use a thread, so that users are forced to wait for the status
b30934cb JS	317	* register.
	318	*/
	319	static void edu_fact_thread(void opaque)
	320	{
	321	EduState *edu = opaque;
	322
	323	while (1) {
	324	uint32_t val, ret = 1;
	325
	326	qemu_mutex_lock(&edu->thr_mutex);
d73415a3	327	while ((qatomic_read(&edu->status) & EDU_STATUS_COMPUTING) == 0 &&
b30934cb JS	328	!edu->stopping) {
	329	qemu_cond_wait(&edu->thr_cond, &edu->thr_mutex);
	330	}
	331
	332	if (edu->stopping) {
	333	qemu_mutex_unlock(&edu->thr_mutex);
	334	break;
	335	}
	336
	337	val = edu->fact;
	338	qemu_mutex_unlock(&edu->thr_mutex);
	339
	340	while (val > 0) {
	341	ret *= val--;
	342	}
	343
	344	/*
	345	* We should sleep for a random period here, so that students are
	346	* forced to check the status properly.
	347	*/
	348
	349	qemu_mutex_lock(&edu->thr_mutex);
	350	edu->fact = ret;
	351	qemu_mutex_unlock(&edu->thr_mutex);
d73415a3	352	qatomic_and(&edu->status, ~EDU_STATUS_COMPUTING);
b30934cb	353
2482aeea PB	354	/* Clear COMPUTING flag before checking IRQFACT. */
	355	smp_mb__after_rmw();
	356
d73415a3	357	if (qatomic_read(&edu->status) & EDU_STATUS_IRQFACT) {
b30934cb JS	358	qemu_mutex_lock_iothread();
	359	edu_raise_irq(edu, FACT_IRQ);
	360	qemu_mutex_unlock_iothread();
	361	}
	362	}
	363
	364	return NULL;
	365	}
	366
f922254c	367	static void pci_edu_realize(PCIDevice pdev, Error *errp)
b30934cb	368	{
a519e389	369	EduState *edu = EDU(pdev);
b30934cb JS	370	uint8_t *pci_conf = pdev->config;
b30934cb JS	371
c25a67f0 PB	372	pci_config_set_interrupt_pin(pci_conf, 1);
	373
	374	if (msi_init(pdev, 0, 1, true, false, errp)) {
	375	return;
	376	}
	377
b30934cb JS	378	timer_init_ms(&edu->dma_timer, QEMU_CLOCK_VIRTUAL, edu_dma_timer, edu);
	379
	380	qemu_mutex_init(&edu->thr_mutex);
	381	qemu_cond_init(&edu->thr_cond);
	382	qemu_thread_create(&edu->thread, "edu", edu_fact_thread,
	383	edu, QEMU_THREAD_JOINABLE);
	384
b30934cb	385	memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
de9b602e	386	"edu-mmio", 1 * MiB);
b30934cb	387	pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);
b30934cb JS	388	}
	389
	390	static void pci_edu_uninit(PCIDevice *pdev)
	391	{
a519e389	392	EduState *edu = EDU(pdev);
b30934cb JS	393
	394	qemu_mutex_lock(&edu->thr_mutex);
	395	edu->stopping = true;
	396	qemu_mutex_unlock(&edu->thr_mutex);
	397	qemu_cond_signal(&edu->thr_cond);
	398	qemu_thread_join(&edu->thread);
	399
	400	qemu_cond_destroy(&edu->thr_cond);
	401	qemu_mutex_destroy(&edu->thr_mutex);
	402
	403	timer_del(&edu->dma_timer);
812e710a	404	msi_uninit(pdev);
b30934cb JS	405	}
b30934cb JS	406
b30934cb JS	407	static void edu_instance_init(Object *obj)
	408	{
	409	EduState *edu = EDU(obj);
	410
	411	edu->dma_mask = (1UL << 28) - 1;
64a7b8de	412	object_property_add_uint64_ptr(obj, "dma_mask",
d2623129	413	&edu->dma_mask, OBJ_PROP_FLAG_READWRITE);
b30934cb JS	414	}
	415
	416	static void edu_class_init(ObjectClass class, void data)
	417	{
aae04907	418	DeviceClass *dc = DEVICE_CLASS(class);
b30934cb JS	419	PCIDeviceClass *k = PCI_DEVICE_CLASS(class);
b30934cb JS	420
f922254c	421	k->realize = pci_edu_realize;
b30934cb JS	422	k->exit = pci_edu_uninit;
	423	k->vendor_id = PCI_VENDOR_ID_QEMU;
	424	k->device_id = 0x11e8;
	425	k->revision = 0x10;
	426	k->class_id = PCI_CLASS_OTHERS;
aae04907	427	set_bit(DEVICE_CATEGORY_MISC, dc->categories);
b30934cb JS	428	}
	429
	430	static void pci_edu_register_types(void)
	431	{
fd3b02c8 EH	432	static InterfaceInfo interfaces[] = {
	433	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	434	{ },
	435	};
b30934cb	436	static const TypeInfo edu_info = {
8371158b	437	.name = TYPE_PCI_EDU_DEVICE,
b30934cb JS	438	.parent = TYPE_PCI_DEVICE,
	439	.instance_size = sizeof(EduState),
	440	.instance_init = edu_instance_init,
	441	.class_init = edu_class_init,
fd3b02c8	442	.interfaces = interfaces,
b30934cb JS	443	};
	444
	445	type_register_static(&edu_info);
	446	}
	447	type_init(pci_edu_register_types)