[mirror_qemu.git] / hw / misc / imx31_ccm.c

/*
 * IMX31 Clock Control Module
 *
 * Copyright (C) 2012 NICTA
 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 * To get the timer frequencies right, we need to emulate at least part of
 * the i.MX31 CCM.
 */

#include "qemu/osdep.h"
#include "hw/misc/imx31_ccm.h"
#include "qemu/log.h"
#include "qemu/module.h"

#define CKIH_FREQ 26000000 /* 26MHz crystal input */

#ifndef DEBUG_IMX31_CCM
#define DEBUG_IMX31_CCM 0
#endif

#define DPRINTF(fmt, args...) \
    do { \
        if (DEBUG_IMX31_CCM) { \
            fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
                                             __func__, ##args); \
        } \
    } while (0)

static const char *imx31_ccm_reg_name(uint32_t reg)
{
    static char unknown[20];

    switch (reg) {
    case IMX31_CCM_CCMR_REG:
        return "CCMR";
    case IMX31_CCM_PDR0_REG:
        return "PDR0";
    case IMX31_CCM_PDR1_REG:
        return "PDR1";
    case IMX31_CCM_RCSR_REG:
        return "RCSR";
    case IMX31_CCM_MPCTL_REG:
        return "MPCTL";
    case IMX31_CCM_UPCTL_REG:
        return "UPCTL";
    case IMX31_CCM_SPCTL_REG:
        return "SPCTL";
    case IMX31_CCM_COSR_REG:
        return "COSR";
    case IMX31_CCM_CGR0_REG:
        return "CGR0";
    case IMX31_CCM_CGR1_REG:
        return "CGR1";
    case IMX31_CCM_CGR2_REG:
        return "CGR2";
    case IMX31_CCM_WIMR_REG:
        return "WIMR";
    case IMX31_CCM_LDC_REG:
        return "LDC";
    case IMX31_CCM_DCVR0_REG:
        return "DCVR0";
    case IMX31_CCM_DCVR1_REG:
        return "DCVR1";
    case IMX31_CCM_DCVR2_REG:
        return "DCVR2";
    case IMX31_CCM_DCVR3_REG:
        return "DCVR3";
    case IMX31_CCM_LTR0_REG:
        return "LTR0";
    case IMX31_CCM_LTR1_REG:
        return "LTR1";
    case IMX31_CCM_LTR2_REG:
        return "LTR2";
    case IMX31_CCM_LTR3_REG:
        return "LTR3";
    case IMX31_CCM_LTBR0_REG:
        return "LTBR0";
    case IMX31_CCM_LTBR1_REG:
        return "LTBR1";
    case IMX31_CCM_PMCR0_REG:
        return "PMCR0";
    case IMX31_CCM_PMCR1_REG:
        return "PMCR1";
    case IMX31_CCM_PDR2_REG:
        return "PDR2";
    default:
        sprintf(unknown, "[%d ?]", reg);
        return unknown;
    }
}

static const VMStateDescription vmstate_imx31_ccm = {
    .name = TYPE_IMX31_CCM,
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
        VMSTATE_END_OF_LIST()
    },
};

static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
{
    uint32_t freq = 0;
    IMX31CCMState *s = IMX31_CCM(dev);

    if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) {
        if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) {
            freq = CKIL_FREQ;
            if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) {
                freq *= 1024;
            }
        } 
    } else {
        freq = CKIH_FREQ;
    }

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
                            imx31_ccm_get_pll_ref_clk(dev));

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) ||
        !(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) {
        freq = imx31_ccm_get_pll_ref_clk(dev);
    } else {
        freq = imx31_ccm_get_mpll_clk(dev);
    }

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    freq = imx31_ccm_get_mcu_main_clk(dev)
           / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    freq = imx31_ccm_get_hclk_clk(dev)
           / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
{
    uint32_t freq = 0;

    switch (clock) {
    case CLK_NONE:
        break;
    case CLK_IPG:
    case CLK_IPG_HIGH:
        freq = imx31_ccm_get_ipg_clk(dev);
        break;
    case CLK_32k:
        freq = CKIL_FREQ;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
                      TYPE_IMX31_CCM, __func__, clock);
        break;
    }

    DPRINTF("Clock = %d) = %d\n", clock, freq);

    return freq;
}

static void imx31_ccm_reset(DeviceState *dev)
{
    IMX31CCMState *s = IMX31_CCM(dev);

    DPRINTF("()\n");

    memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG);

    s->reg[IMX31_CCM_CCMR_REG]   = 0x074b0b7d;
    s->reg[IMX31_CCM_PDR0_REG]   = 0xff870b48;
    s->reg[IMX31_CCM_PDR1_REG]   = 0x49fcfe7f;
    s->reg[IMX31_CCM_RCSR_REG]   = 0x007f0000;
    s->reg[IMX31_CCM_MPCTL_REG]  = 0x04001800;
    s->reg[IMX31_CCM_UPCTL_REG]  = 0x04051c03;
    s->reg[IMX31_CCM_SPCTL_REG]  = 0x04043001;
    s->reg[IMX31_CCM_COSR_REG]   = 0x00000280;
    s->reg[IMX31_CCM_CGR0_REG]   = 0xffffffff;
    s->reg[IMX31_CCM_CGR1_REG]   = 0xffffffff;
    s->reg[IMX31_CCM_CGR2_REG]   = 0xffffffff;
    s->reg[IMX31_CCM_WIMR_REG]   = 0xffffffff;
    s->reg[IMX31_CCM_LTR1_REG]   = 0x00004040;
    s->reg[IMX31_CCM_PMCR0_REG]  = 0x80209828;
    s->reg[IMX31_CCM_PMCR1_REG]  = 0x00aa0000;
    s->reg[IMX31_CCM_PDR2_REG]   = 0x00000285;
}

static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
{
    uint32_t value = 0;
    IMX31CCMState *s = (IMX31CCMState *)opaque;

    if ((offset >> 2) < IMX31_CCM_MAX_REG) {
        value = s->reg[offset >> 2];
    } else {
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
    }

    DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
            value);

    return (uint64_t)value;
}

static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
                            unsigned size)
{
    IMX31CCMState *s = (IMX31CCMState *)opaque;

    DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
            (uint32_t)value);

    switch (offset >> 2) {
    case IMX31_CCM_CCMR_REG:
        s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF | (value & 0x3b6fdfff);
        break;
    case IMX31_CCM_PDR0_REG:
        s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff;
        break;
    case IMX31_CCM_PDR1_REG:
        s->reg[IMX31_CCM_PDR1_REG] = value;
        break;
    case IMX31_CCM_MPCTL_REG:
        s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff;
        break;
    case IMX31_CCM_SPCTL_REG:
        s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff;
        break;
    case IMX31_CCM_CGR0_REG:
        s->reg[IMX31_CCM_CGR0_REG] = value;
        break;
    case IMX31_CCM_CGR1_REG:
        s->reg[IMX31_CCM_CGR1_REG] = value;
        break;
    case IMX31_CCM_CGR2_REG:
        s->reg[IMX31_CCM_CGR2_REG] = value;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
        break;
    }
}

static const struct MemoryRegionOps imx31_ccm_ops = {
    .read = imx31_ccm_read,
    .write = imx31_ccm_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        /*
         * Our device would not work correctly if the guest was doing
         * unaligned access. This might not be a limitation on the real
         * device but in practice there is no reason for a guest to access
         * this device unaligned.
         */
        .min_access_size = 4,
        .max_access_size = 4,
        .unaligned = false,
    },

};

static void imx31_ccm_init(Object *obj)
{
    DeviceState *dev = DEVICE(obj);
    SysBusDevice *sd = SYS_BUS_DEVICE(obj);
    IMX31CCMState *s = IMX31_CCM(obj);

    memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s,
                          TYPE_IMX31_CCM, 0x1000);
    sysbus_init_mmio(sd, &s->iomem);
}

static void imx31_ccm_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc  = DEVICE_CLASS(klass);
    IMXCCMClass *ccm = IMX_CCM_CLASS(klass);

    dc->reset = imx31_ccm_reset;
    dc->vmsd  = &vmstate_imx31_ccm;
    dc->desc  = "i.MX31 Clock Control Module";

    ccm->get_clock_frequency = imx31_ccm_get_clock_frequency;
}

static const TypeInfo imx31_ccm_info = {
    .name          = TYPE_IMX31_CCM,
    .parent        = TYPE_IMX_CCM,
    .instance_size = sizeof(IMX31CCMState),
    .instance_init = imx31_ccm_init,
    .class_init    = imx31_ccm_class_init,
};

static void imx31_ccm_register_types(void)
{
    type_register_static(&imx31_ccm_info);
}

type_init(imx31_ccm_register_types)
Commit	Line	Data
cb54d868 JCD	1	/*
	2	* IMX31 Clock Control Module
	3	*
	4	* Copyright (C) 2012 NICTA
	5	* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
	6	*
	7	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	8	* See the COPYING file in the top-level directory.
	9	*
	10	* To get the timer frequencies right, we need to emulate at least part of
	11	* the i.MX31 CCM.
	12	*/
	13
8ef94f0b	14	#include "qemu/osdep.h"
cb54d868	15	#include "hw/misc/imx31_ccm.h"
03dd024f	16	#include "qemu/log.h"
0b8fa32f	17	#include "qemu/module.h"
cb54d868 JCD	18
	19	#define CKIH_FREQ 26000000 /* 26MHz crystal input */
	20
	21	#ifndef DEBUG_IMX31_CCM
	22	#define DEBUG_IMX31_CCM 0
	23	#endif
	24
	25	#define DPRINTF(fmt, args...) \
	26	do { \
	27	if (DEBUG_IMX31_CCM) { \
	28	fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
	29	__func__, ##args); \
	30	} \
	31	} while (0)
	32
d675765a	33	static const char *imx31_ccm_reg_name(uint32_t reg)
cb54d868	34	{
fea01f96 JCD	35	static char unknown[20];
fea01f96 JCD	36
cb54d868	37	switch (reg) {
fea01f96	38	case IMX31_CCM_CCMR_REG:
cb54d868	39	return "CCMR";
fea01f96	40	case IMX31_CCM_PDR0_REG:
cb54d868	41	return "PDR0";
fea01f96	42	case IMX31_CCM_PDR1_REG:
cb54d868	43	return "PDR1";
fea01f96	44	case IMX31_CCM_RCSR_REG:
cb54d868	45	return "RCSR";
fea01f96	46	case IMX31_CCM_MPCTL_REG:
cb54d868	47	return "MPCTL";
fea01f96	48	case IMX31_CCM_UPCTL_REG:
cb54d868	49	return "UPCTL";
fea01f96	50	case IMX31_CCM_SPCTL_REG:
cb54d868	51	return "SPCTL";
fea01f96	52	case IMX31_CCM_COSR_REG:
cb54d868	53	return "COSR";
fea01f96	54	case IMX31_CCM_CGR0_REG:
cb54d868	55	return "CGR0";
fea01f96	56	case IMX31_CCM_CGR1_REG:
cb54d868	57	return "CGR1";
fea01f96	58	case IMX31_CCM_CGR2_REG:
cb54d868	59	return "CGR2";
fea01f96	60	case IMX31_CCM_WIMR_REG:
cb54d868	61	return "WIMR";
fea01f96	62	case IMX31_CCM_LDC_REG:
cb54d868	63	return "LDC";
fea01f96	64	case IMX31_CCM_DCVR0_REG:
cb54d868	65	return "DCVR0";
fea01f96	66	case IMX31_CCM_DCVR1_REG:
cb54d868	67	return "DCVR1";
fea01f96	68	case IMX31_CCM_DCVR2_REG:
cb54d868	69	return "DCVR2";
fea01f96	70	case IMX31_CCM_DCVR3_REG:
cb54d868	71	return "DCVR3";
fea01f96	72	case IMX31_CCM_LTR0_REG:
cb54d868	73	return "LTR0";
fea01f96	74	case IMX31_CCM_LTR1_REG:
cb54d868	75	return "LTR1";
fea01f96	76	case IMX31_CCM_LTR2_REG:
cb54d868	77	return "LTR2";
fea01f96	78	case IMX31_CCM_LTR3_REG:
cb54d868	79	return "LTR3";
fea01f96	80	case IMX31_CCM_LTBR0_REG:
cb54d868	81	return "LTBR0";
fea01f96	82	case IMX31_CCM_LTBR1_REG:
cb54d868	83	return "LTBR1";
fea01f96	84	case IMX31_CCM_PMCR0_REG:
cb54d868	85	return "PMCR0";
fea01f96	86	case IMX31_CCM_PMCR1_REG:
cb54d868	87	return "PMCR1";
fea01f96	88	case IMX31_CCM_PDR2_REG:
cb54d868 JCD	89	return "PDR2";
cb54d868 JCD	90	default:
fea01f96 JCD	91	sprintf(unknown, "[%d ?]", reg);
fea01f96 JCD	92	return unknown;
cb54d868 JCD	93	}
	94	}
	95
	96	static const VMStateDescription vmstate_imx31_ccm = {
	97	.name = TYPE_IMX31_CCM,
fea01f96 JCD	98	.version_id = 2,
fea01f96 JCD	99	.minimum_version_id = 2,
cb54d868	100	.fields = (VMStateField[]) {
fea01f96	101	VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
cb54d868 JCD	102	VMSTATE_END_OF_LIST()
	103	},
	104	};
	105
	106	static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
	107	{
	108	uint32_t freq = 0;
	109	IMX31CCMState *s = IMX31_CCM(dev);
	110
fea01f96 JCD	111	if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) {
fea01f96 JCD	112	if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) {
cb54d868	113	freq = CKIL_FREQ;
fea01f96	114	if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) {
cb54d868 JCD	115	freq *= 1024;
	116	}
	117	}
	118	} else {
	119	freq = CKIH_FREQ;
	120	}
	121
	122	DPRINTF("freq = %d\n", freq);
	123
	124	return freq;
	125	}
	126
	127	static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
	128	{
	129	uint32_t freq;
	130	IMX31CCMState *s = IMX31_CCM(dev);
	131
fea01f96 JCD	132	freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
fea01f96 JCD	133	imx31_ccm_get_pll_ref_clk(dev));
cb54d868 JCD	134
	135	DPRINTF("freq = %d\n", freq);
	136
	137	return freq;
	138	}
	139
	140	static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
	141	{
	142	uint32_t freq;
	143	IMX31CCMState *s = IMX31_CCM(dev);
	144
fea01f96 JCD	145	if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) \|\|
fea01f96 JCD	146	!(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) {
cb54d868 JCD	147	freq = imx31_ccm_get_pll_ref_clk(dev);
	148	} else {
	149	freq = imx31_ccm_get_mpll_clk(dev);
	150	}
	151
	152	DPRINTF("freq = %d\n", freq);
	153
	154	return freq;
	155	}
	156
cb54d868 JCD	157	static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
	158	{
	159	uint32_t freq;
	160	IMX31CCMState *s = IMX31_CCM(dev);
	161
fea01f96 JCD	162	freq = imx31_ccm_get_mcu_main_clk(dev)
fea01f96 JCD	163	/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
cb54d868 JCD	164
	165	DPRINTF("freq = %d\n", freq);
	166
	167	return freq;
	168	}
	169
	170	static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
	171	{
	172	uint32_t freq;
	173	IMX31CCMState *s = IMX31_CCM(dev);
	174
fea01f96 JCD	175	freq = imx31_ccm_get_hclk_clk(dev)
fea01f96 JCD	176	/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
cb54d868 JCD	177
	178	DPRINTF("freq = %d\n", freq);
	179
	180	return freq;
	181	}
	182
	183	static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
	184	{
	185	uint32_t freq = 0;
	186
	187	switch (clock) {
c91a5883	188	case CLK_NONE:
cb54d868	189	break;
cb54d868	190	case CLK_IPG:
d552f675	191	case CLK_IPG_HIGH:
cb54d868 JCD	192	freq = imx31_ccm_get_ipg_clk(dev);
	193	break;
	194	case CLK_32k:
	195	freq = CKIL_FREQ;
	196	break;
	197	default:
	198	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
	199	TYPE_IMX31_CCM, __func__, clock);
	200	break;
	201	}
	202
	203	DPRINTF("Clock = %d) = %d\n", clock, freq);
	204
	205	return freq;
	206	}
	207
	208	static void imx31_ccm_reset(DeviceState *dev)
	209	{
	210	IMX31CCMState *s = IMX31_CCM(dev);
	211
	212	DPRINTF("()\n");
	213
fea01f96 JCD	214	memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG);
	215
	216	s->reg[IMX31_CCM_CCMR_REG] = 0x074b0b7d;
	217	s->reg[IMX31_CCM_PDR0_REG] = 0xff870b48;
	218	s->reg[IMX31_CCM_PDR1_REG] = 0x49fcfe7f;
	219	s->reg[IMX31_CCM_RCSR_REG] = 0x007f0000;
	220	s->reg[IMX31_CCM_MPCTL_REG] = 0x04001800;
	221	s->reg[IMX31_CCM_UPCTL_REG] = 0x04051c03;
	222	s->reg[IMX31_CCM_SPCTL_REG] = 0x04043001;
	223	s->reg[IMX31_CCM_COSR_REG] = 0x00000280;
	224	s->reg[IMX31_CCM_CGR0_REG] = 0xffffffff;
	225	s->reg[IMX31_CCM_CGR1_REG] = 0xffffffff;
	226	s->reg[IMX31_CCM_CGR2_REG] = 0xffffffff;
	227	s->reg[IMX31_CCM_WIMR_REG] = 0xffffffff;
	228	s->reg[IMX31_CCM_LTR1_REG] = 0x00004040;
	229	s->reg[IMX31_CCM_PMCR0_REG] = 0x80209828;
	230	s->reg[IMX31_CCM_PMCR1_REG] = 0x00aa0000;
	231	s->reg[IMX31_CCM_PDR2_REG] = 0x00000285;
cb54d868 JCD	232	}
	233
	234	static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
	235	{
3a87d009	236	uint32_t value = 0;
cb54d868 JCD	237	IMX31CCMState s = (IMX31CCMState )opaque;
cb54d868 JCD	238
fea01f96 JCD	239	if ((offset >> 2) < IMX31_CCM_MAX_REG) {
	240	value = s->reg[offset >> 2];
	241	} else {
cb54d868 JCD	242	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
cb54d868 JCD	243	HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
cb54d868 JCD	244	}
	245
	246	DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
	247	value);
	248
	249	return (uint64_t)value;
	250	}
	251
	252	static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
	253	unsigned size)
	254	{
	255	IMX31CCMState s = (IMX31CCMState )opaque;
	256
	257	DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
	258	(uint32_t)value);
	259
	260	switch (offset >> 2) {
fea01f96 JCD	261	case IMX31_CCM_CCMR_REG:
fea01f96 JCD	262	s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF \| (value & 0x3b6fdfff);
cb54d868	263	break;
fea01f96 JCD	264	case IMX31_CCM_PDR0_REG:
fea01f96 JCD	265	s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff;
cb54d868	266	break;
fea01f96 JCD	267	case IMX31_CCM_PDR1_REG:
fea01f96 JCD	268	s->reg[IMX31_CCM_PDR1_REG] = value;
cb54d868	269	break;
fea01f96 JCD	270	case IMX31_CCM_MPCTL_REG:
fea01f96 JCD	271	s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff;
cb54d868	272	break;
fea01f96 JCD	273	case IMX31_CCM_SPCTL_REG:
fea01f96 JCD	274	s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff;
cb54d868	275	break;
fea01f96 JCD	276	case IMX31_CCM_CGR0_REG:
fea01f96 JCD	277	s->reg[IMX31_CCM_CGR0_REG] = value;
cb54d868	278	break;
fea01f96 JCD	279	case IMX31_CCM_CGR1_REG:
fea01f96 JCD	280	s->reg[IMX31_CCM_CGR1_REG] = value;
cb54d868	281	break;
fea01f96 JCD	282	case IMX31_CCM_CGR2_REG:
fea01f96 JCD	283	s->reg[IMX31_CCM_CGR2_REG] = value;
cb54d868 JCD	284	break;
	285	default:
	286	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
	287	HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
	288	break;
	289	}
	290	}
	291
	292	static const struct MemoryRegionOps imx31_ccm_ops = {
	293	.read = imx31_ccm_read,
	294	.write = imx31_ccm_write,
	295	.endianness = DEVICE_NATIVE_ENDIAN,
	296	.valid = {
	297	/*
	298	* Our device would not work correctly if the guest was doing
	299	* unaligned access. This might not be a limitation on the real
	300	* device but in practice there is no reason for a guest to access
	301	* this device unaligned.
	302	*/
	303	.min_access_size = 4,
	304	.max_access_size = 4,
	305	.unaligned = false,
	306	},
	307
	308	};
	309
	310	static void imx31_ccm_init(Object *obj)
	311	{
	312	DeviceState *dev = DEVICE(obj);
	313	SysBusDevice *sd = SYS_BUS_DEVICE(obj);
	314	IMX31CCMState *s = IMX31_CCM(obj);
	315
	316	memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s,
	317	TYPE_IMX31_CCM, 0x1000);
	318	sysbus_init_mmio(sd, &s->iomem);
	319	}
	320
	321	static void imx31_ccm_class_init(ObjectClass klass, void data)
	322	{
	323	DeviceClass *dc = DEVICE_CLASS(klass);
	324	IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
	325
	326	dc->reset = imx31_ccm_reset;
	327	dc->vmsd = &vmstate_imx31_ccm;
	328	dc->desc = "i.MX31 Clock Control Module";
	329
	330	ccm->get_clock_frequency = imx31_ccm_get_clock_frequency;
	331	}
	332
	333	static const TypeInfo imx31_ccm_info = {
	334	.name = TYPE_IMX31_CCM,
	335	.parent = TYPE_IMX_CCM,
	336	.instance_size = sizeof(IMX31CCMState),
	337	.instance_init = imx31_ccm_init,
	338	.class_init = imx31_ccm_class_init,
	339	};
	340
	341	static void imx31_ccm_register_types(void)
	342	{
	343	type_register_static(&imx31_ccm_info);
	344	}
	345
	346	type_init(imx31_ccm_register_types)