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cb54d868 JCD |
1 | /* |
2 | * IMX31 Clock Control Module | |
3 | * | |
4 | * Copyright (C) 2012 NICTA | |
5 | * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> | |
6 | * | |
7 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
8 | * See the COPYING file in the top-level directory. | |
9 | * | |
10 | * To get the timer frequencies right, we need to emulate at least part of | |
11 | * the i.MX31 CCM. | |
12 | */ | |
13 | ||
8ef94f0b | 14 | #include "qemu/osdep.h" |
cb54d868 | 15 | #include "hw/misc/imx31_ccm.h" |
d6454270 | 16 | #include "migration/vmstate.h" |
03dd024f | 17 | #include "qemu/log.h" |
0b8fa32f | 18 | #include "qemu/module.h" |
cb54d868 JCD |
19 | |
20 | #define CKIH_FREQ 26000000 /* 26MHz crystal input */ | |
21 | ||
22 | #ifndef DEBUG_IMX31_CCM | |
23 | #define DEBUG_IMX31_CCM 0 | |
24 | #endif | |
25 | ||
26 | #define DPRINTF(fmt, args...) \ | |
27 | do { \ | |
28 | if (DEBUG_IMX31_CCM) { \ | |
29 | fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \ | |
30 | __func__, ##args); \ | |
31 | } \ | |
32 | } while (0) | |
33 | ||
d675765a | 34 | static const char *imx31_ccm_reg_name(uint32_t reg) |
cb54d868 | 35 | { |
fea01f96 JCD |
36 | static char unknown[20]; |
37 | ||
cb54d868 | 38 | switch (reg) { |
fea01f96 | 39 | case IMX31_CCM_CCMR_REG: |
cb54d868 | 40 | return "CCMR"; |
fea01f96 | 41 | case IMX31_CCM_PDR0_REG: |
cb54d868 | 42 | return "PDR0"; |
fea01f96 | 43 | case IMX31_CCM_PDR1_REG: |
cb54d868 | 44 | return "PDR1"; |
fea01f96 | 45 | case IMX31_CCM_RCSR_REG: |
cb54d868 | 46 | return "RCSR"; |
fea01f96 | 47 | case IMX31_CCM_MPCTL_REG: |
cb54d868 | 48 | return "MPCTL"; |
fea01f96 | 49 | case IMX31_CCM_UPCTL_REG: |
cb54d868 | 50 | return "UPCTL"; |
fea01f96 | 51 | case IMX31_CCM_SPCTL_REG: |
cb54d868 | 52 | return "SPCTL"; |
fea01f96 | 53 | case IMX31_CCM_COSR_REG: |
cb54d868 | 54 | return "COSR"; |
fea01f96 | 55 | case IMX31_CCM_CGR0_REG: |
cb54d868 | 56 | return "CGR0"; |
fea01f96 | 57 | case IMX31_CCM_CGR1_REG: |
cb54d868 | 58 | return "CGR1"; |
fea01f96 | 59 | case IMX31_CCM_CGR2_REG: |
cb54d868 | 60 | return "CGR2"; |
fea01f96 | 61 | case IMX31_CCM_WIMR_REG: |
cb54d868 | 62 | return "WIMR"; |
fea01f96 | 63 | case IMX31_CCM_LDC_REG: |
cb54d868 | 64 | return "LDC"; |
fea01f96 | 65 | case IMX31_CCM_DCVR0_REG: |
cb54d868 | 66 | return "DCVR0"; |
fea01f96 | 67 | case IMX31_CCM_DCVR1_REG: |
cb54d868 | 68 | return "DCVR1"; |
fea01f96 | 69 | case IMX31_CCM_DCVR2_REG: |
cb54d868 | 70 | return "DCVR2"; |
fea01f96 | 71 | case IMX31_CCM_DCVR3_REG: |
cb54d868 | 72 | return "DCVR3"; |
fea01f96 | 73 | case IMX31_CCM_LTR0_REG: |
cb54d868 | 74 | return "LTR0"; |
fea01f96 | 75 | case IMX31_CCM_LTR1_REG: |
cb54d868 | 76 | return "LTR1"; |
fea01f96 | 77 | case IMX31_CCM_LTR2_REG: |
cb54d868 | 78 | return "LTR2"; |
fea01f96 | 79 | case IMX31_CCM_LTR3_REG: |
cb54d868 | 80 | return "LTR3"; |
fea01f96 | 81 | case IMX31_CCM_LTBR0_REG: |
cb54d868 | 82 | return "LTBR0"; |
fea01f96 | 83 | case IMX31_CCM_LTBR1_REG: |
cb54d868 | 84 | return "LTBR1"; |
fea01f96 | 85 | case IMX31_CCM_PMCR0_REG: |
cb54d868 | 86 | return "PMCR0"; |
fea01f96 | 87 | case IMX31_CCM_PMCR1_REG: |
cb54d868 | 88 | return "PMCR1"; |
fea01f96 | 89 | case IMX31_CCM_PDR2_REG: |
cb54d868 JCD |
90 | return "PDR2"; |
91 | default: | |
a88ae037 | 92 | sprintf(unknown, "[%u ?]", reg); |
fea01f96 | 93 | return unknown; |
cb54d868 JCD |
94 | } |
95 | } | |
96 | ||
97 | static const VMStateDescription vmstate_imx31_ccm = { | |
98 | .name = TYPE_IMX31_CCM, | |
fea01f96 JCD |
99 | .version_id = 2, |
100 | .minimum_version_id = 2, | |
cb54d868 | 101 | .fields = (VMStateField[]) { |
fea01f96 | 102 | VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG), |
cb54d868 JCD |
103 | VMSTATE_END_OF_LIST() |
104 | }, | |
105 | }; | |
106 | ||
107 | static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev) | |
108 | { | |
109 | uint32_t freq = 0; | |
110 | IMX31CCMState *s = IMX31_CCM(dev); | |
111 | ||
fea01f96 JCD |
112 | if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) { |
113 | if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) { | |
cb54d868 | 114 | freq = CKIL_FREQ; |
fea01f96 | 115 | if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) { |
cb54d868 JCD |
116 | freq *= 1024; |
117 | } | |
118 | } | |
119 | } else { | |
120 | freq = CKIH_FREQ; | |
121 | } | |
122 | ||
a88ae037 | 123 | DPRINTF("freq = %u\n", freq); |
cb54d868 JCD |
124 | |
125 | return freq; | |
126 | } | |
127 | ||
128 | static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev) | |
129 | { | |
130 | uint32_t freq; | |
131 | IMX31CCMState *s = IMX31_CCM(dev); | |
132 | ||
fea01f96 JCD |
133 | freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG], |
134 | imx31_ccm_get_pll_ref_clk(dev)); | |
cb54d868 | 135 | |
a88ae037 | 136 | DPRINTF("freq = %u\n", freq); |
cb54d868 JCD |
137 | |
138 | return freq; | |
139 | } | |
140 | ||
141 | static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev) | |
142 | { | |
143 | uint32_t freq; | |
144 | IMX31CCMState *s = IMX31_CCM(dev); | |
145 | ||
fea01f96 JCD |
146 | if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) || |
147 | !(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) { | |
cb54d868 JCD |
148 | freq = imx31_ccm_get_pll_ref_clk(dev); |
149 | } else { | |
150 | freq = imx31_ccm_get_mpll_clk(dev); | |
151 | } | |
152 | ||
a88ae037 | 153 | DPRINTF("freq = %u\n", freq); |
cb54d868 JCD |
154 | |
155 | return freq; | |
156 | } | |
157 | ||
cb54d868 JCD |
158 | static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev) |
159 | { | |
160 | uint32_t freq; | |
161 | IMX31CCMState *s = IMX31_CCM(dev); | |
162 | ||
fea01f96 JCD |
163 | freq = imx31_ccm_get_mcu_main_clk(dev) |
164 | / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX)); | |
cb54d868 | 165 | |
a88ae037 | 166 | DPRINTF("freq = %u\n", freq); |
cb54d868 JCD |
167 | |
168 | return freq; | |
169 | } | |
170 | ||
171 | static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev) | |
172 | { | |
173 | uint32_t freq; | |
174 | IMX31CCMState *s = IMX31_CCM(dev); | |
175 | ||
fea01f96 JCD |
176 | freq = imx31_ccm_get_hclk_clk(dev) |
177 | / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG)); | |
cb54d868 | 178 | |
a88ae037 | 179 | DPRINTF("freq = %u\n", freq); |
cb54d868 JCD |
180 | |
181 | return freq; | |
182 | } | |
183 | ||
184 | static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) | |
185 | { | |
186 | uint32_t freq = 0; | |
187 | ||
188 | switch (clock) { | |
c91a5883 | 189 | case CLK_NONE: |
cb54d868 | 190 | break; |
cb54d868 | 191 | case CLK_IPG: |
d552f675 | 192 | case CLK_IPG_HIGH: |
cb54d868 JCD |
193 | freq = imx31_ccm_get_ipg_clk(dev); |
194 | break; | |
195 | case CLK_32k: | |
196 | freq = CKIL_FREQ; | |
197 | break; | |
198 | default: | |
199 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n", | |
200 | TYPE_IMX31_CCM, __func__, clock); | |
201 | break; | |
202 | } | |
203 | ||
a88ae037 | 204 | DPRINTF("Clock = %d) = %u\n", clock, freq); |
cb54d868 JCD |
205 | |
206 | return freq; | |
207 | } | |
208 | ||
209 | static void imx31_ccm_reset(DeviceState *dev) | |
210 | { | |
211 | IMX31CCMState *s = IMX31_CCM(dev); | |
212 | ||
213 | DPRINTF("()\n"); | |
214 | ||
fea01f96 JCD |
215 | memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG); |
216 | ||
217 | s->reg[IMX31_CCM_CCMR_REG] = 0x074b0b7d; | |
218 | s->reg[IMX31_CCM_PDR0_REG] = 0xff870b48; | |
219 | s->reg[IMX31_CCM_PDR1_REG] = 0x49fcfe7f; | |
220 | s->reg[IMX31_CCM_RCSR_REG] = 0x007f0000; | |
221 | s->reg[IMX31_CCM_MPCTL_REG] = 0x04001800; | |
222 | s->reg[IMX31_CCM_UPCTL_REG] = 0x04051c03; | |
223 | s->reg[IMX31_CCM_SPCTL_REG] = 0x04043001; | |
224 | s->reg[IMX31_CCM_COSR_REG] = 0x00000280; | |
225 | s->reg[IMX31_CCM_CGR0_REG] = 0xffffffff; | |
226 | s->reg[IMX31_CCM_CGR1_REG] = 0xffffffff; | |
227 | s->reg[IMX31_CCM_CGR2_REG] = 0xffffffff; | |
228 | s->reg[IMX31_CCM_WIMR_REG] = 0xffffffff; | |
229 | s->reg[IMX31_CCM_LTR1_REG] = 0x00004040; | |
230 | s->reg[IMX31_CCM_PMCR0_REG] = 0x80209828; | |
231 | s->reg[IMX31_CCM_PMCR1_REG] = 0x00aa0000; | |
232 | s->reg[IMX31_CCM_PDR2_REG] = 0x00000285; | |
cb54d868 JCD |
233 | } |
234 | ||
235 | static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size) | |
236 | { | |
3a87d009 | 237 | uint32_t value = 0; |
cb54d868 JCD |
238 | IMX31CCMState *s = (IMX31CCMState *)opaque; |
239 | ||
fea01f96 JCD |
240 | if ((offset >> 2) < IMX31_CCM_MAX_REG) { |
241 | value = s->reg[offset >> 2]; | |
242 | } else { | |
cb54d868 JCD |
243 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
244 | HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset); | |
cb54d868 JCD |
245 | } |
246 | ||
247 | DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2), | |
248 | value); | |
249 | ||
250 | return (uint64_t)value; | |
251 | } | |
252 | ||
253 | static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value, | |
254 | unsigned size) | |
255 | { | |
256 | IMX31CCMState *s = (IMX31CCMState *)opaque; | |
257 | ||
258 | DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2), | |
259 | (uint32_t)value); | |
260 | ||
261 | switch (offset >> 2) { | |
fea01f96 JCD |
262 | case IMX31_CCM_CCMR_REG: |
263 | s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF | (value & 0x3b6fdfff); | |
cb54d868 | 264 | break; |
fea01f96 JCD |
265 | case IMX31_CCM_PDR0_REG: |
266 | s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff; | |
cb54d868 | 267 | break; |
fea01f96 JCD |
268 | case IMX31_CCM_PDR1_REG: |
269 | s->reg[IMX31_CCM_PDR1_REG] = value; | |
cb54d868 | 270 | break; |
fea01f96 JCD |
271 | case IMX31_CCM_MPCTL_REG: |
272 | s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff; | |
cb54d868 | 273 | break; |
fea01f96 JCD |
274 | case IMX31_CCM_SPCTL_REG: |
275 | s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff; | |
cb54d868 | 276 | break; |
fea01f96 JCD |
277 | case IMX31_CCM_CGR0_REG: |
278 | s->reg[IMX31_CCM_CGR0_REG] = value; | |
cb54d868 | 279 | break; |
fea01f96 JCD |
280 | case IMX31_CCM_CGR1_REG: |
281 | s->reg[IMX31_CCM_CGR1_REG] = value; | |
cb54d868 | 282 | break; |
fea01f96 JCD |
283 | case IMX31_CCM_CGR2_REG: |
284 | s->reg[IMX31_CCM_CGR2_REG] = value; | |
cb54d868 JCD |
285 | break; |
286 | default: | |
287 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" | |
288 | HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset); | |
289 | break; | |
290 | } | |
291 | } | |
292 | ||
293 | static const struct MemoryRegionOps imx31_ccm_ops = { | |
294 | .read = imx31_ccm_read, | |
295 | .write = imx31_ccm_write, | |
296 | .endianness = DEVICE_NATIVE_ENDIAN, | |
297 | .valid = { | |
298 | /* | |
299 | * Our device would not work correctly if the guest was doing | |
300 | * unaligned access. This might not be a limitation on the real | |
301 | * device but in practice there is no reason for a guest to access | |
302 | * this device unaligned. | |
303 | */ | |
304 | .min_access_size = 4, | |
305 | .max_access_size = 4, | |
306 | .unaligned = false, | |
307 | }, | |
308 | ||
309 | }; | |
310 | ||
311 | static void imx31_ccm_init(Object *obj) | |
312 | { | |
313 | DeviceState *dev = DEVICE(obj); | |
314 | SysBusDevice *sd = SYS_BUS_DEVICE(obj); | |
315 | IMX31CCMState *s = IMX31_CCM(obj); | |
316 | ||
317 | memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s, | |
318 | TYPE_IMX31_CCM, 0x1000); | |
319 | sysbus_init_mmio(sd, &s->iomem); | |
320 | } | |
321 | ||
322 | static void imx31_ccm_class_init(ObjectClass *klass, void *data) | |
323 | { | |
324 | DeviceClass *dc = DEVICE_CLASS(klass); | |
325 | IMXCCMClass *ccm = IMX_CCM_CLASS(klass); | |
326 | ||
327 | dc->reset = imx31_ccm_reset; | |
328 | dc->vmsd = &vmstate_imx31_ccm; | |
329 | dc->desc = "i.MX31 Clock Control Module"; | |
330 | ||
331 | ccm->get_clock_frequency = imx31_ccm_get_clock_frequency; | |
332 | } | |
333 | ||
334 | static const TypeInfo imx31_ccm_info = { | |
335 | .name = TYPE_IMX31_CCM, | |
336 | .parent = TYPE_IMX_CCM, | |
337 | .instance_size = sizeof(IMX31CCMState), | |
338 | .instance_init = imx31_ccm_init, | |
339 | .class_init = imx31_ccm_class_init, | |
340 | }; | |
341 | ||
342 | static void imx31_ccm_register_types(void) | |
343 | { | |
344 | type_register_static(&imx31_ccm_info); | |
345 | } | |
346 | ||
347 | type_init(imx31_ccm_register_types) |