[mirror_qemu.git] / hw / misc / imx31_ccm.c

/*
 * IMX31 Clock Control Module
 *
 * Copyright (C) 2012 NICTA
 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 * To get the timer frequencies right, we need to emulate at least part of
 * the i.MX31 CCM.
 */

#include "qemu/osdep.h"
#include "hw/misc/imx31_ccm.h"
#include "qemu/log.h"

#define CKIH_FREQ 26000000 /* 26MHz crystal input */

#ifndef DEBUG_IMX31_CCM
#define DEBUG_IMX31_CCM 0
#endif

#define DPRINTF(fmt, args...) \
    do { \
        if (DEBUG_IMX31_CCM) { \
            fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
                                             __func__, ##args); \
        } \
    } while (0)

static const char *imx31_ccm_reg_name(uint32_t reg)
{
    static char unknown[20];

    switch (reg) {
    case IMX31_CCM_CCMR_REG:
        return "CCMR";
    case IMX31_CCM_PDR0_REG:
        return "PDR0";
    case IMX31_CCM_PDR1_REG:
        return "PDR1";
    case IMX31_CCM_RCSR_REG:
        return "RCSR";
    case IMX31_CCM_MPCTL_REG:
        return "MPCTL";
    case IMX31_CCM_UPCTL_REG:
        return "UPCTL";
    case IMX31_CCM_SPCTL_REG:
        return "SPCTL";
    case IMX31_CCM_COSR_REG:
        return "COSR";
    case IMX31_CCM_CGR0_REG:
        return "CGR0";
    case IMX31_CCM_CGR1_REG:
        return "CGR1";
    case IMX31_CCM_CGR2_REG:
        return "CGR2";
    case IMX31_CCM_WIMR_REG:
        return "WIMR";
    case IMX31_CCM_LDC_REG:
        return "LDC";
    case IMX31_CCM_DCVR0_REG:
        return "DCVR0";
    case IMX31_CCM_DCVR1_REG:
        return "DCVR1";
    case IMX31_CCM_DCVR2_REG:
        return "DCVR2";
    case IMX31_CCM_DCVR3_REG:
        return "DCVR3";
    case IMX31_CCM_LTR0_REG:
        return "LTR0";
    case IMX31_CCM_LTR1_REG:
        return "LTR1";
    case IMX31_CCM_LTR2_REG:
        return "LTR2";
    case IMX31_CCM_LTR3_REG:
        return "LTR3";
    case IMX31_CCM_LTBR0_REG:
        return "LTBR0";
    case IMX31_CCM_LTBR1_REG:
        return "LTBR1";
    case IMX31_CCM_PMCR0_REG:
        return "PMCR0";
    case IMX31_CCM_PMCR1_REG:
        return "PMCR1";
    case IMX31_CCM_PDR2_REG:
        return "PDR2";
    default:
        sprintf(unknown, "[%d ?]", reg);
        return unknown;
    }
}

static const VMStateDescription vmstate_imx31_ccm = {
    .name = TYPE_IMX31_CCM,
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
        VMSTATE_END_OF_LIST()
    },
};

static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
{
    uint32_t freq = 0;
    IMX31CCMState *s = IMX31_CCM(dev);

    if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) {
        if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) {
            freq = CKIL_FREQ;
            if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) {
                freq *= 1024;
            }
        } 
    } else {
        freq = CKIH_FREQ;
    }

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
                            imx31_ccm_get_pll_ref_clk(dev));

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) ||
        !(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) {
        freq = imx31_ccm_get_pll_ref_clk(dev);
    } else {
        freq = imx31_ccm_get_mpll_clk(dev);
    }

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    freq = imx31_ccm_get_mcu_main_clk(dev)
           / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    freq = imx31_ccm_get_hclk_clk(dev)
           / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
{
    uint32_t freq = 0;

    switch (clock) {
    case CLK_NONE:
        break;
    case CLK_IPG:
    case CLK_IPG_HIGH:
        freq = imx31_ccm_get_ipg_clk(dev);
        break;
    case CLK_32k:
        freq = CKIL_FREQ;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
                      TYPE_IMX31_CCM, __func__, clock);
        break;
    }

    DPRINTF("Clock = %d) = %d\n", clock, freq);

    return freq;
}

static void imx31_ccm_reset(DeviceState *dev)
{
    IMX31CCMState *s = IMX31_CCM(dev);

    DPRINTF("()\n");

    memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG);

    s->reg[IMX31_CCM_CCMR_REG]   = 0x074b0b7d;
    s->reg[IMX31_CCM_PDR0_REG]   = 0xff870b48;
    s->reg[IMX31_CCM_PDR1_REG]   = 0x49fcfe7f;
    s->reg[IMX31_CCM_RCSR_REG]   = 0x007f0000;
    s->reg[IMX31_CCM_MPCTL_REG]  = 0x04001800;
    s->reg[IMX31_CCM_UPCTL_REG]  = 0x04051c03;
    s->reg[IMX31_CCM_SPCTL_REG]  = 0x04043001;
    s->reg[IMX31_CCM_COSR_REG]   = 0x00000280;
    s->reg[IMX31_CCM_CGR0_REG]   = 0xffffffff;
    s->reg[IMX31_CCM_CGR1_REG]   = 0xffffffff;
    s->reg[IMX31_CCM_CGR2_REG]   = 0xffffffff;
    s->reg[IMX31_CCM_WIMR_REG]   = 0xffffffff;
    s->reg[IMX31_CCM_LTR1_REG]   = 0x00004040;
    s->reg[IMX31_CCM_PMCR0_REG]  = 0x80209828;
    s->reg[IMX31_CCM_PMCR1_REG]  = 0x00aa0000;
    s->reg[IMX31_CCM_PDR2_REG]   = 0x00000285;
}

static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
{
    uint32_t value = 0;
    IMX31CCMState *s = (IMX31CCMState *)opaque;

    if ((offset >> 2) < IMX31_CCM_MAX_REG) {
        value = s->reg[offset >> 2];
    } else {
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
    }

    DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
            value);

    return (uint64_t)value;
}

static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
                            unsigned size)
{
    IMX31CCMState *s = (IMX31CCMState *)opaque;

    DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
            (uint32_t)value);

    switch (offset >> 2) {
    case IMX31_CCM_CCMR_REG:
        s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF | (value & 0x3b6fdfff);
        break;
    case IMX31_CCM_PDR0_REG:
        s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff;
        break;
    case IMX31_CCM_PDR1_REG:
        s->reg[IMX31_CCM_PDR1_REG] = value;
        break;
    case IMX31_CCM_MPCTL_REG:
        s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff;
        break;
    case IMX31_CCM_SPCTL_REG:
        s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff;
        break;
    case IMX31_CCM_CGR0_REG:
        s->reg[IMX31_CCM_CGR0_REG] = value;
        break;
    case IMX31_CCM_CGR1_REG:
        s->reg[IMX31_CCM_CGR1_REG] = value;
        break;
    case IMX31_CCM_CGR2_REG:
        s->reg[IMX31_CCM_CGR2_REG] = value;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
        break;
    }
}

static const struct MemoryRegionOps imx31_ccm_ops = {
    .read = imx31_ccm_read,
    .write = imx31_ccm_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        /*
         * Our device would not work correctly if the guest was doing
         * unaligned access. This might not be a limitation on the real
         * device but in practice there is no reason for a guest to access
         * this device unaligned.
         */
        .min_access_size = 4,
        .max_access_size = 4,
        .unaligned = false,
    },

};

static void imx31_ccm_init(Object *obj)
{
    DeviceState *dev = DEVICE(obj);
    SysBusDevice *sd = SYS_BUS_DEVICE(obj);
    IMX31CCMState *s = IMX31_CCM(obj);

    memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s,
                          TYPE_IMX31_CCM, 0x1000);
    sysbus_init_mmio(sd, &s->iomem);
}

static void imx31_ccm_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc  = DEVICE_CLASS(klass);
    IMXCCMClass *ccm = IMX_CCM_CLASS(klass);

    dc->reset = imx31_ccm_reset;
    dc->vmsd  = &vmstate_imx31_ccm;
    dc->desc  = "i.MX31 Clock Control Module";

    ccm->get_clock_frequency = imx31_ccm_get_clock_frequency;
}

static const TypeInfo imx31_ccm_info = {
    .name          = TYPE_IMX31_CCM,
    .parent        = TYPE_IMX_CCM,
    .instance_size = sizeof(IMX31CCMState),
    .instance_init = imx31_ccm_init,
    .class_init    = imx31_ccm_class_init,
};

static void imx31_ccm_register_types(void)
{
    type_register_static(&imx31_ccm_info);
}

type_init(imx31_ccm_register_types)
Commit	Line	Data
cb54d868 JCD	1	/*
	2	* IMX31 Clock Control Module
	3	*
	4	* Copyright (C) 2012 NICTA
	5	* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
	6	*
	7	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	8	* See the COPYING file in the top-level directory.
	9	*
	10	* To get the timer frequencies right, we need to emulate at least part of
	11	* the i.MX31 CCM.
	12	*/
	13
8ef94f0b	14	#include "qemu/osdep.h"
cb54d868	15	#include "hw/misc/imx31_ccm.h"
03dd024f	16	#include "qemu/log.h"
cb54d868 JCD	17
	18	#define CKIH_FREQ 26000000 /* 26MHz crystal input */
	19
	20	#ifndef DEBUG_IMX31_CCM
	21	#define DEBUG_IMX31_CCM 0
	22	#endif
	23
	24	#define DPRINTF(fmt, args...) \
	25	do { \
	26	if (DEBUG_IMX31_CCM) { \
	27	fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
	28	__func__, ##args); \
	29	} \
	30	} while (0)
	31
d675765a	32	static const char *imx31_ccm_reg_name(uint32_t reg)
cb54d868	33	{
fea01f96 JCD	34	static char unknown[20];
fea01f96 JCD	35
cb54d868	36	switch (reg) {
fea01f96	37	case IMX31_CCM_CCMR_REG:
cb54d868	38	return "CCMR";
fea01f96	39	case IMX31_CCM_PDR0_REG:
cb54d868	40	return "PDR0";
fea01f96	41	case IMX31_CCM_PDR1_REG:
cb54d868	42	return "PDR1";
fea01f96	43	case IMX31_CCM_RCSR_REG:
cb54d868	44	return "RCSR";
fea01f96	45	case IMX31_CCM_MPCTL_REG:
cb54d868	46	return "MPCTL";
fea01f96	47	case IMX31_CCM_UPCTL_REG:
cb54d868	48	return "UPCTL";
fea01f96	49	case IMX31_CCM_SPCTL_REG:
cb54d868	50	return "SPCTL";
fea01f96	51	case IMX31_CCM_COSR_REG:
cb54d868	52	return "COSR";
fea01f96	53	case IMX31_CCM_CGR0_REG:
cb54d868	54	return "CGR0";
fea01f96	55	case IMX31_CCM_CGR1_REG:
cb54d868	56	return "CGR1";
fea01f96	57	case IMX31_CCM_CGR2_REG:
cb54d868	58	return "CGR2";
fea01f96	59	case IMX31_CCM_WIMR_REG:
cb54d868	60	return "WIMR";
fea01f96	61	case IMX31_CCM_LDC_REG:
cb54d868	62	return "LDC";
fea01f96	63	case IMX31_CCM_DCVR0_REG:
cb54d868	64	return "DCVR0";
fea01f96	65	case IMX31_CCM_DCVR1_REG:
cb54d868	66	return "DCVR1";
fea01f96	67	case IMX31_CCM_DCVR2_REG:
cb54d868	68	return "DCVR2";
fea01f96	69	case IMX31_CCM_DCVR3_REG:
cb54d868	70	return "DCVR3";
fea01f96	71	case IMX31_CCM_LTR0_REG:
cb54d868	72	return "LTR0";
fea01f96	73	case IMX31_CCM_LTR1_REG:
cb54d868	74	return "LTR1";
fea01f96	75	case IMX31_CCM_LTR2_REG:
cb54d868	76	return "LTR2";
fea01f96	77	case IMX31_CCM_LTR3_REG:
cb54d868	78	return "LTR3";
fea01f96	79	case IMX31_CCM_LTBR0_REG:
cb54d868	80	return "LTBR0";
fea01f96	81	case IMX31_CCM_LTBR1_REG:
cb54d868	82	return "LTBR1";
fea01f96	83	case IMX31_CCM_PMCR0_REG:
cb54d868	84	return "PMCR0";
fea01f96	85	case IMX31_CCM_PMCR1_REG:
cb54d868	86	return "PMCR1";
fea01f96	87	case IMX31_CCM_PDR2_REG:
cb54d868 JCD	88	return "PDR2";
cb54d868 JCD	89	default:
fea01f96 JCD	90	sprintf(unknown, "[%d ?]", reg);
fea01f96 JCD	91	return unknown;
cb54d868 JCD	92	}
	93	}
	94
	95	static const VMStateDescription vmstate_imx31_ccm = {
	96	.name = TYPE_IMX31_CCM,
fea01f96 JCD	97	.version_id = 2,
fea01f96 JCD	98	.minimum_version_id = 2,
cb54d868	99	.fields = (VMStateField[]) {
fea01f96	100	VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
cb54d868 JCD	101	VMSTATE_END_OF_LIST()
	102	},
	103	};
	104
	105	static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
	106	{
	107	uint32_t freq = 0;
	108	IMX31CCMState *s = IMX31_CCM(dev);
	109
fea01f96 JCD	110	if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) {
fea01f96 JCD	111	if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) {
cb54d868	112	freq = CKIL_FREQ;
fea01f96	113	if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) {
cb54d868 JCD	114	freq *= 1024;
	115	}
	116	}
	117	} else {
	118	freq = CKIH_FREQ;
	119	}
	120
	121	DPRINTF("freq = %d\n", freq);
	122
	123	return freq;
	124	}
	125
	126	static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
	127	{
	128	uint32_t freq;
	129	IMX31CCMState *s = IMX31_CCM(dev);
	130
fea01f96 JCD	131	freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
fea01f96 JCD	132	imx31_ccm_get_pll_ref_clk(dev));
cb54d868 JCD	133
	134	DPRINTF("freq = %d\n", freq);
	135
	136	return freq;
	137	}
	138
	139	static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
	140	{
	141	uint32_t freq;
	142	IMX31CCMState *s = IMX31_CCM(dev);
	143
fea01f96 JCD	144	if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) \|\|
fea01f96 JCD	145	!(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) {
cb54d868 JCD	146	freq = imx31_ccm_get_pll_ref_clk(dev);
	147	} else {
	148	freq = imx31_ccm_get_mpll_clk(dev);
	149	}
	150
	151	DPRINTF("freq = %d\n", freq);
	152
	153	return freq;
	154	}
	155
cb54d868 JCD	156	static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
	157	{
	158	uint32_t freq;
	159	IMX31CCMState *s = IMX31_CCM(dev);
	160
fea01f96 JCD	161	freq = imx31_ccm_get_mcu_main_clk(dev)
fea01f96 JCD	162	/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
cb54d868 JCD	163
	164	DPRINTF("freq = %d\n", freq);
	165
	166	return freq;
	167	}
	168
	169	static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
	170	{
	171	uint32_t freq;
	172	IMX31CCMState *s = IMX31_CCM(dev);
	173
fea01f96 JCD	174	freq = imx31_ccm_get_hclk_clk(dev)
fea01f96 JCD	175	/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
cb54d868 JCD	176
	177	DPRINTF("freq = %d\n", freq);
	178
	179	return freq;
	180	}
	181
	182	static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
	183	{
	184	uint32_t freq = 0;
	185
	186	switch (clock) {
c91a5883	187	case CLK_NONE:
cb54d868	188	break;
cb54d868	189	case CLK_IPG:
d552f675	190	case CLK_IPG_HIGH:
cb54d868 JCD	191	freq = imx31_ccm_get_ipg_clk(dev);
	192	break;
	193	case CLK_32k:
	194	freq = CKIL_FREQ;
	195	break;
	196	default:
	197	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
	198	TYPE_IMX31_CCM, __func__, clock);
	199	break;
	200	}
	201
	202	DPRINTF("Clock = %d) = %d\n", clock, freq);
	203
	204	return freq;
	205	}
	206
	207	static void imx31_ccm_reset(DeviceState *dev)
	208	{
	209	IMX31CCMState *s = IMX31_CCM(dev);
	210
	211	DPRINTF("()\n");
	212
fea01f96 JCD	213	memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG);
	214
	215	s->reg[IMX31_CCM_CCMR_REG] = 0x074b0b7d;
	216	s->reg[IMX31_CCM_PDR0_REG] = 0xff870b48;
	217	s->reg[IMX31_CCM_PDR1_REG] = 0x49fcfe7f;
	218	s->reg[IMX31_CCM_RCSR_REG] = 0x007f0000;
	219	s->reg[IMX31_CCM_MPCTL_REG] = 0x04001800;
	220	s->reg[IMX31_CCM_UPCTL_REG] = 0x04051c03;
	221	s->reg[IMX31_CCM_SPCTL_REG] = 0x04043001;
	222	s->reg[IMX31_CCM_COSR_REG] = 0x00000280;
	223	s->reg[IMX31_CCM_CGR0_REG] = 0xffffffff;
	224	s->reg[IMX31_CCM_CGR1_REG] = 0xffffffff;
	225	s->reg[IMX31_CCM_CGR2_REG] = 0xffffffff;
	226	s->reg[IMX31_CCM_WIMR_REG] = 0xffffffff;
	227	s->reg[IMX31_CCM_LTR1_REG] = 0x00004040;
	228	s->reg[IMX31_CCM_PMCR0_REG] = 0x80209828;
	229	s->reg[IMX31_CCM_PMCR1_REG] = 0x00aa0000;
	230	s->reg[IMX31_CCM_PDR2_REG] = 0x00000285;
cb54d868 JCD	231	}
	232
	233	static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
	234	{
3a87d009	235	uint32_t value = 0;
cb54d868 JCD	236	IMX31CCMState s = (IMX31CCMState )opaque;
cb54d868 JCD	237
fea01f96 JCD	238	if ((offset >> 2) < IMX31_CCM_MAX_REG) {
	239	value = s->reg[offset >> 2];
	240	} else {
cb54d868 JCD	241	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
cb54d868 JCD	242	HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
cb54d868 JCD	243	}
	244
	245	DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
	246	value);
	247
	248	return (uint64_t)value;
	249	}
	250
	251	static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
	252	unsigned size)
	253	{
	254	IMX31CCMState s = (IMX31CCMState )opaque;
	255
	256	DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
	257	(uint32_t)value);
	258
	259	switch (offset >> 2) {
fea01f96 JCD	260	case IMX31_CCM_CCMR_REG:
fea01f96 JCD	261	s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF \| (value & 0x3b6fdfff);
cb54d868	262	break;
fea01f96 JCD	263	case IMX31_CCM_PDR0_REG:
fea01f96 JCD	264	s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff;
cb54d868	265	break;
fea01f96 JCD	266	case IMX31_CCM_PDR1_REG:
fea01f96 JCD	267	s->reg[IMX31_CCM_PDR1_REG] = value;
cb54d868	268	break;
fea01f96 JCD	269	case IMX31_CCM_MPCTL_REG:
fea01f96 JCD	270	s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff;
cb54d868	271	break;
fea01f96 JCD	272	case IMX31_CCM_SPCTL_REG:
fea01f96 JCD	273	s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff;
cb54d868	274	break;
fea01f96 JCD	275	case IMX31_CCM_CGR0_REG:
fea01f96 JCD	276	s->reg[IMX31_CCM_CGR0_REG] = value;
cb54d868	277	break;
fea01f96 JCD	278	case IMX31_CCM_CGR1_REG:
fea01f96 JCD	279	s->reg[IMX31_CCM_CGR1_REG] = value;
cb54d868	280	break;
fea01f96 JCD	281	case IMX31_CCM_CGR2_REG:
fea01f96 JCD	282	s->reg[IMX31_CCM_CGR2_REG] = value;
cb54d868 JCD	283	break;
	284	default:
	285	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
	286	HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
	287	break;
	288	}
	289	}
	290
	291	static const struct MemoryRegionOps imx31_ccm_ops = {
	292	.read = imx31_ccm_read,
	293	.write = imx31_ccm_write,
	294	.endianness = DEVICE_NATIVE_ENDIAN,
	295	.valid = {
	296	/*
	297	* Our device would not work correctly if the guest was doing
	298	* unaligned access. This might not be a limitation on the real
	299	* device but in practice there is no reason for a guest to access
	300	* this device unaligned.
	301	*/
	302	.min_access_size = 4,
	303	.max_access_size = 4,
	304	.unaligned = false,
	305	},
	306
	307	};
	308
	309	static void imx31_ccm_init(Object *obj)
	310	{
	311	DeviceState *dev = DEVICE(obj);
	312	SysBusDevice *sd = SYS_BUS_DEVICE(obj);
	313	IMX31CCMState *s = IMX31_CCM(obj);
	314
	315	memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s,
	316	TYPE_IMX31_CCM, 0x1000);
	317	sysbus_init_mmio(sd, &s->iomem);
	318	}
	319
	320	static void imx31_ccm_class_init(ObjectClass klass, void data)
	321	{
	322	DeviceClass *dc = DEVICE_CLASS(klass);
	323	IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
	324
	325	dc->reset = imx31_ccm_reset;
	326	dc->vmsd = &vmstate_imx31_ccm;
	327	dc->desc = "i.MX31 Clock Control Module";
	328
	329	ccm->get_clock_frequency = imx31_ccm_get_clock_frequency;
	330	}
	331
	332	static const TypeInfo imx31_ccm_info = {
	333	.name = TYPE_IMX31_CCM,
	334	.parent = TYPE_IMX_CCM,
	335	.instance_size = sizeof(IMX31CCMState),
	336	.instance_init = imx31_ccm_init,
	337	.class_init = imx31_ccm_class_init,
	338	};
	339
	340	static void imx31_ccm_register_types(void)
	341	{
	342	type_register_static(&imx31_ccm_info);
	343	}
	344
	345	type_init(imx31_ccm_register_types)