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Commit | Line | Data |
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6cbf4c8c CM |
1 | /* |
2 | * Inter-VM Shared Memory PCI device. | |
3 | * | |
4 | * Author: | |
5 | * Cam Macdonell <cam@cs.ualberta.ca> | |
6 | * | |
7 | * Based On: cirrus_vga.c | |
8 | * Copyright (c) 2004 Fabrice Bellard | |
9 | * Copyright (c) 2004 Makoto Suzuki (suzu) | |
10 | * | |
11 | * and rtl8139.c | |
12 | * Copyright (c) 2006 Igor Kovalenko | |
13 | * | |
14 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
15 | * |
16 | * Contributions after 2012-01-13 are licensed under the terms of the | |
17 | * GNU GPL, version 2 or (at your option) any later version. | |
6cbf4c8c | 18 | */ |
0b8fa32f | 19 | |
0d1c9782 | 20 | #include "qemu/osdep.h" |
519abcdf | 21 | #include "qemu/units.h" |
da34e65c | 22 | #include "qapi/error.h" |
f348b6d1 | 23 | #include "qemu/cutils.h" |
83c9f4ca | 24 | #include "hw/pci/pci.h" |
a27bd6c7 | 25 | #include "hw/qdev-properties.h" |
ce35e229 | 26 | #include "hw/qdev-properties-system.h" |
660c97ee | 27 | #include "hw/pci/msi.h" |
83c9f4ca | 28 | #include "hw/pci/msix.h" |
9c17d615 | 29 | #include "sysemu/kvm.h" |
795c40b8 | 30 | #include "migration/blocker.h" |
d6454270 | 31 | #include "migration/vmstate.h" |
d49b6836 | 32 | #include "qemu/error-report.h" |
1de7afc9 | 33 | #include "qemu/event_notifier.h" |
0b8fa32f | 34 | #include "qemu/module.h" |
5503e285 | 35 | #include "qom/object_interfaces.h" |
4d43a603 | 36 | #include "chardev/char-fe.h" |
d9453c93 MAL |
37 | #include "sysemu/hostmem.h" |
38 | #include "qapi/visitor.h" | |
6cbf4c8c | 39 | |
5105b1d8 | 40 | #include "hw/misc/ivshmem.h" |
db1015e9 | 41 | #include "qom/object.h" |
5105b1d8 | 42 | |
b8ef62a9 PB |
43 | #define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET |
44 | #define PCI_DEVICE_ID_IVSHMEM 0x1110 | |
45 | ||
cd9953f7 | 46 | #define IVSHMEM_MAX_PEERS UINT16_MAX |
6cbf4c8c CM |
47 | #define IVSHMEM_IOEVENTFD 0 |
48 | #define IVSHMEM_MSI 1 | |
49 | ||
6cbf4c8c CM |
50 | #define IVSHMEM_REG_BAR_SIZE 0x100 |
51 | ||
a4fa93bf MA |
52 | #define IVSHMEM_DEBUG 0 |
53 | #define IVSHMEM_DPRINTF(fmt, ...) \ | |
54 | do { \ | |
55 | if (IVSHMEM_DEBUG) { \ | |
56 | printf("IVSHMEM: " fmt, ## __VA_ARGS__); \ | |
57 | } \ | |
58 | } while (0) | |
6cbf4c8c | 59 | |
5400c02b | 60 | #define TYPE_IVSHMEM_COMMON "ivshmem-common" |
db1015e9 | 61 | typedef struct IVShmemState IVShmemState; |
8110fa1d EH |
62 | DECLARE_INSTANCE_CHECKER(IVShmemState, IVSHMEM_COMMON, |
63 | TYPE_IVSHMEM_COMMON) | |
5400c02b MA |
64 | |
65 | #define TYPE_IVSHMEM_PLAIN "ivshmem-plain" | |
8110fa1d EH |
66 | DECLARE_INSTANCE_CHECKER(IVShmemState, IVSHMEM_PLAIN, |
67 | TYPE_IVSHMEM_PLAIN) | |
5400c02b MA |
68 | |
69 | #define TYPE_IVSHMEM_DOORBELL "ivshmem-doorbell" | |
8110fa1d EH |
70 | DECLARE_INSTANCE_CHECKER(IVShmemState, IVSHMEM_DOORBELL, |
71 | TYPE_IVSHMEM_DOORBELL) | |
5400c02b | 72 | |
eb3fedf3 | 73 | #define TYPE_IVSHMEM "ivshmem" |
8110fa1d EH |
74 | DECLARE_INSTANCE_CHECKER(IVShmemState, IVSHMEM, |
75 | TYPE_IVSHMEM) | |
eb3fedf3 | 76 | |
6cbf4c8c CM |
77 | typedef struct Peer { |
78 | int nb_eventfds; | |
563027cc | 79 | EventNotifier *eventfds; |
6cbf4c8c CM |
80 | } Peer; |
81 | ||
0f57350e | 82 | typedef struct MSIVector { |
6cbf4c8c | 83 | PCIDevice *pdev; |
660c97ee | 84 | int virq; |
089fd803 | 85 | bool unmasked; |
0f57350e | 86 | } MSIVector; |
6cbf4c8c | 87 | |
db1015e9 | 88 | struct IVShmemState { |
b7578eaa AF |
89 | /*< private >*/ |
90 | PCIDevice parent_obj; | |
91 | /*< public >*/ | |
92 | ||
ddc85284 MA |
93 | uint32_t features; |
94 | ||
95 | /* exactly one of these two may be set */ | |
96 | HostMemoryBackend *hostmem; /* with interrupts */ | |
becdfa00 | 97 | CharBackend server_chr; /* without interrupts */ |
ddc85284 MA |
98 | |
99 | /* registers */ | |
6cbf4c8c CM |
100 | uint32_t intrmask; |
101 | uint32_t intrstatus; | |
ddc85284 | 102 | int vm_id; |
6cbf4c8c | 103 | |
ddc85284 MA |
104 | /* BARs */ |
105 | MemoryRegion ivshmem_mmio; /* BAR 0 (registers) */ | |
c2d8019c MA |
106 | MemoryRegion *ivshmem_bar2; /* BAR 2 (shared memory) */ |
107 | MemoryRegion server_bar2; /* used with server_chr */ | |
6cbf4c8c | 108 | |
ddc85284 | 109 | /* interrupt support */ |
6cbf4c8c | 110 | Peer *peers; |
cd9953f7 | 111 | int nb_peers; /* space in @peers[] */ |
6cbf4c8c | 112 | uint32_t vectors; |
0f57350e | 113 | MSIVector *msi_vectors; |
ee276391 MA |
114 | uint64_t msg_buf; /* buffer for receiving server messages */ |
115 | int msg_buffered_bytes; /* #bytes in @msg_buf */ | |
6cbf4c8c | 116 | |
ddc85284 | 117 | /* migration stuff */ |
2a845da7 | 118 | OnOffAuto master; |
38e0735e | 119 | Error *migration_blocker; |
db1015e9 | 120 | }; |
6cbf4c8c CM |
121 | |
122 | /* registers for the Inter-VM shared memory device */ | |
123 | enum ivshmem_registers { | |
124 | INTRMASK = 0, | |
125 | INTRSTATUS = 4, | |
126 | IVPOSITION = 8, | |
127 | DOORBELL = 12, | |
128 | }; | |
129 | ||
130 | static inline uint32_t ivshmem_has_feature(IVShmemState *ivs, | |
131 | unsigned int feature) { | |
132 | return (ivs->features & (1 << feature)); | |
133 | } | |
134 | ||
2a845da7 MA |
135 | static inline bool ivshmem_is_master(IVShmemState *s) |
136 | { | |
137 | assert(s->master != ON_OFF_AUTO_AUTO); | |
138 | return s->master == ON_OFF_AUTO_ON; | |
139 | } | |
140 | ||
6cbf4c8c CM |
141 | static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val) |
142 | { | |
143 | IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val); | |
144 | ||
145 | s->intrmask = val; | |
6cbf4c8c CM |
146 | } |
147 | ||
148 | static uint32_t ivshmem_IntrMask_read(IVShmemState *s) | |
149 | { | |
150 | uint32_t ret = s->intrmask; | |
151 | ||
152 | IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret); | |
6cbf4c8c CM |
153 | return ret; |
154 | } | |
155 | ||
156 | static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val) | |
157 | { | |
158 | IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val); | |
159 | ||
160 | s->intrstatus = val; | |
6cbf4c8c CM |
161 | } |
162 | ||
163 | static uint32_t ivshmem_IntrStatus_read(IVShmemState *s) | |
164 | { | |
165 | uint32_t ret = s->intrstatus; | |
166 | ||
167 | /* reading ISR clears all interrupts */ | |
168 | s->intrstatus = 0; | |
6cbf4c8c CM |
169 | return ret; |
170 | } | |
171 | ||
a8170e5e | 172 | static void ivshmem_io_write(void *opaque, hwaddr addr, |
cb06608e | 173 | uint64_t val, unsigned size) |
6cbf4c8c CM |
174 | { |
175 | IVShmemState *s = opaque; | |
176 | ||
6cbf4c8c CM |
177 | uint16_t dest = val >> 16; |
178 | uint16_t vector = val & 0xff; | |
179 | ||
180 | addr &= 0xfc; | |
181 | ||
883f2c59 | 182 | IVSHMEM_DPRINTF("writing to addr " HWADDR_FMT_plx "\n", addr); |
6cbf4c8c CM |
183 | switch (addr) |
184 | { | |
185 | case INTRMASK: | |
186 | ivshmem_IntrMask_write(s, val); | |
187 | break; | |
188 | ||
189 | case INTRSTATUS: | |
190 | ivshmem_IntrStatus_write(s, val); | |
191 | break; | |
192 | ||
193 | case DOORBELL: | |
194 | /* check that dest VM ID is reasonable */ | |
95c8425c | 195 | if (dest >= s->nb_peers) { |
6cbf4c8c CM |
196 | IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest); |
197 | break; | |
198 | } | |
199 | ||
200 | /* check doorbell range */ | |
1b27d7a1 | 201 | if (vector < s->peers[dest].nb_eventfds) { |
563027cc PB |
202 | IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector); |
203 | event_notifier_set(&s->peers[dest].eventfds[vector]); | |
f59bb378 MAL |
204 | } else { |
205 | IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n", | |
206 | vector, dest); | |
6cbf4c8c CM |
207 | } |
208 | break; | |
209 | default: | |
883f2c59 | 210 | IVSHMEM_DPRINTF("Unhandled write " HWADDR_FMT_plx "\n", addr); |
6cbf4c8c CM |
211 | } |
212 | } | |
213 | ||
a8170e5e | 214 | static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, |
cb06608e | 215 | unsigned size) |
6cbf4c8c CM |
216 | { |
217 | ||
218 | IVShmemState *s = opaque; | |
219 | uint32_t ret; | |
220 | ||
221 | switch (addr) | |
222 | { | |
223 | case INTRMASK: | |
224 | ret = ivshmem_IntrMask_read(s); | |
225 | break; | |
226 | ||
227 | case INTRSTATUS: | |
228 | ret = ivshmem_IntrStatus_read(s); | |
229 | break; | |
230 | ||
231 | case IVPOSITION: | |
1309cf44 | 232 | ret = s->vm_id; |
6cbf4c8c CM |
233 | break; |
234 | ||
235 | default: | |
883f2c59 | 236 | IVSHMEM_DPRINTF("why are we reading " HWADDR_FMT_plx "\n", addr); |
6cbf4c8c CM |
237 | ret = 0; |
238 | } | |
239 | ||
240 | return ret; | |
241 | } | |
242 | ||
cb06608e AK |
243 | static const MemoryRegionOps ivshmem_mmio_ops = { |
244 | .read = ivshmem_io_read, | |
245 | .write = ivshmem_io_write, | |
ef80a708 | 246 | .endianness = DEVICE_LITTLE_ENDIAN, |
cb06608e AK |
247 | .impl = { |
248 | .min_access_size = 4, | |
249 | .max_access_size = 4, | |
250 | }, | |
6cbf4c8c CM |
251 | }; |
252 | ||
9940c323 MAL |
253 | static void ivshmem_vector_notify(void *opaque) |
254 | { | |
0f57350e | 255 | MSIVector *entry = opaque; |
6cbf4c8c | 256 | PCIDevice *pdev = entry->pdev; |
5400c02b | 257 | IVShmemState *s = IVSHMEM_COMMON(pdev); |
0f57350e | 258 | int vector = entry - s->msi_vectors; |
9940c323 MAL |
259 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
260 | ||
261 | if (!event_notifier_test_and_clear(n)) { | |
262 | return; | |
263 | } | |
6cbf4c8c | 264 | |
d160f3f7 | 265 | IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector); |
9940c323 | 266 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
082751e8 MA |
267 | if (msix_enabled(pdev)) { |
268 | msix_notify(pdev, vector); | |
269 | } | |
9940c323 MAL |
270 | } else { |
271 | ivshmem_IntrStatus_write(s, 1); | |
272 | } | |
6cbf4c8c CM |
273 | } |
274 | ||
660c97ee MAL |
275 | static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector, |
276 | MSIMessage msg) | |
277 | { | |
5400c02b | 278 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee MAL |
279 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
280 | MSIVector *v = &s->msi_vectors[vector]; | |
281 | int ret; | |
282 | ||
283 | IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector); | |
e6a354be LP |
284 | if (!v->pdev) { |
285 | error_report("ivshmem: vector %d route does not exist", vector); | |
286 | return -EINVAL; | |
287 | } | |
089fd803 | 288 | assert(!v->unmasked); |
660c97ee MAL |
289 | |
290 | ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev); | |
291 | if (ret < 0) { | |
292 | return ret; | |
293 | } | |
3f1fea0f | 294 | kvm_irqchip_commit_routes(kvm_state); |
660c97ee | 295 | |
089fd803 LP |
296 | ret = kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq); |
297 | if (ret < 0) { | |
298 | return ret; | |
299 | } | |
300 | v->unmasked = true; | |
301 | ||
302 | return 0; | |
660c97ee MAL |
303 | } |
304 | ||
305 | static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector) | |
306 | { | |
5400c02b | 307 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee | 308 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
e6a354be | 309 | MSIVector *v = &s->msi_vectors[vector]; |
660c97ee MAL |
310 | int ret; |
311 | ||
312 | IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector); | |
e6a354be LP |
313 | if (!v->pdev) { |
314 | error_report("ivshmem: vector %d route does not exist", vector); | |
315 | return; | |
316 | } | |
089fd803 | 317 | assert(v->unmasked); |
660c97ee | 318 | |
e6a354be | 319 | ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, v->virq); |
089fd803 | 320 | if (ret < 0) { |
660c97ee | 321 | error_report("remove_irqfd_notifier_gsi failed"); |
089fd803 | 322 | return; |
660c97ee | 323 | } |
089fd803 | 324 | v->unmasked = false; |
660c97ee MAL |
325 | } |
326 | ||
327 | static void ivshmem_vector_poll(PCIDevice *dev, | |
328 | unsigned int vector_start, | |
329 | unsigned int vector_end) | |
330 | { | |
5400c02b | 331 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee MAL |
332 | unsigned int vector; |
333 | ||
334 | IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end); | |
335 | ||
336 | vector_end = MIN(vector_end, s->vectors); | |
337 | ||
338 | for (vector = vector_start; vector < vector_end; vector++) { | |
339 | EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector]; | |
340 | ||
341 | if (!msix_is_masked(dev, vector)) { | |
342 | continue; | |
343 | } | |
344 | ||
345 | if (event_notifier_test_and_clear(notifier)) { | |
346 | msix_set_pending(dev, vector); | |
347 | } | |
348 | } | |
349 | } | |
350 | ||
9940c323 MAL |
351 | static void watch_vector_notifier(IVShmemState *s, EventNotifier *n, |
352 | int vector) | |
6cbf4c8c | 353 | { |
563027cc | 354 | int eventfd = event_notifier_get_fd(n); |
6cbf4c8c | 355 | |
3c27969b | 356 | assert(!s->msi_vectors[vector].pdev); |
9940c323 | 357 | s->msi_vectors[vector].pdev = PCI_DEVICE(s); |
6cbf4c8c | 358 | |
9940c323 MAL |
359 | qemu_set_fd_handler(eventfd, ivshmem_vector_notify, |
360 | NULL, &s->msi_vectors[vector]); | |
6cbf4c8c CM |
361 | } |
362 | ||
563027cc PB |
363 | static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i) |
364 | { | |
365 | memory_region_add_eventfd(&s->ivshmem_mmio, | |
366 | DOORBELL, | |
367 | 4, | |
368 | true, | |
369 | (posn << 16) | i, | |
753d5e14 | 370 | &s->peers[posn].eventfds[i]); |
563027cc PB |
371 | } |
372 | ||
373 | static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i) | |
374 | { | |
375 | memory_region_del_eventfd(&s->ivshmem_mmio, | |
376 | DOORBELL, | |
377 | 4, | |
378 | true, | |
379 | (posn << 16) | i, | |
753d5e14 | 380 | &s->peers[posn].eventfds[i]); |
563027cc PB |
381 | } |
382 | ||
f456179f | 383 | static void close_peer_eventfds(IVShmemState *s, int posn) |
6cbf4c8c | 384 | { |
f456179f | 385 | int i, n; |
6cbf4c8c | 386 | |
9db51b4d | 387 | assert(posn >= 0 && posn < s->nb_peers); |
f456179f | 388 | n = s->peers[posn].nb_eventfds; |
6cbf4c8c | 389 | |
9db51b4d MA |
390 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
391 | memory_region_transaction_begin(); | |
392 | for (i = 0; i < n; i++) { | |
393 | ivshmem_del_eventfd(s, posn, i); | |
394 | } | |
395 | memory_region_transaction_commit(); | |
b6a1f3a5 | 396 | } |
9db51b4d | 397 | |
f456179f | 398 | for (i = 0; i < n; i++) { |
563027cc | 399 | event_notifier_cleanup(&s->peers[posn].eventfds[i]); |
6cbf4c8c CM |
400 | } |
401 | ||
7267c094 | 402 | g_free(s->peers[posn].eventfds); |
6cbf4c8c CM |
403 | s->peers[posn].nb_eventfds = 0; |
404 | } | |
405 | ||
cd9953f7 | 406 | static void resize_peers(IVShmemState *s, int nb_peers) |
34bc07c5 | 407 | { |
cd9953f7 MA |
408 | int old_nb_peers = s->nb_peers; |
409 | int i; | |
6cbf4c8c | 410 | |
cd9953f7 MA |
411 | assert(nb_peers > old_nb_peers); |
412 | IVSHMEM_DPRINTF("bumping storage to %d peers\n", nb_peers); | |
6cbf4c8c | 413 | |
b21e2380 | 414 | s->peers = g_renew(Peer, s->peers, nb_peers); |
cd9953f7 | 415 | s->nb_peers = nb_peers; |
1300b273 | 416 | |
cd9953f7 MA |
417 | for (i = old_nb_peers; i < nb_peers; i++) { |
418 | s->peers[i].eventfds = g_new0(EventNotifier, s->vectors); | |
419 | s->peers[i].nb_eventfds = 0; | |
6cbf4c8c CM |
420 | } |
421 | } | |
422 | ||
1309cf44 MA |
423 | static void ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector, |
424 | Error **errp) | |
660c97ee MAL |
425 | { |
426 | PCIDevice *pdev = PCI_DEVICE(s); | |
def4c557 | 427 | KVMRouteChange c; |
660c97ee MAL |
428 | int ret; |
429 | ||
430 | IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector); | |
3c27969b | 431 | assert(!s->msi_vectors[vector].pdev); |
660c97ee | 432 | |
def4c557 LM |
433 | c = kvm_irqchip_begin_route_changes(kvm_state); |
434 | ret = kvm_irqchip_add_msi_route(&c, vector, pdev); | |
660c97ee | 435 | if (ret < 0) { |
1309cf44 MA |
436 | error_setg(errp, "kvm_irqchip_add_msi_route failed"); |
437 | return; | |
660c97ee | 438 | } |
def4c557 | 439 | kvm_irqchip_commit_route_changes(&c); |
660c97ee MAL |
440 | |
441 | s->msi_vectors[vector].virq = ret; | |
442 | s->msi_vectors[vector].pdev = pdev; | |
660c97ee MAL |
443 | } |
444 | ||
1309cf44 | 445 | static void setup_interrupt(IVShmemState *s, int vector, Error **errp) |
660c97ee MAL |
446 | { |
447 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
448 | bool with_irqfd = kvm_msi_via_irqfd_enabled() && | |
449 | ivshmem_has_feature(s, IVSHMEM_MSI); | |
450 | PCIDevice *pdev = PCI_DEVICE(s); | |
1309cf44 | 451 | Error *err = NULL; |
660c97ee MAL |
452 | |
453 | IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector); | |
454 | ||
455 | if (!with_irqfd) { | |
97553976 | 456 | IVSHMEM_DPRINTF("with eventfd\n"); |
9940c323 | 457 | watch_vector_notifier(s, n, vector); |
660c97ee | 458 | } else if (msix_enabled(pdev)) { |
97553976 | 459 | IVSHMEM_DPRINTF("with irqfd\n"); |
1309cf44 MA |
460 | ivshmem_add_kvm_msi_virq(s, vector, &err); |
461 | if (err) { | |
462 | error_propagate(errp, err); | |
660c97ee MAL |
463 | return; |
464 | } | |
465 | ||
466 | if (!msix_is_masked(pdev, vector)) { | |
467 | kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, | |
468 | s->msi_vectors[vector].virq); | |
1309cf44 | 469 | /* TODO handle error */ |
660c97ee MAL |
470 | } |
471 | } else { | |
472 | /* it will be delayed until msix is enabled, in write_config */ | |
97553976 | 473 | IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n"); |
660c97ee MAL |
474 | } |
475 | } | |
476 | ||
1309cf44 | 477 | static void process_msg_shmem(IVShmemState *s, int fd, Error **errp) |
6cbf4c8c | 478 | { |
8baeb22b | 479 | struct stat buf; |
5400c02b | 480 | size_t size; |
6cbf4c8c | 481 | |
c2d8019c | 482 | if (s->ivshmem_bar2) { |
1309cf44 | 483 | error_setg(errp, "server sent unexpected shared memory message"); |
ca0b7566 | 484 | close(fd); |
0f14fd71 | 485 | return; |
a2e9011b SH |
486 | } |
487 | ||
8baeb22b MA |
488 | if (fstat(fd, &buf) < 0) { |
489 | error_setg_errno(errp, errno, | |
490 | "can't determine size of shared memory sent by server"); | |
491 | close(fd); | |
492 | return; | |
493 | } | |
494 | ||
5400c02b MA |
495 | size = buf.st_size; |
496 | ||
ca0b7566 | 497 | /* mmap the region and map into the BAR2 */ |
7493bd18 PMD |
498 | if (!memory_region_init_ram_from_fd(&s->server_bar2, OBJECT(s), |
499 | "ivshmem.bar2", size, RAM_SHARED, | |
500 | fd, 0, errp)) { | |
ca0b7566 | 501 | return; |
6cbf4c8c | 502 | } |
8381d89b | 503 | |
c2d8019c | 504 | s->ivshmem_bar2 = &s->server_bar2; |
ca0b7566 MA |
505 | } |
506 | ||
1309cf44 MA |
507 | static void process_msg_disconnect(IVShmemState *s, uint16_t posn, |
508 | Error **errp) | |
ca0b7566 MA |
509 | { |
510 | IVSHMEM_DPRINTF("posn %d has gone away\n", posn); | |
9db51b4d | 511 | if (posn >= s->nb_peers || posn == s->vm_id) { |
1309cf44 | 512 | error_setg(errp, "invalid peer %d", posn); |
9db51b4d MA |
513 | return; |
514 | } | |
ca0b7566 MA |
515 | close_peer_eventfds(s, posn); |
516 | } | |
6cbf4c8c | 517 | |
1309cf44 MA |
518 | static void process_msg_connect(IVShmemState *s, uint16_t posn, int fd, |
519 | Error **errp) | |
ca0b7566 MA |
520 | { |
521 | Peer *peer = &s->peers[posn]; | |
522 | int vector; | |
9a2f0e64 | 523 | |
ca0b7566 MA |
524 | /* |
525 | * The N-th connect message for this peer comes with the file | |
526 | * descriptor for vector N-1. Count messages to find the vector. | |
527 | */ | |
528 | if (peer->nb_eventfds >= s->vectors) { | |
1309cf44 MA |
529 | error_setg(errp, "Too many eventfd received, device has %d vectors", |
530 | s->vectors); | |
ca0b7566 | 531 | close(fd); |
6f8a16d5 | 532 | return; |
6cbf4c8c | 533 | } |
ca0b7566 | 534 | vector = peer->nb_eventfds++; |
6cbf4c8c | 535 | |
ca0b7566 MA |
536 | IVSHMEM_DPRINTF("eventfds[%d][%d] = %d\n", posn, vector, fd); |
537 | event_notifier_init_fd(&peer->eventfds[vector], fd); | |
4d14cb0c | 538 | g_unix_set_fd_nonblocking(fd, true, NULL); /* msix/irqfd poll non block */ |
945001a1 | 539 | |
ca0b7566 | 540 | if (posn == s->vm_id) { |
1309cf44 MA |
541 | setup_interrupt(s, vector, errp); |
542 | /* TODO do we need to handle the error? */ | |
ca0b7566 | 543 | } |
6cbf4c8c | 544 | |
ca0b7566 MA |
545 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
546 | ivshmem_add_eventfd(s, posn, vector); | |
547 | } | |
548 | } | |
6cbf4c8c | 549 | |
1309cf44 | 550 | static void process_msg(IVShmemState *s, int64_t msg, int fd, Error **errp) |
ca0b7566 MA |
551 | { |
552 | IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd); | |
6cbf4c8c | 553 | |
ca0b7566 | 554 | if (msg < -1 || msg > IVSHMEM_MAX_PEERS) { |
1309cf44 | 555 | error_setg(errp, "server sent invalid message %" PRId64, msg); |
ca0b7566 | 556 | close(fd); |
6cbf4c8c CM |
557 | return; |
558 | } | |
559 | ||
ca0b7566 | 560 | if (msg == -1) { |
1309cf44 | 561 | process_msg_shmem(s, fd, errp); |
1ee57de4 MAL |
562 | return; |
563 | } | |
564 | ||
ca0b7566 MA |
565 | if (msg >= s->nb_peers) { |
566 | resize_peers(s, msg + 1); | |
567 | } | |
6cbf4c8c | 568 | |
ca0b7566 | 569 | if (fd >= 0) { |
1309cf44 | 570 | process_msg_connect(s, msg, fd, errp); |
ca0b7566 | 571 | } else { |
1309cf44 | 572 | process_msg_disconnect(s, msg, errp); |
6cbf4c8c | 573 | } |
ca0b7566 | 574 | } |
6cbf4c8c | 575 | |
ee276391 MA |
576 | static int ivshmem_can_receive(void *opaque) |
577 | { | |
578 | IVShmemState *s = opaque; | |
579 | ||
580 | assert(s->msg_buffered_bytes < sizeof(s->msg_buf)); | |
581 | return sizeof(s->msg_buf) - s->msg_buffered_bytes; | |
582 | } | |
583 | ||
ca0b7566 MA |
584 | static void ivshmem_read(void *opaque, const uint8_t *buf, int size) |
585 | { | |
586 | IVShmemState *s = opaque; | |
1309cf44 | 587 | Error *err = NULL; |
ca0b7566 MA |
588 | int fd; |
589 | int64_t msg; | |
590 | ||
ee276391 MA |
591 | assert(size >= 0 && s->msg_buffered_bytes + size <= sizeof(s->msg_buf)); |
592 | memcpy((unsigned char *)&s->msg_buf + s->msg_buffered_bytes, buf, size); | |
593 | s->msg_buffered_bytes += size; | |
594 | if (s->msg_buffered_bytes < sizeof(s->msg_buf)) { | |
ca0b7566 | 595 | return; |
6cbf4c8c | 596 | } |
ee276391 MA |
597 | msg = le64_to_cpu(s->msg_buf); |
598 | s->msg_buffered_bytes = 0; | |
ca0b7566 | 599 | |
5345fdb4 | 600 | fd = qemu_chr_fe_get_msgfd(&s->server_chr); |
ca0b7566 | 601 | |
1309cf44 MA |
602 | process_msg(s, msg, fd, &err); |
603 | if (err) { | |
604 | error_report_err(err); | |
605 | } | |
6cbf4c8c CM |
606 | } |
607 | ||
1309cf44 | 608 | static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp) |
5105b1d8 | 609 | { |
3a55fc0f MA |
610 | int64_t msg; |
611 | int n, ret; | |
612 | ||
613 | n = 0; | |
614 | do { | |
5345fdb4 MAL |
615 | ret = qemu_chr_fe_read_all(&s->server_chr, (uint8_t *)&msg + n, |
616 | sizeof(msg) - n); | |
b7b1e9dd PMD |
617 | if (ret < 0) { |
618 | if (ret == -EINTR) { | |
619 | continue; | |
620 | } | |
1309cf44 | 621 | error_setg_errno(errp, -ret, "read from server failed"); |
3a55fc0f MA |
622 | return INT64_MIN; |
623 | } | |
624 | n += ret; | |
625 | } while (n < sizeof(msg)); | |
5105b1d8 | 626 | |
5345fdb4 | 627 | *pfd = qemu_chr_fe_get_msgfd(&s->server_chr); |
51af0ec9 | 628 | return le64_to_cpu(msg); |
3a55fc0f | 629 | } |
5105b1d8 | 630 | |
1309cf44 | 631 | static void ivshmem_recv_setup(IVShmemState *s, Error **errp) |
3a55fc0f | 632 | { |
1309cf44 | 633 | Error *err = NULL; |
3a55fc0f MA |
634 | int64_t msg; |
635 | int fd; | |
636 | ||
1309cf44 MA |
637 | msg = ivshmem_recv_msg(s, &fd, &err); |
638 | if (err) { | |
639 | error_propagate(errp, err); | |
640 | return; | |
641 | } | |
642 | if (msg != IVSHMEM_PROTOCOL_VERSION) { | |
643 | error_setg(errp, "server sent version %" PRId64 ", expecting %d", | |
644 | msg, IVSHMEM_PROTOCOL_VERSION); | |
645 | return; | |
646 | } | |
647 | if (fd != -1) { | |
648 | error_setg(errp, "server sent invalid version message"); | |
5105b1d8 DM |
649 | return; |
650 | } | |
651 | ||
a3feb086 MA |
652 | /* |
653 | * ivshmem-server sends the remaining initial messages in a fixed | |
654 | * order, but the device has always accepted them in any order. | |
655 | * Stay as compatible as practical, just in case people use | |
656 | * servers that behave differently. | |
657 | */ | |
658 | ||
659 | /* | |
660 | * ivshmem_device_spec.txt has always required the ID message | |
661 | * right here, and ivshmem-server has always complied. However, | |
662 | * older versions of the device accepted it out of order, but | |
663 | * broke when an interrupt setup message arrived before it. | |
664 | */ | |
665 | msg = ivshmem_recv_msg(s, &fd, &err); | |
666 | if (err) { | |
667 | error_propagate(errp, err); | |
668 | return; | |
669 | } | |
670 | if (fd != -1 || msg < 0 || msg > IVSHMEM_MAX_PEERS) { | |
671 | error_setg(errp, "server sent invalid ID message"); | |
672 | return; | |
673 | } | |
674 | s->vm_id = msg; | |
675 | ||
3a55fc0f MA |
676 | /* |
677 | * Receive more messages until we got shared memory. | |
678 | */ | |
679 | do { | |
1309cf44 MA |
680 | msg = ivshmem_recv_msg(s, &fd, &err); |
681 | if (err) { | |
682 | error_propagate(errp, err); | |
683 | return; | |
684 | } | |
685 | process_msg(s, msg, fd, &err); | |
686 | if (err) { | |
687 | error_propagate(errp, err); | |
688 | return; | |
689 | } | |
3a55fc0f | 690 | } while (msg != -1); |
1309cf44 MA |
691 | |
692 | /* | |
693 | * This function must either map the shared memory or fail. The | |
694 | * loop above ensures that: it terminates normally only after it | |
695 | * successfully processed the server's shared memory message. | |
696 | * Assert that actually mapped the shared memory: | |
697 | */ | |
c2d8019c | 698 | assert(s->ivshmem_bar2); |
5105b1d8 DM |
699 | } |
700 | ||
4490c711 MT |
701 | /* Select the MSI-X vectors used by device. |
702 | * ivshmem maps events to vectors statically, so | |
703 | * we just enable all vectors on init and after reset. */ | |
082751e8 | 704 | static void ivshmem_msix_vector_use(IVShmemState *s) |
4490c711 | 705 | { |
b7578eaa | 706 | PCIDevice *d = PCI_DEVICE(s); |
4490c711 MT |
707 | int i; |
708 | ||
4490c711 | 709 | for (i = 0; i < s->vectors; i++) { |
b7578eaa | 710 | msix_vector_use(d, i); |
4490c711 MT |
711 | } |
712 | } | |
713 | ||
a4022791 LP |
714 | static void ivshmem_disable_irqfd(IVShmemState *s); |
715 | ||
6cbf4c8c CM |
716 | static void ivshmem_reset(DeviceState *d) |
717 | { | |
5400c02b | 718 | IVShmemState *s = IVSHMEM_COMMON(d); |
6cbf4c8c | 719 | |
a4022791 LP |
720 | ivshmem_disable_irqfd(s); |
721 | ||
6cbf4c8c | 722 | s->intrstatus = 0; |
972ad215 | 723 | s->intrmask = 0; |
082751e8 MA |
724 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
725 | ivshmem_msix_vector_use(s); | |
726 | } | |
6cbf4c8c CM |
727 | } |
728 | ||
ee640c62 | 729 | static int ivshmem_setup_interrupts(IVShmemState *s, Error **errp) |
4490c711 | 730 | { |
fd47bfe5 | 731 | /* allocate QEMU callback data for receiving interrupts */ |
b21e2380 | 732 | s->msi_vectors = g_new0(MSIVector, s->vectors); |
6cbf4c8c | 733 | |
fd47bfe5 | 734 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
ee640c62 | 735 | if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1, errp)) { |
fd47bfe5 MAL |
736 | return -1; |
737 | } | |
1116b539 | 738 | |
fd47bfe5 | 739 | IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors); |
082751e8 | 740 | ivshmem_msix_vector_use(s); |
fd47bfe5 | 741 | } |
4490c711 | 742 | |
d58d7e84 | 743 | return 0; |
6cbf4c8c CM |
744 | } |
745 | ||
0b88dd94 LP |
746 | static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector) |
747 | { | |
748 | IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector); | |
749 | ||
750 | if (s->msi_vectors[vector].pdev == NULL) { | |
751 | return; | |
752 | } | |
753 | ||
754 | /* it was cleaned when masked in the frontend. */ | |
755 | kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq); | |
756 | ||
757 | s->msi_vectors[vector].pdev = NULL; | |
758 | } | |
759 | ||
660c97ee MAL |
760 | static void ivshmem_enable_irqfd(IVShmemState *s) |
761 | { | |
762 | PCIDevice *pdev = PCI_DEVICE(s); | |
763 | int i; | |
764 | ||
765 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
1309cf44 MA |
766 | Error *err = NULL; |
767 | ||
768 | ivshmem_add_kvm_msi_virq(s, i, &err); | |
769 | if (err) { | |
770 | error_report_err(err); | |
0b88dd94 | 771 | goto undo; |
1309cf44 | 772 | } |
660c97ee MAL |
773 | } |
774 | ||
775 | if (msix_set_vector_notifiers(pdev, | |
776 | ivshmem_vector_unmask, | |
777 | ivshmem_vector_mask, | |
778 | ivshmem_vector_poll)) { | |
779 | error_report("ivshmem: msix_set_vector_notifiers failed"); | |
0b88dd94 | 780 | goto undo; |
660c97ee | 781 | } |
0b88dd94 | 782 | return; |
660c97ee | 783 | |
0b88dd94 LP |
784 | undo: |
785 | while (--i >= 0) { | |
786 | ivshmem_remove_kvm_msi_virq(s, i); | |
660c97ee | 787 | } |
660c97ee MAL |
788 | } |
789 | ||
790 | static void ivshmem_disable_irqfd(IVShmemState *s) | |
791 | { | |
792 | PCIDevice *pdev = PCI_DEVICE(s); | |
793 | int i; | |
794 | ||
0b88dd94 LP |
795 | if (!pdev->msix_vector_use_notifier) { |
796 | return; | |
797 | } | |
798 | ||
089fd803 LP |
799 | msix_unset_vector_notifiers(pdev); |
800 | ||
660c97ee | 801 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { |
089fd803 LP |
802 | /* |
803 | * MSI-X is already disabled here so msix_unset_vector_notifiers() | |
804 | * didn't call our release notifier. Do it now to keep our masks and | |
805 | * unmasks balanced. | |
806 | */ | |
807 | if (s->msi_vectors[i].unmasked) { | |
808 | ivshmem_vector_mask(pdev, i); | |
809 | } | |
660c97ee MAL |
810 | ivshmem_remove_kvm_msi_virq(s, i); |
811 | } | |
812 | ||
660c97ee MAL |
813 | } |
814 | ||
815 | static void ivshmem_write_config(PCIDevice *pdev, uint32_t address, | |
d58d7e84 | 816 | uint32_t val, int len) |
4490c711 | 817 | { |
5400c02b | 818 | IVShmemState *s = IVSHMEM_COMMON(pdev); |
660c97ee MAL |
819 | int is_enabled, was_enabled = msix_enabled(pdev); |
820 | ||
821 | pci_default_write_config(pdev, address, val, len); | |
822 | is_enabled = msix_enabled(pdev); | |
823 | ||
1309cf44 | 824 | if (kvm_msi_via_irqfd_enabled()) { |
660c97ee MAL |
825 | if (!was_enabled && is_enabled) { |
826 | ivshmem_enable_irqfd(s); | |
827 | } else if (was_enabled && !is_enabled) { | |
828 | ivshmem_disable_irqfd(s); | |
829 | } | |
830 | } | |
4490c711 MT |
831 | } |
832 | ||
5400c02b | 833 | static void ivshmem_common_realize(PCIDevice *dev, Error **errp) |
6cbf4c8c | 834 | { |
5400c02b | 835 | IVShmemState *s = IVSHMEM_COMMON(dev); |
d855e275 | 836 | Error *err = NULL; |
6cbf4c8c CM |
837 | uint8_t *pci_conf; |
838 | ||
6cbf4c8c CM |
839 | /* IRQFD requires MSI */ |
840 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) && | |
841 | !ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
d58d7e84 MAL |
842 | error_setg(errp, "ioeventfd/irqfd requires MSI"); |
843 | return; | |
6cbf4c8c CM |
844 | } |
845 | ||
b7578eaa | 846 | pci_conf = dev->config; |
6cbf4c8c | 847 | pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
6cbf4c8c | 848 | |
3c161542 | 849 | memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s, |
cb06608e AK |
850 | "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE); |
851 | ||
6cbf4c8c | 852 | /* region for registers*/ |
b7578eaa | 853 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, |
e824b2cc | 854 | &s->ivshmem_mmio); |
cb06608e | 855 | |
d9453c93 | 856 | if (s->hostmem != NULL) { |
d9453c93 MAL |
857 | IVSHMEM_DPRINTF("using hostmem\n"); |
858 | ||
7943e97b | 859 | s->ivshmem_bar2 = host_memory_backend_get_memory(s->hostmem); |
b266f1d1 | 860 | host_memory_backend_set_mapped(s->hostmem, true); |
5503e285 | 861 | } else { |
0ec7b3e7 | 862 | Chardev *chr = qemu_chr_fe_get_driver(&s->server_chr); |
5345fdb4 | 863 | assert(chr); |
6dc64780 | 864 | |
6cbf4c8c | 865 | IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n", |
5345fdb4 | 866 | chr->filename); |
6cbf4c8c | 867 | |
f456179f | 868 | /* we allocate enough space for 16 peers and grow as needed */ |
1300b273 | 869 | resize_peers(s, 16); |
6cbf4c8c | 870 | |
3a55fc0f MA |
871 | /* |
872 | * Receive setup messages from server synchronously. | |
873 | * Older versions did it asynchronously, but that creates a | |
874 | * number of entertaining race conditions. | |
3a55fc0f | 875 | */ |
1309cf44 MA |
876 | ivshmem_recv_setup(s, &err); |
877 | if (err) { | |
878 | error_propagate(errp, err); | |
879 | return; | |
3a55fc0f MA |
880 | } |
881 | ||
62a830b6 MA |
882 | if (s->master == ON_OFF_AUTO_ON && s->vm_id != 0) { |
883 | error_setg(errp, | |
884 | "master must connect to the server before any peers"); | |
885 | return; | |
886 | } | |
887 | ||
5345fdb4 | 888 | qemu_chr_fe_set_handlers(&s->server_chr, ivshmem_can_receive, |
81517ba3 | 889 | ivshmem_read, NULL, NULL, s, NULL, true); |
1309cf44 | 890 | |
ee640c62 C |
891 | if (ivshmem_setup_interrupts(s, errp) < 0) { |
892 | error_prepend(errp, "Failed to initialize interrupts: "); | |
3a55fc0f MA |
893 | return; |
894 | } | |
d855e275 MA |
895 | } |
896 | ||
2a845da7 MA |
897 | if (s->master == ON_OFF_AUTO_AUTO) { |
898 | s->master = s->vm_id == 0 ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; | |
899 | } | |
900 | ||
901 | if (!ivshmem_is_master(s)) { | |
d855e275 MA |
902 | error_setg(&s->migration_blocker, |
903 | "Migration is disabled when using feature 'peer mode' in device 'ivshmem'"); | |
c8a7fc51 | 904 | if (migrate_add_blocker(&s->migration_blocker, errp) < 0) { |
fe44dc91 AA |
905 | return; |
906 | } | |
6cbf4c8c | 907 | } |
fe44dc91 AA |
908 | |
909 | vmstate_register_ram(s->ivshmem_bar2, DEVICE(s)); | |
5a0e75f0 TH |
910 | pci_register_bar(PCI_DEVICE(s), 2, |
911 | PCI_BASE_ADDRESS_SPACE_MEMORY | | |
912 | PCI_BASE_ADDRESS_MEM_PREFETCH | | |
913 | PCI_BASE_ADDRESS_MEM_TYPE_64, | |
914 | s->ivshmem_bar2); | |
6cbf4c8c CM |
915 | } |
916 | ||
5400c02b MA |
917 | static void ivshmem_exit(PCIDevice *dev) |
918 | { | |
919 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
f64a078d MAL |
920 | int i; |
921 | ||
c8a7fc51 | 922 | migrate_del_blocker(&s->migration_blocker); |
38e0735e | 923 | |
c2d8019c | 924 | if (memory_region_is_mapped(s->ivshmem_bar2)) { |
d9453c93 | 925 | if (!s->hostmem) { |
c2d8019c | 926 | void *addr = memory_region_get_ram_ptr(s->ivshmem_bar2); |
56a571d9 | 927 | int fd; |
d9453c93 | 928 | |
5400c02b | 929 | if (munmap(addr, memory_region_size(s->ivshmem_bar2) == -1)) { |
d9453c93 MAL |
930 | error_report("Failed to munmap shared memory %s", |
931 | strerror(errno)); | |
932 | } | |
56a571d9 | 933 | |
4ff87573 | 934 | fd = memory_region_get_fd(s->ivshmem_bar2); |
c2d8019c | 935 | close(fd); |
d9453c93 | 936 | } |
f64a078d | 937 | |
c2d8019c | 938 | vmstate_unregister_ram(s->ivshmem_bar2, DEVICE(dev)); |
f64a078d MAL |
939 | } |
940 | ||
b266f1d1 MA |
941 | if (s->hostmem) { |
942 | host_memory_backend_set_mapped(s->hostmem, false); | |
943 | } | |
944 | ||
f64a078d MAL |
945 | if (s->peers) { |
946 | for (i = 0; i < s->nb_peers; i++) { | |
f456179f | 947 | close_peer_eventfds(s, i); |
f64a078d MAL |
948 | } |
949 | g_free(s->peers); | |
950 | } | |
951 | ||
952 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
953 | msix_uninit_exclusive_bar(dev); | |
954 | } | |
955 | ||
0f57350e | 956 | g_free(s->msi_vectors); |
6cbf4c8c CM |
957 | } |
958 | ||
1f8552df MAL |
959 | static int ivshmem_pre_load(void *opaque) |
960 | { | |
961 | IVShmemState *s = opaque; | |
962 | ||
2a845da7 | 963 | if (!ivshmem_is_master(s)) { |
1f8552df MAL |
964 | error_report("'peer' devices are not migratable"); |
965 | return -EINVAL; | |
966 | } | |
967 | ||
968 | return 0; | |
969 | } | |
970 | ||
971 | static int ivshmem_post_load(void *opaque, int version_id) | |
972 | { | |
973 | IVShmemState *s = opaque; | |
974 | ||
975 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
082751e8 | 976 | ivshmem_msix_vector_use(s); |
1f8552df | 977 | } |
1f8552df MAL |
978 | return 0; |
979 | } | |
980 | ||
5400c02b | 981 | static void ivshmem_common_class_init(ObjectClass *klass, void *data) |
40021f08 | 982 | { |
39bffca2 | 983 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
984 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
985 | ||
5400c02b MA |
986 | k->realize = ivshmem_common_realize; |
987 | k->exit = ivshmem_exit; | |
d58d7e84 | 988 | k->config_write = ivshmem_write_config; |
b8ef62a9 PB |
989 | k->vendor_id = PCI_VENDOR_ID_IVSHMEM; |
990 | k->device_id = PCI_DEVICE_ID_IVSHMEM; | |
40021f08 | 991 | k->class_id = PCI_CLASS_MEMORY_RAM; |
5400c02b | 992 | k->revision = 1; |
39bffca2 | 993 | dc->reset = ivshmem_reset; |
125ee0ed | 994 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
d383537d | 995 | dc->desc = "Inter-VM shared memory"; |
40021f08 AL |
996 | } |
997 | ||
ddc85284 MA |
998 | static const TypeInfo ivshmem_common_info = { |
999 | .name = TYPE_IVSHMEM_COMMON, | |
1000 | .parent = TYPE_PCI_DEVICE, | |
1001 | .instance_size = sizeof(IVShmemState), | |
1002 | .abstract = true, | |
1003 | .class_init = ivshmem_common_class_init, | |
fd3b02c8 EH |
1004 | .interfaces = (InterfaceInfo[]) { |
1005 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
1006 | { }, | |
1007 | }, | |
ddc85284 | 1008 | }; |
5400c02b | 1009 | |
5400c02b MA |
1010 | static const VMStateDescription ivshmem_plain_vmsd = { |
1011 | .name = TYPE_IVSHMEM_PLAIN, | |
1012 | .version_id = 0, | |
1013 | .minimum_version_id = 0, | |
1014 | .pre_load = ivshmem_pre_load, | |
1015 | .post_load = ivshmem_post_load, | |
e4ea952f | 1016 | .fields = (const VMStateField[]) { |
5400c02b MA |
1017 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), |
1018 | VMSTATE_UINT32(intrstatus, IVShmemState), | |
1019 | VMSTATE_UINT32(intrmask, IVShmemState), | |
1020 | VMSTATE_END_OF_LIST() | |
1021 | }, | |
1022 | }; | |
1023 | ||
1024 | static Property ivshmem_plain_properties[] = { | |
1025 | DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), | |
e9cb190a FZ |
1026 | DEFINE_PROP_LINK("memdev", IVShmemState, hostmem, TYPE_MEMORY_BACKEND, |
1027 | HostMemoryBackend *), | |
5400c02b MA |
1028 | DEFINE_PROP_END_OF_LIST(), |
1029 | }; | |
1030 | ||
6dc64780 MAL |
1031 | static void ivshmem_plain_realize(PCIDevice *dev, Error **errp) |
1032 | { | |
1033 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
1034 | ||
1035 | if (!s->hostmem) { | |
1036 | error_setg(errp, "You must specify a 'memdev'"); | |
1037 | return; | |
e9cb190a | 1038 | } else if (host_memory_backend_is_mapped(s->hostmem)) { |
7a309cc9 MA |
1039 | error_setg(errp, "can't use already busy memdev: %s", |
1040 | object_get_canonical_path_component(OBJECT(s->hostmem))); | |
e9cb190a | 1041 | return; |
6dc64780 MAL |
1042 | } |
1043 | ||
1044 | ivshmem_common_realize(dev, errp); | |
1045 | } | |
1046 | ||
5400c02b MA |
1047 | static void ivshmem_plain_class_init(ObjectClass *klass, void *data) |
1048 | { | |
1049 | DeviceClass *dc = DEVICE_CLASS(klass); | |
6dc64780 | 1050 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
5400c02b | 1051 | |
6dc64780 | 1052 | k->realize = ivshmem_plain_realize; |
4f67d30b | 1053 | device_class_set_props(dc, ivshmem_plain_properties); |
5400c02b MA |
1054 | dc->vmsd = &ivshmem_plain_vmsd; |
1055 | } | |
1056 | ||
1057 | static const TypeInfo ivshmem_plain_info = { | |
1058 | .name = TYPE_IVSHMEM_PLAIN, | |
1059 | .parent = TYPE_IVSHMEM_COMMON, | |
1060 | .instance_size = sizeof(IVShmemState), | |
5400c02b MA |
1061 | .class_init = ivshmem_plain_class_init, |
1062 | }; | |
1063 | ||
1064 | static const VMStateDescription ivshmem_doorbell_vmsd = { | |
1065 | .name = TYPE_IVSHMEM_DOORBELL, | |
1066 | .version_id = 0, | |
1067 | .minimum_version_id = 0, | |
1068 | .pre_load = ivshmem_pre_load, | |
1069 | .post_load = ivshmem_post_load, | |
e4ea952f | 1070 | .fields = (const VMStateField[]) { |
5400c02b MA |
1071 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), |
1072 | VMSTATE_MSIX(parent_obj, IVShmemState), | |
1073 | VMSTATE_UINT32(intrstatus, IVShmemState), | |
1074 | VMSTATE_UINT32(intrmask, IVShmemState), | |
1075 | VMSTATE_END_OF_LIST() | |
1076 | }, | |
1077 | }; | |
1078 | ||
1079 | static Property ivshmem_doorbell_properties[] = { | |
1080 | DEFINE_PROP_CHR("chardev", IVShmemState, server_chr), | |
1081 | DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1), | |
1082 | DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, | |
1083 | true), | |
1084 | DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), | |
1085 | DEFINE_PROP_END_OF_LIST(), | |
1086 | }; | |
1087 | ||
1088 | static void ivshmem_doorbell_init(Object *obj) | |
1089 | { | |
1090 | IVShmemState *s = IVSHMEM_DOORBELL(obj); | |
1091 | ||
1092 | s->features |= (1 << IVSHMEM_MSI); | |
5400c02b MA |
1093 | } |
1094 | ||
6dc64780 MAL |
1095 | static void ivshmem_doorbell_realize(PCIDevice *dev, Error **errp) |
1096 | { | |
1097 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
1098 | ||
30650701 | 1099 | if (!qemu_chr_fe_backend_connected(&s->server_chr)) { |
6dc64780 MAL |
1100 | error_setg(errp, "You must specify a 'chardev'"); |
1101 | return; | |
1102 | } | |
1103 | ||
1104 | ivshmem_common_realize(dev, errp); | |
1105 | } | |
1106 | ||
5400c02b MA |
1107 | static void ivshmem_doorbell_class_init(ObjectClass *klass, void *data) |
1108 | { | |
1109 | DeviceClass *dc = DEVICE_CLASS(klass); | |
6dc64780 | 1110 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
5400c02b | 1111 | |
6dc64780 | 1112 | k->realize = ivshmem_doorbell_realize; |
4f67d30b | 1113 | device_class_set_props(dc, ivshmem_doorbell_properties); |
5400c02b MA |
1114 | dc->vmsd = &ivshmem_doorbell_vmsd; |
1115 | } | |
1116 | ||
1117 | static const TypeInfo ivshmem_doorbell_info = { | |
1118 | .name = TYPE_IVSHMEM_DOORBELL, | |
1119 | .parent = TYPE_IVSHMEM_COMMON, | |
1120 | .instance_size = sizeof(IVShmemState), | |
1121 | .instance_init = ivshmem_doorbell_init, | |
1122 | .class_init = ivshmem_doorbell_class_init, | |
1123 | }; | |
1124 | ||
83f7d43a | 1125 | static void ivshmem_register_types(void) |
6cbf4c8c | 1126 | { |
5400c02b MA |
1127 | type_register_static(&ivshmem_common_info); |
1128 | type_register_static(&ivshmem_plain_info); | |
1129 | type_register_static(&ivshmem_doorbell_info); | |
6cbf4c8c CM |
1130 | } |
1131 | ||
83f7d43a | 1132 | type_init(ivshmem_register_types) |