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ivshmem: Always remove irqfd notifiers
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CommitLineData
6cbf4c8c
CM
1/*
2 * Inter-VM Shared Memory PCI device.
3 *
4 * Author:
5 * Cam Macdonell <cam@cs.ualberta.ca>
6 *
7 * Based On: cirrus_vga.c
8 * Copyright (c) 2004 Fabrice Bellard
9 * Copyright (c) 2004 Makoto Suzuki (suzu)
10 *
11 * and rtl8139.c
12 * Copyright (c) 2006 Igor Kovalenko
13 *
14 * This code is licensed under the GNU GPL v2.
6b620ca3
PB
15 *
16 * Contributions after 2012-01-13 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
6cbf4c8c 18 */
0d1c9782 19#include "qemu/osdep.h"
da34e65c 20#include "qapi/error.h"
f348b6d1 21#include "qemu/cutils.h"
83c9f4ca 22#include "hw/hw.h"
83c9f4ca 23#include "hw/pci/pci.h"
660c97ee 24#include "hw/pci/msi.h"
83c9f4ca 25#include "hw/pci/msix.h"
9c17d615 26#include "sysemu/kvm.h"
795c40b8 27#include "migration/blocker.h"
d49b6836 28#include "qemu/error-report.h"
1de7afc9 29#include "qemu/event_notifier.h"
5503e285 30#include "qom/object_interfaces.h"
4d43a603 31#include "chardev/char-fe.h"
d9453c93 32#include "sysemu/hostmem.h"
5400c02b 33#include "sysemu/qtest.h"
d9453c93 34#include "qapi/visitor.h"
6cbf4c8c 35
5105b1d8
DM
36#include "hw/misc/ivshmem.h"
37
b8ef62a9
PB
38#define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET
39#define PCI_DEVICE_ID_IVSHMEM 0x1110
40
cd9953f7 41#define IVSHMEM_MAX_PEERS UINT16_MAX
6cbf4c8c
CM
42#define IVSHMEM_IOEVENTFD 0
43#define IVSHMEM_MSI 1
44
6cbf4c8c
CM
45#define IVSHMEM_REG_BAR_SIZE 0x100
46
a4fa93bf
MA
47#define IVSHMEM_DEBUG 0
48#define IVSHMEM_DPRINTF(fmt, ...) \
49 do { \
50 if (IVSHMEM_DEBUG) { \
51 printf("IVSHMEM: " fmt, ## __VA_ARGS__); \
52 } \
53 } while (0)
6cbf4c8c 54
5400c02b
MA
55#define TYPE_IVSHMEM_COMMON "ivshmem-common"
56#define IVSHMEM_COMMON(obj) \
57 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_COMMON)
58
59#define TYPE_IVSHMEM_PLAIN "ivshmem-plain"
60#define IVSHMEM_PLAIN(obj) \
61 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_PLAIN)
62
63#define TYPE_IVSHMEM_DOORBELL "ivshmem-doorbell"
64#define IVSHMEM_DOORBELL(obj) \
65 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_DOORBELL)
66
eb3fedf3
PC
67#define TYPE_IVSHMEM "ivshmem"
68#define IVSHMEM(obj) \
69 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM)
70
6cbf4c8c
CM
71typedef struct Peer {
72 int nb_eventfds;
563027cc 73 EventNotifier *eventfds;
6cbf4c8c
CM
74} Peer;
75
0f57350e 76typedef struct MSIVector {
6cbf4c8c 77 PCIDevice *pdev;
660c97ee 78 int virq;
089fd803 79 bool unmasked;
0f57350e 80} MSIVector;
6cbf4c8c
CM
81
82typedef struct IVShmemState {
b7578eaa
AF
83 /*< private >*/
84 PCIDevice parent_obj;
85 /*< public >*/
86
ddc85284
MA
87 uint32_t features;
88
89 /* exactly one of these two may be set */
90 HostMemoryBackend *hostmem; /* with interrupts */
becdfa00 91 CharBackend server_chr; /* without interrupts */
ddc85284
MA
92
93 /* registers */
6cbf4c8c
CM
94 uint32_t intrmask;
95 uint32_t intrstatus;
ddc85284 96 int vm_id;
6cbf4c8c 97
ddc85284
MA
98 /* BARs */
99 MemoryRegion ivshmem_mmio; /* BAR 0 (registers) */
c2d8019c
MA
100 MemoryRegion *ivshmem_bar2; /* BAR 2 (shared memory) */
101 MemoryRegion server_bar2; /* used with server_chr */
6cbf4c8c 102
ddc85284 103 /* interrupt support */
6cbf4c8c 104 Peer *peers;
cd9953f7 105 int nb_peers; /* space in @peers[] */
6cbf4c8c 106 uint32_t vectors;
0f57350e 107 MSIVector *msi_vectors;
ee276391
MA
108 uint64_t msg_buf; /* buffer for receiving server messages */
109 int msg_buffered_bytes; /* #bytes in @msg_buf */
6cbf4c8c 110
ddc85284 111 /* migration stuff */
2a845da7 112 OnOffAuto master;
38e0735e
AL
113 Error *migration_blocker;
114
5400c02b
MA
115 /* legacy cruft */
116 char *role;
117 char *shmobj;
118 char *sizearg;
119 size_t legacy_size;
120 uint32_t not_legacy_32bit;
6cbf4c8c
CM
121} IVShmemState;
122
123/* registers for the Inter-VM shared memory device */
124enum ivshmem_registers {
125 INTRMASK = 0,
126 INTRSTATUS = 4,
127 IVPOSITION = 8,
128 DOORBELL = 12,
129};
130
131static inline uint32_t ivshmem_has_feature(IVShmemState *ivs,
132 unsigned int feature) {
133 return (ivs->features & (1 << feature));
134}
135
2a845da7
MA
136static inline bool ivshmem_is_master(IVShmemState *s)
137{
138 assert(s->master != ON_OFF_AUTO_AUTO);
139 return s->master == ON_OFF_AUTO_ON;
140}
141
d8a5da07 142static void ivshmem_update_irq(IVShmemState *s)
6cbf4c8c 143{
b7578eaa 144 PCIDevice *d = PCI_DEVICE(s);
434ad76d 145 uint32_t isr = s->intrstatus & s->intrmask;
6cbf4c8c 146
5400c02b
MA
147 /*
148 * Do nothing unless the device actually uses INTx. Here's how
149 * the device variants signal interrupts, what they put in PCI
150 * config space:
151 * Device variant Interrupt Interrupt Pin MSI-X cap.
152 * ivshmem-plain none 0 no
153 * ivshmem-doorbell MSI-X 1 yes(1)
154 * ivshmem,msi=off INTx 1 no
155 * ivshmem,msi=on MSI-X 1(2) yes(1)
156 * (1) if guest enabled MSI-X
157 * (2) the device lies
158 * Leads to the condition for doing nothing:
159 */
160 if (ivshmem_has_feature(s, IVSHMEM_MSI)
161 || !d->config[PCI_INTERRUPT_PIN]) {
2d1d422d
MA
162 return;
163 }
164
6cbf4c8c
CM
165 /* don't print ISR resets */
166 if (isr) {
167 IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n",
dbc464d4 168 isr ? 1 : 0, s->intrstatus, s->intrmask);
6cbf4c8c
CM
169 }
170
434ad76d 171 pci_set_irq(d, isr != 0);
6cbf4c8c
CM
172}
173
174static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val)
175{
176 IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val);
177
178 s->intrmask = val;
d8a5da07 179 ivshmem_update_irq(s);
6cbf4c8c
CM
180}
181
182static uint32_t ivshmem_IntrMask_read(IVShmemState *s)
183{
184 uint32_t ret = s->intrmask;
185
186 IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret);
6cbf4c8c
CM
187 return ret;
188}
189
190static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val)
191{
192 IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val);
193
194 s->intrstatus = val;
d8a5da07 195 ivshmem_update_irq(s);
6cbf4c8c
CM
196}
197
198static uint32_t ivshmem_IntrStatus_read(IVShmemState *s)
199{
200 uint32_t ret = s->intrstatus;
201
202 /* reading ISR clears all interrupts */
203 s->intrstatus = 0;
d8a5da07 204 ivshmem_update_irq(s);
6cbf4c8c
CM
205 return ret;
206}
207
a8170e5e 208static void ivshmem_io_write(void *opaque, hwaddr addr,
cb06608e 209 uint64_t val, unsigned size)
6cbf4c8c
CM
210{
211 IVShmemState *s = opaque;
212
6cbf4c8c
CM
213 uint16_t dest = val >> 16;
214 uint16_t vector = val & 0xff;
215
216 addr &= 0xfc;
217
218 IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr);
219 switch (addr)
220 {
221 case INTRMASK:
222 ivshmem_IntrMask_write(s, val);
223 break;
224
225 case INTRSTATUS:
226 ivshmem_IntrStatus_write(s, val);
227 break;
228
229 case DOORBELL:
230 /* check that dest VM ID is reasonable */
95c8425c 231 if (dest >= s->nb_peers) {
6cbf4c8c
CM
232 IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest);
233 break;
234 }
235
236 /* check doorbell range */
1b27d7a1 237 if (vector < s->peers[dest].nb_eventfds) {
563027cc
PB
238 IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector);
239 event_notifier_set(&s->peers[dest].eventfds[vector]);
f59bb378
MAL
240 } else {
241 IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n",
242 vector, dest);
6cbf4c8c
CM
243 }
244 break;
245 default:
f59bb378 246 IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr);
6cbf4c8c
CM
247 }
248}
249
a8170e5e 250static uint64_t ivshmem_io_read(void *opaque, hwaddr addr,
cb06608e 251 unsigned size)
6cbf4c8c
CM
252{
253
254 IVShmemState *s = opaque;
255 uint32_t ret;
256
257 switch (addr)
258 {
259 case INTRMASK:
260 ret = ivshmem_IntrMask_read(s);
261 break;
262
263 case INTRSTATUS:
264 ret = ivshmem_IntrStatus_read(s);
265 break;
266
267 case IVPOSITION:
1309cf44 268 ret = s->vm_id;
6cbf4c8c
CM
269 break;
270
271 default:
272 IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr);
273 ret = 0;
274 }
275
276 return ret;
277}
278
cb06608e
AK
279static const MemoryRegionOps ivshmem_mmio_ops = {
280 .read = ivshmem_io_read,
281 .write = ivshmem_io_write,
282 .endianness = DEVICE_NATIVE_ENDIAN,
283 .impl = {
284 .min_access_size = 4,
285 .max_access_size = 4,
286 },
6cbf4c8c
CM
287};
288
9940c323
MAL
289static void ivshmem_vector_notify(void *opaque)
290{
0f57350e 291 MSIVector *entry = opaque;
6cbf4c8c 292 PCIDevice *pdev = entry->pdev;
5400c02b 293 IVShmemState *s = IVSHMEM_COMMON(pdev);
0f57350e 294 int vector = entry - s->msi_vectors;
9940c323
MAL
295 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
296
297 if (!event_notifier_test_and_clear(n)) {
298 return;
299 }
6cbf4c8c 300
d160f3f7 301 IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector);
9940c323 302 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
082751e8
MA
303 if (msix_enabled(pdev)) {
304 msix_notify(pdev, vector);
305 }
9940c323
MAL
306 } else {
307 ivshmem_IntrStatus_write(s, 1);
308 }
6cbf4c8c
CM
309}
310
660c97ee
MAL
311static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector,
312 MSIMessage msg)
313{
5400c02b 314 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
315 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
316 MSIVector *v = &s->msi_vectors[vector];
317 int ret;
318
319 IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector);
e6a354be
LP
320 if (!v->pdev) {
321 error_report("ivshmem: vector %d route does not exist", vector);
322 return -EINVAL;
323 }
089fd803 324 assert(!v->unmasked);
660c97ee
MAL
325
326 ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev);
327 if (ret < 0) {
328 return ret;
329 }
3f1fea0f 330 kvm_irqchip_commit_routes(kvm_state);
660c97ee 331
089fd803
LP
332 ret = kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq);
333 if (ret < 0) {
334 return ret;
335 }
336 v->unmasked = true;
337
338 return 0;
660c97ee
MAL
339}
340
341static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector)
342{
5400c02b 343 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee 344 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
e6a354be 345 MSIVector *v = &s->msi_vectors[vector];
660c97ee
MAL
346 int ret;
347
348 IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector);
e6a354be
LP
349 if (!v->pdev) {
350 error_report("ivshmem: vector %d route does not exist", vector);
351 return;
352 }
089fd803 353 assert(v->unmasked);
660c97ee 354
e6a354be 355 ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, v->virq);
089fd803 356 if (ret < 0) {
660c97ee 357 error_report("remove_irqfd_notifier_gsi failed");
089fd803 358 return;
660c97ee 359 }
089fd803 360 v->unmasked = false;
660c97ee
MAL
361}
362
363static void ivshmem_vector_poll(PCIDevice *dev,
364 unsigned int vector_start,
365 unsigned int vector_end)
366{
5400c02b 367 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
368 unsigned int vector;
369
370 IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end);
371
372 vector_end = MIN(vector_end, s->vectors);
373
374 for (vector = vector_start; vector < vector_end; vector++) {
375 EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector];
376
377 if (!msix_is_masked(dev, vector)) {
378 continue;
379 }
380
381 if (event_notifier_test_and_clear(notifier)) {
382 msix_set_pending(dev, vector);
383 }
384 }
385}
386
9940c323
MAL
387static void watch_vector_notifier(IVShmemState *s, EventNotifier *n,
388 int vector)
6cbf4c8c 389{
563027cc 390 int eventfd = event_notifier_get_fd(n);
6cbf4c8c 391
3c27969b 392 assert(!s->msi_vectors[vector].pdev);
9940c323 393 s->msi_vectors[vector].pdev = PCI_DEVICE(s);
6cbf4c8c 394
9940c323
MAL
395 qemu_set_fd_handler(eventfd, ivshmem_vector_notify,
396 NULL, &s->msi_vectors[vector]);
6cbf4c8c
CM
397}
398
563027cc
PB
399static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i)
400{
401 memory_region_add_eventfd(&s->ivshmem_mmio,
402 DOORBELL,
403 4,
404 true,
405 (posn << 16) | i,
753d5e14 406 &s->peers[posn].eventfds[i]);
563027cc
PB
407}
408
409static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i)
410{
411 memory_region_del_eventfd(&s->ivshmem_mmio,
412 DOORBELL,
413 4,
414 true,
415 (posn << 16) | i,
753d5e14 416 &s->peers[posn].eventfds[i]);
563027cc
PB
417}
418
f456179f 419static void close_peer_eventfds(IVShmemState *s, int posn)
6cbf4c8c 420{
f456179f 421 int i, n;
6cbf4c8c 422
9db51b4d 423 assert(posn >= 0 && posn < s->nb_peers);
f456179f 424 n = s->peers[posn].nb_eventfds;
6cbf4c8c 425
9db51b4d
MA
426 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) {
427 memory_region_transaction_begin();
428 for (i = 0; i < n; i++) {
429 ivshmem_del_eventfd(s, posn, i);
430 }
431 memory_region_transaction_commit();
b6a1f3a5 432 }
9db51b4d 433
f456179f 434 for (i = 0; i < n; i++) {
563027cc 435 event_notifier_cleanup(&s->peers[posn].eventfds[i]);
6cbf4c8c
CM
436 }
437
7267c094 438 g_free(s->peers[posn].eventfds);
6cbf4c8c
CM
439 s->peers[posn].nb_eventfds = 0;
440}
441
cd9953f7 442static void resize_peers(IVShmemState *s, int nb_peers)
34bc07c5 443{
cd9953f7
MA
444 int old_nb_peers = s->nb_peers;
445 int i;
6cbf4c8c 446
cd9953f7
MA
447 assert(nb_peers > old_nb_peers);
448 IVSHMEM_DPRINTF("bumping storage to %d peers\n", nb_peers);
6cbf4c8c 449
cd9953f7
MA
450 s->peers = g_realloc(s->peers, nb_peers * sizeof(Peer));
451 s->nb_peers = nb_peers;
1300b273 452
cd9953f7
MA
453 for (i = old_nb_peers; i < nb_peers; i++) {
454 s->peers[i].eventfds = g_new0(EventNotifier, s->vectors);
455 s->peers[i].nb_eventfds = 0;
6cbf4c8c
CM
456 }
457}
458
1309cf44
MA
459static void ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector,
460 Error **errp)
660c97ee
MAL
461{
462 PCIDevice *pdev = PCI_DEVICE(s);
660c97ee
MAL
463 int ret;
464
465 IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector);
3c27969b 466 assert(!s->msi_vectors[vector].pdev);
660c97ee 467
d1f6af6a 468 ret = kvm_irqchip_add_msi_route(kvm_state, vector, pdev);
660c97ee 469 if (ret < 0) {
1309cf44
MA
470 error_setg(errp, "kvm_irqchip_add_msi_route failed");
471 return;
660c97ee
MAL
472 }
473
474 s->msi_vectors[vector].virq = ret;
475 s->msi_vectors[vector].pdev = pdev;
660c97ee
MAL
476}
477
1309cf44 478static void setup_interrupt(IVShmemState *s, int vector, Error **errp)
660c97ee
MAL
479{
480 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
481 bool with_irqfd = kvm_msi_via_irqfd_enabled() &&
482 ivshmem_has_feature(s, IVSHMEM_MSI);
483 PCIDevice *pdev = PCI_DEVICE(s);
1309cf44 484 Error *err = NULL;
660c97ee
MAL
485
486 IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector);
487
488 if (!with_irqfd) {
97553976 489 IVSHMEM_DPRINTF("with eventfd\n");
9940c323 490 watch_vector_notifier(s, n, vector);
660c97ee 491 } else if (msix_enabled(pdev)) {
97553976 492 IVSHMEM_DPRINTF("with irqfd\n");
1309cf44
MA
493 ivshmem_add_kvm_msi_virq(s, vector, &err);
494 if (err) {
495 error_propagate(errp, err);
660c97ee
MAL
496 return;
497 }
498
499 if (!msix_is_masked(pdev, vector)) {
500 kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL,
501 s->msi_vectors[vector].virq);
1309cf44 502 /* TODO handle error */
660c97ee
MAL
503 }
504 } else {
505 /* it will be delayed until msix is enabled, in write_config */
97553976 506 IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n");
660c97ee
MAL
507 }
508}
509
1309cf44 510static void process_msg_shmem(IVShmemState *s, int fd, Error **errp)
6cbf4c8c 511{
8381d89b 512 Error *local_err = NULL;
8baeb22b 513 struct stat buf;
5400c02b 514 size_t size;
6cbf4c8c 515
c2d8019c 516 if (s->ivshmem_bar2) {
1309cf44 517 error_setg(errp, "server sent unexpected shared memory message");
ca0b7566 518 close(fd);
0f14fd71 519 return;
a2e9011b
SH
520 }
521
8baeb22b
MA
522 if (fstat(fd, &buf) < 0) {
523 error_setg_errno(errp, errno,
524 "can't determine size of shared memory sent by server");
525 close(fd);
526 return;
527 }
528
5400c02b
MA
529 size = buf.st_size;
530
531 /* Legacy cruft */
532 if (s->legacy_size != SIZE_MAX) {
533 if (size < s->legacy_size) {
534 error_setg(errp, "server sent only %zd bytes of shared memory",
535 (size_t)buf.st_size);
536 close(fd);
537 return;
538 }
539 size = s->legacy_size;
cd9953f7
MA
540 }
541
ca0b7566 542 /* mmap the region and map into the BAR2 */
8381d89b
MAL
543 memory_region_init_ram_from_fd(&s->server_bar2, OBJECT(s),
544 "ivshmem.bar2", size, true, fd, &local_err);
545 if (local_err) {
546 error_propagate(errp, local_err);
ca0b7566 547 return;
6cbf4c8c 548 }
8381d89b 549
c2d8019c 550 s->ivshmem_bar2 = &s->server_bar2;
ca0b7566
MA
551}
552
1309cf44
MA
553static void process_msg_disconnect(IVShmemState *s, uint16_t posn,
554 Error **errp)
ca0b7566
MA
555{
556 IVSHMEM_DPRINTF("posn %d has gone away\n", posn);
9db51b4d 557 if (posn >= s->nb_peers || posn == s->vm_id) {
1309cf44 558 error_setg(errp, "invalid peer %d", posn);
9db51b4d
MA
559 return;
560 }
ca0b7566
MA
561 close_peer_eventfds(s, posn);
562}
6cbf4c8c 563
1309cf44
MA
564static void process_msg_connect(IVShmemState *s, uint16_t posn, int fd,
565 Error **errp)
ca0b7566
MA
566{
567 Peer *peer = &s->peers[posn];
568 int vector;
9a2f0e64 569
ca0b7566
MA
570 /*
571 * The N-th connect message for this peer comes with the file
572 * descriptor for vector N-1. Count messages to find the vector.
573 */
574 if (peer->nb_eventfds >= s->vectors) {
1309cf44
MA
575 error_setg(errp, "Too many eventfd received, device has %d vectors",
576 s->vectors);
ca0b7566 577 close(fd);
6f8a16d5 578 return;
6cbf4c8c 579 }
ca0b7566 580 vector = peer->nb_eventfds++;
6cbf4c8c 581
ca0b7566
MA
582 IVSHMEM_DPRINTF("eventfds[%d][%d] = %d\n", posn, vector, fd);
583 event_notifier_init_fd(&peer->eventfds[vector], fd);
584 fcntl_setfl(fd, O_NONBLOCK); /* msix/irqfd poll non block */
945001a1 585
ca0b7566 586 if (posn == s->vm_id) {
1309cf44
MA
587 setup_interrupt(s, vector, errp);
588 /* TODO do we need to handle the error? */
ca0b7566 589 }
6cbf4c8c 590
ca0b7566
MA
591 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) {
592 ivshmem_add_eventfd(s, posn, vector);
593 }
594}
6cbf4c8c 595
1309cf44 596static void process_msg(IVShmemState *s, int64_t msg, int fd, Error **errp)
ca0b7566
MA
597{
598 IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd);
6cbf4c8c 599
ca0b7566 600 if (msg < -1 || msg > IVSHMEM_MAX_PEERS) {
1309cf44 601 error_setg(errp, "server sent invalid message %" PRId64, msg);
ca0b7566 602 close(fd);
6cbf4c8c
CM
603 return;
604 }
605
ca0b7566 606 if (msg == -1) {
1309cf44 607 process_msg_shmem(s, fd, errp);
1ee57de4
MAL
608 return;
609 }
610
ca0b7566
MA
611 if (msg >= s->nb_peers) {
612 resize_peers(s, msg + 1);
613 }
6cbf4c8c 614
ca0b7566 615 if (fd >= 0) {
1309cf44 616 process_msg_connect(s, msg, fd, errp);
ca0b7566 617 } else {
1309cf44 618 process_msg_disconnect(s, msg, errp);
6cbf4c8c 619 }
ca0b7566 620}
6cbf4c8c 621
ee276391
MA
622static int ivshmem_can_receive(void *opaque)
623{
624 IVShmemState *s = opaque;
625
626 assert(s->msg_buffered_bytes < sizeof(s->msg_buf));
627 return sizeof(s->msg_buf) - s->msg_buffered_bytes;
628}
629
ca0b7566
MA
630static void ivshmem_read(void *opaque, const uint8_t *buf, int size)
631{
632 IVShmemState *s = opaque;
1309cf44 633 Error *err = NULL;
ca0b7566
MA
634 int fd;
635 int64_t msg;
636
ee276391
MA
637 assert(size >= 0 && s->msg_buffered_bytes + size <= sizeof(s->msg_buf));
638 memcpy((unsigned char *)&s->msg_buf + s->msg_buffered_bytes, buf, size);
639 s->msg_buffered_bytes += size;
640 if (s->msg_buffered_bytes < sizeof(s->msg_buf)) {
ca0b7566 641 return;
6cbf4c8c 642 }
ee276391
MA
643 msg = le64_to_cpu(s->msg_buf);
644 s->msg_buffered_bytes = 0;
ca0b7566 645
5345fdb4 646 fd = qemu_chr_fe_get_msgfd(&s->server_chr);
ca0b7566 647
1309cf44
MA
648 process_msg(s, msg, fd, &err);
649 if (err) {
650 error_report_err(err);
651 }
6cbf4c8c
CM
652}
653
1309cf44 654static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp)
5105b1d8 655{
3a55fc0f
MA
656 int64_t msg;
657 int n, ret;
658
659 n = 0;
660 do {
5345fdb4
MAL
661 ret = qemu_chr_fe_read_all(&s->server_chr, (uint8_t *)&msg + n,
662 sizeof(msg) - n);
b7b1e9dd
PMD
663 if (ret < 0) {
664 if (ret == -EINTR) {
665 continue;
666 }
1309cf44 667 error_setg_errno(errp, -ret, "read from server failed");
3a55fc0f
MA
668 return INT64_MIN;
669 }
670 n += ret;
671 } while (n < sizeof(msg));
5105b1d8 672
5345fdb4 673 *pfd = qemu_chr_fe_get_msgfd(&s->server_chr);
51af0ec9 674 return le64_to_cpu(msg);
3a55fc0f 675}
5105b1d8 676
1309cf44 677static void ivshmem_recv_setup(IVShmemState *s, Error **errp)
3a55fc0f 678{
1309cf44 679 Error *err = NULL;
3a55fc0f
MA
680 int64_t msg;
681 int fd;
682
1309cf44
MA
683 msg = ivshmem_recv_msg(s, &fd, &err);
684 if (err) {
685 error_propagate(errp, err);
686 return;
687 }
688 if (msg != IVSHMEM_PROTOCOL_VERSION) {
689 error_setg(errp, "server sent version %" PRId64 ", expecting %d",
690 msg, IVSHMEM_PROTOCOL_VERSION);
691 return;
692 }
693 if (fd != -1) {
694 error_setg(errp, "server sent invalid version message");
5105b1d8
DM
695 return;
696 }
697
a3feb086
MA
698 /*
699 * ivshmem-server sends the remaining initial messages in a fixed
700 * order, but the device has always accepted them in any order.
701 * Stay as compatible as practical, just in case people use
702 * servers that behave differently.
703 */
704
705 /*
706 * ivshmem_device_spec.txt has always required the ID message
707 * right here, and ivshmem-server has always complied. However,
708 * older versions of the device accepted it out of order, but
709 * broke when an interrupt setup message arrived before it.
710 */
711 msg = ivshmem_recv_msg(s, &fd, &err);
712 if (err) {
713 error_propagate(errp, err);
714 return;
715 }
716 if (fd != -1 || msg < 0 || msg > IVSHMEM_MAX_PEERS) {
717 error_setg(errp, "server sent invalid ID message");
718 return;
719 }
720 s->vm_id = msg;
721
3a55fc0f
MA
722 /*
723 * Receive more messages until we got shared memory.
724 */
725 do {
1309cf44
MA
726 msg = ivshmem_recv_msg(s, &fd, &err);
727 if (err) {
728 error_propagate(errp, err);
729 return;
730 }
731 process_msg(s, msg, fd, &err);
732 if (err) {
733 error_propagate(errp, err);
734 return;
735 }
3a55fc0f 736 } while (msg != -1);
1309cf44
MA
737
738 /*
739 * This function must either map the shared memory or fail. The
740 * loop above ensures that: it terminates normally only after it
741 * successfully processed the server's shared memory message.
742 * Assert that actually mapped the shared memory:
743 */
c2d8019c 744 assert(s->ivshmem_bar2);
5105b1d8
DM
745}
746
4490c711
MT
747/* Select the MSI-X vectors used by device.
748 * ivshmem maps events to vectors statically, so
749 * we just enable all vectors on init and after reset. */
082751e8 750static void ivshmem_msix_vector_use(IVShmemState *s)
4490c711 751{
b7578eaa 752 PCIDevice *d = PCI_DEVICE(s);
4490c711
MT
753 int i;
754
4490c711 755 for (i = 0; i < s->vectors; i++) {
b7578eaa 756 msix_vector_use(d, i);
4490c711
MT
757 }
758}
759
6cbf4c8c
CM
760static void ivshmem_reset(DeviceState *d)
761{
5400c02b 762 IVShmemState *s = IVSHMEM_COMMON(d);
6cbf4c8c
CM
763
764 s->intrstatus = 0;
972ad215 765 s->intrmask = 0;
082751e8
MA
766 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
767 ivshmem_msix_vector_use(s);
768 }
6cbf4c8c
CM
769}
770
ee640c62 771static int ivshmem_setup_interrupts(IVShmemState *s, Error **errp)
4490c711 772{
fd47bfe5
MAL
773 /* allocate QEMU callback data for receiving interrupts */
774 s->msi_vectors = g_malloc0(s->vectors * sizeof(MSIVector));
6cbf4c8c 775
fd47bfe5 776 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
ee640c62 777 if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1, errp)) {
fd47bfe5
MAL
778 return -1;
779 }
1116b539 780
fd47bfe5 781 IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors);
082751e8 782 ivshmem_msix_vector_use(s);
fd47bfe5 783 }
4490c711 784
d58d7e84 785 return 0;
6cbf4c8c
CM
786}
787
660c97ee
MAL
788static void ivshmem_enable_irqfd(IVShmemState *s)
789{
790 PCIDevice *pdev = PCI_DEVICE(s);
791 int i;
792
793 for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) {
1309cf44
MA
794 Error *err = NULL;
795
796 ivshmem_add_kvm_msi_virq(s, i, &err);
797 if (err) {
798 error_report_err(err);
799 /* TODO do we need to handle the error? */
800 }
660c97ee
MAL
801 }
802
803 if (msix_set_vector_notifiers(pdev,
804 ivshmem_vector_unmask,
805 ivshmem_vector_mask,
806 ivshmem_vector_poll)) {
807 error_report("ivshmem: msix_set_vector_notifiers failed");
808 }
809}
810
811static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector)
812{
813 IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector);
814
815 if (s->msi_vectors[vector].pdev == NULL) {
816 return;
817 }
818
819 /* it was cleaned when masked in the frontend. */
820 kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq);
821
822 s->msi_vectors[vector].pdev = NULL;
823}
824
825static void ivshmem_disable_irqfd(IVShmemState *s)
826{
827 PCIDevice *pdev = PCI_DEVICE(s);
828 int i;
829
089fd803
LP
830 msix_unset_vector_notifiers(pdev);
831
660c97ee 832 for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) {
089fd803
LP
833 /*
834 * MSI-X is already disabled here so msix_unset_vector_notifiers()
835 * didn't call our release notifier. Do it now to keep our masks and
836 * unmasks balanced.
837 */
838 if (s->msi_vectors[i].unmasked) {
839 ivshmem_vector_mask(pdev, i);
840 }
660c97ee
MAL
841 ivshmem_remove_kvm_msi_virq(s, i);
842 }
843
660c97ee
MAL
844}
845
846static void ivshmem_write_config(PCIDevice *pdev, uint32_t address,
d58d7e84 847 uint32_t val, int len)
4490c711 848{
5400c02b 849 IVShmemState *s = IVSHMEM_COMMON(pdev);
660c97ee
MAL
850 int is_enabled, was_enabled = msix_enabled(pdev);
851
852 pci_default_write_config(pdev, address, val, len);
853 is_enabled = msix_enabled(pdev);
854
1309cf44 855 if (kvm_msi_via_irqfd_enabled()) {
660c97ee
MAL
856 if (!was_enabled && is_enabled) {
857 ivshmem_enable_irqfd(s);
858 } else if (was_enabled && !is_enabled) {
859 ivshmem_disable_irqfd(s);
860 }
861 }
4490c711
MT
862}
863
5400c02b 864static void ivshmem_common_realize(PCIDevice *dev, Error **errp)
6cbf4c8c 865{
5400c02b 866 IVShmemState *s = IVSHMEM_COMMON(dev);
d855e275 867 Error *err = NULL;
6cbf4c8c 868 uint8_t *pci_conf;
9113e3f3
MAL
869 uint8_t attr = PCI_BASE_ADDRESS_SPACE_MEMORY |
870 PCI_BASE_ADDRESS_MEM_PREFETCH;
fe44dc91 871 Error *local_err = NULL;
6cbf4c8c 872
6cbf4c8c
CM
873 /* IRQFD requires MSI */
874 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) &&
875 !ivshmem_has_feature(s, IVSHMEM_MSI)) {
d58d7e84
MAL
876 error_setg(errp, "ioeventfd/irqfd requires MSI");
877 return;
6cbf4c8c
CM
878 }
879
b7578eaa 880 pci_conf = dev->config;
6cbf4c8c 881 pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
6cbf4c8c 882
3c161542 883 memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s,
cb06608e
AK
884 "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE);
885
6cbf4c8c 886 /* region for registers*/
b7578eaa 887 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
e824b2cc 888 &s->ivshmem_mmio);
cb06608e 889
b2b79a69 890 if (s->not_legacy_32bit) {
9113e3f3 891 attr |= PCI_BASE_ADDRESS_MEM_TYPE_64;
c08ba66f 892 }
6cbf4c8c 893
d9453c93 894 if (s->hostmem != NULL) {
d9453c93
MAL
895 IVSHMEM_DPRINTF("using hostmem\n");
896
c2d8019c
MA
897 s->ivshmem_bar2 = host_memory_backend_get_memory(s->hostmem,
898 &error_abort);
5503e285 899 } else {
0ec7b3e7 900 Chardev *chr = qemu_chr_fe_get_driver(&s->server_chr);
5345fdb4 901 assert(chr);
6dc64780 902
6cbf4c8c 903 IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n",
5345fdb4 904 chr->filename);
6cbf4c8c 905
f456179f 906 /* we allocate enough space for 16 peers and grow as needed */
1300b273 907 resize_peers(s, 16);
6cbf4c8c 908
3a55fc0f
MA
909 /*
910 * Receive setup messages from server synchronously.
911 * Older versions did it asynchronously, but that creates a
912 * number of entertaining race conditions.
3a55fc0f 913 */
1309cf44
MA
914 ivshmem_recv_setup(s, &err);
915 if (err) {
916 error_propagate(errp, err);
917 return;
3a55fc0f
MA
918 }
919
62a830b6
MA
920 if (s->master == ON_OFF_AUTO_ON && s->vm_id != 0) {
921 error_setg(errp,
922 "master must connect to the server before any peers");
923 return;
924 }
925
5345fdb4 926 qemu_chr_fe_set_handlers(&s->server_chr, ivshmem_can_receive,
81517ba3 927 ivshmem_read, NULL, NULL, s, NULL, true);
1309cf44 928
ee640c62
C
929 if (ivshmem_setup_interrupts(s, errp) < 0) {
930 error_prepend(errp, "Failed to initialize interrupts: ");
3a55fc0f
MA
931 return;
932 }
d855e275
MA
933 }
934
2a845da7
MA
935 if (s->master == ON_OFF_AUTO_AUTO) {
936 s->master = s->vm_id == 0 ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
937 }
938
939 if (!ivshmem_is_master(s)) {
d855e275
MA
940 error_setg(&s->migration_blocker,
941 "Migration is disabled when using feature 'peer mode' in device 'ivshmem'");
fe44dc91
AA
942 migrate_add_blocker(s->migration_blocker, &local_err);
943 if (local_err) {
944 error_propagate(errp, local_err);
945 error_free(s->migration_blocker);
946 return;
947 }
6cbf4c8c 948 }
fe44dc91
AA
949
950 vmstate_register_ram(s->ivshmem_bar2, DEVICE(s));
951 pci_register_bar(PCI_DEVICE(s), 2, attr, s->ivshmem_bar2);
6cbf4c8c
CM
952}
953
5400c02b
MA
954static void ivshmem_exit(PCIDevice *dev)
955{
956 IVShmemState *s = IVSHMEM_COMMON(dev);
f64a078d
MAL
957 int i;
958
38e0735e
AL
959 if (s->migration_blocker) {
960 migrate_del_blocker(s->migration_blocker);
961 error_free(s->migration_blocker);
962 }
963
c2d8019c 964 if (memory_region_is_mapped(s->ivshmem_bar2)) {
d9453c93 965 if (!s->hostmem) {
c2d8019c 966 void *addr = memory_region_get_ram_ptr(s->ivshmem_bar2);
56a571d9 967 int fd;
d9453c93 968
5400c02b 969 if (munmap(addr, memory_region_size(s->ivshmem_bar2) == -1)) {
d9453c93
MAL
970 error_report("Failed to munmap shared memory %s",
971 strerror(errno));
972 }
56a571d9 973
4ff87573 974 fd = memory_region_get_fd(s->ivshmem_bar2);
c2d8019c 975 close(fd);
d9453c93 976 }
f64a078d 977
c2d8019c 978 vmstate_unregister_ram(s->ivshmem_bar2, DEVICE(dev));
f64a078d
MAL
979 }
980
f64a078d
MAL
981 if (s->peers) {
982 for (i = 0; i < s->nb_peers; i++) {
f456179f 983 close_peer_eventfds(s, i);
f64a078d
MAL
984 }
985 g_free(s->peers);
986 }
987
988 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
989 msix_uninit_exclusive_bar(dev);
990 }
991
0f57350e 992 g_free(s->msi_vectors);
6cbf4c8c
CM
993}
994
1f8552df
MAL
995static int ivshmem_pre_load(void *opaque)
996{
997 IVShmemState *s = opaque;
998
2a845da7 999 if (!ivshmem_is_master(s)) {
1f8552df
MAL
1000 error_report("'peer' devices are not migratable");
1001 return -EINVAL;
1002 }
1003
1004 return 0;
1005}
1006
1007static int ivshmem_post_load(void *opaque, int version_id)
1008{
1009 IVShmemState *s = opaque;
1010
1011 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
082751e8 1012 ivshmem_msix_vector_use(s);
1f8552df 1013 }
1f8552df
MAL
1014 return 0;
1015}
1016
5400c02b 1017static void ivshmem_common_class_init(ObjectClass *klass, void *data)
40021f08 1018{
39bffca2 1019 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL
1020 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1021
5400c02b
MA
1022 k->realize = ivshmem_common_realize;
1023 k->exit = ivshmem_exit;
d58d7e84 1024 k->config_write = ivshmem_write_config;
b8ef62a9
PB
1025 k->vendor_id = PCI_VENDOR_ID_IVSHMEM;
1026 k->device_id = PCI_DEVICE_ID_IVSHMEM;
40021f08 1027 k->class_id = PCI_CLASS_MEMORY_RAM;
5400c02b 1028 k->revision = 1;
39bffca2 1029 dc->reset = ivshmem_reset;
125ee0ed 1030 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
d383537d 1031 dc->desc = "Inter-VM shared memory";
40021f08
AL
1032}
1033
ddc85284
MA
1034static const TypeInfo ivshmem_common_info = {
1035 .name = TYPE_IVSHMEM_COMMON,
1036 .parent = TYPE_PCI_DEVICE,
1037 .instance_size = sizeof(IVShmemState),
1038 .abstract = true,
1039 .class_init = ivshmem_common_class_init,
fd3b02c8
EH
1040 .interfaces = (InterfaceInfo[]) {
1041 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1042 { },
1043 },
ddc85284 1044};
5400c02b 1045
5400c02b
MA
1046static const VMStateDescription ivshmem_plain_vmsd = {
1047 .name = TYPE_IVSHMEM_PLAIN,
1048 .version_id = 0,
1049 .minimum_version_id = 0,
1050 .pre_load = ivshmem_pre_load,
1051 .post_load = ivshmem_post_load,
1052 .fields = (VMStateField[]) {
1053 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1054 VMSTATE_UINT32(intrstatus, IVShmemState),
1055 VMSTATE_UINT32(intrmask, IVShmemState),
1056 VMSTATE_END_OF_LIST()
1057 },
1058};
1059
1060static Property ivshmem_plain_properties[] = {
1061 DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
e9cb190a
FZ
1062 DEFINE_PROP_LINK("memdev", IVShmemState, hostmem, TYPE_MEMORY_BACKEND,
1063 HostMemoryBackend *),
5400c02b
MA
1064 DEFINE_PROP_END_OF_LIST(),
1065};
1066
1067static void ivshmem_plain_init(Object *obj)
1068{
1069 IVShmemState *s = IVSHMEM_PLAIN(obj);
1070
b2b79a69 1071 s->not_legacy_32bit = 1;
5400c02b
MA
1072}
1073
6dc64780
MAL
1074static void ivshmem_plain_realize(PCIDevice *dev, Error **errp)
1075{
1076 IVShmemState *s = IVSHMEM_COMMON(dev);
1077
1078 if (!s->hostmem) {
1079 error_setg(errp, "You must specify a 'memdev'");
1080 return;
e9cb190a
FZ
1081 } else if (host_memory_backend_is_mapped(s->hostmem)) {
1082 char *path = object_get_canonical_path_component(OBJECT(s->hostmem));
1083 error_setg(errp, "can't use already busy memdev: %s", path);
1084 g_free(path);
1085 return;
6dc64780
MAL
1086 }
1087
1088 ivshmem_common_realize(dev, errp);
2aece63c
XG
1089 host_memory_backend_set_mapped(s->hostmem, true);
1090}
1091
1092static void ivshmem_plain_exit(PCIDevice *pci_dev)
1093{
1094 IVShmemState *s = IVSHMEM_COMMON(pci_dev);
1095
1096 host_memory_backend_set_mapped(s->hostmem, false);
6dc64780
MAL
1097}
1098
5400c02b
MA
1099static void ivshmem_plain_class_init(ObjectClass *klass, void *data)
1100{
1101 DeviceClass *dc = DEVICE_CLASS(klass);
6dc64780 1102 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
5400c02b 1103
6dc64780 1104 k->realize = ivshmem_plain_realize;
2aece63c 1105 k->exit = ivshmem_plain_exit;
5400c02b
MA
1106 dc->props = ivshmem_plain_properties;
1107 dc->vmsd = &ivshmem_plain_vmsd;
1108}
1109
1110static const TypeInfo ivshmem_plain_info = {
1111 .name = TYPE_IVSHMEM_PLAIN,
1112 .parent = TYPE_IVSHMEM_COMMON,
1113 .instance_size = sizeof(IVShmemState),
1114 .instance_init = ivshmem_plain_init,
1115 .class_init = ivshmem_plain_class_init,
1116};
1117
1118static const VMStateDescription ivshmem_doorbell_vmsd = {
1119 .name = TYPE_IVSHMEM_DOORBELL,
1120 .version_id = 0,
1121 .minimum_version_id = 0,
1122 .pre_load = ivshmem_pre_load,
1123 .post_load = ivshmem_post_load,
1124 .fields = (VMStateField[]) {
1125 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1126 VMSTATE_MSIX(parent_obj, IVShmemState),
1127 VMSTATE_UINT32(intrstatus, IVShmemState),
1128 VMSTATE_UINT32(intrmask, IVShmemState),
1129 VMSTATE_END_OF_LIST()
1130 },
1131};
1132
1133static Property ivshmem_doorbell_properties[] = {
1134 DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
1135 DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
1136 DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD,
1137 true),
1138 DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
1139 DEFINE_PROP_END_OF_LIST(),
1140};
1141
1142static void ivshmem_doorbell_init(Object *obj)
1143{
1144 IVShmemState *s = IVSHMEM_DOORBELL(obj);
1145
1146 s->features |= (1 << IVSHMEM_MSI);
1147 s->legacy_size = SIZE_MAX; /* whatever the server sends */
b2b79a69 1148 s->not_legacy_32bit = 1;
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MA
1149}
1150
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MAL
1151static void ivshmem_doorbell_realize(PCIDevice *dev, Error **errp)
1152{
1153 IVShmemState *s = IVSHMEM_COMMON(dev);
1154
30650701 1155 if (!qemu_chr_fe_backend_connected(&s->server_chr)) {
6dc64780
MAL
1156 error_setg(errp, "You must specify a 'chardev'");
1157 return;
1158 }
1159
1160 ivshmem_common_realize(dev, errp);
1161}
1162
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MA
1163static void ivshmem_doorbell_class_init(ObjectClass *klass, void *data)
1164{
1165 DeviceClass *dc = DEVICE_CLASS(klass);
6dc64780 1166 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
5400c02b 1167
6dc64780 1168 k->realize = ivshmem_doorbell_realize;
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MA
1169 dc->props = ivshmem_doorbell_properties;
1170 dc->vmsd = &ivshmem_doorbell_vmsd;
1171}
1172
1173static const TypeInfo ivshmem_doorbell_info = {
1174 .name = TYPE_IVSHMEM_DOORBELL,
1175 .parent = TYPE_IVSHMEM_COMMON,
1176 .instance_size = sizeof(IVShmemState),
1177 .instance_init = ivshmem_doorbell_init,
1178 .class_init = ivshmem_doorbell_class_init,
1179};
1180
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MA
1181static int ivshmem_load_old(QEMUFile *f, void *opaque, int version_id)
1182{
1183 IVShmemState *s = opaque;
1184 PCIDevice *pdev = PCI_DEVICE(s);
1185 int ret;
1186
1187 IVSHMEM_DPRINTF("ivshmem_load_old\n");
1188
1189 if (version_id != 0) {
1190 return -EINVAL;
1191 }
1192
1193 ret = ivshmem_pre_load(s);
1194 if (ret) {
1195 return ret;
1196 }
1197
1198 ret = pci_device_load(pdev, f);
1199 if (ret) {
1200 return ret;
1201 }
1202
1203 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
1204 msix_load(pdev, f);
1205 ivshmem_msix_vector_use(s);
1206 } else {
1207 s->intrstatus = qemu_get_be32(f);
1208 s->intrmask = qemu_get_be32(f);
1209 }
1210
1211 return 0;
1212}
1213
1214static bool test_msix(void *opaque, int version_id)
1215{
1216 IVShmemState *s = opaque;
1217
1218 return ivshmem_has_feature(s, IVSHMEM_MSI);
1219}
1220
1221static bool test_no_msix(void *opaque, int version_id)
1222{
1223 return !test_msix(opaque, version_id);
1224}
1225
1226static const VMStateDescription ivshmem_vmsd = {
1227 .name = "ivshmem",
1228 .version_id = 1,
1229 .minimum_version_id = 1,
1230 .pre_load = ivshmem_pre_load,
1231 .post_load = ivshmem_post_load,
1232 .fields = (VMStateField[]) {
1233 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1234
1235 VMSTATE_MSIX_TEST(parent_obj, IVShmemState, test_msix),
1236 VMSTATE_UINT32_TEST(intrstatus, IVShmemState, test_no_msix),
1237 VMSTATE_UINT32_TEST(intrmask, IVShmemState, test_no_msix),
1238
1239 VMSTATE_END_OF_LIST()
1240 },
1241 .load_state_old = ivshmem_load_old,
1242 .minimum_version_id_old = 0
1243};
1244
1245static Property ivshmem_properties[] = {
1246 DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
1247 DEFINE_PROP_STRING("size", IVShmemState, sizearg),
1248 DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
1249 DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD,
1250 false),
1251 DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true),
1252 DEFINE_PROP_STRING("shm", IVShmemState, shmobj),
1253 DEFINE_PROP_STRING("role", IVShmemState, role),
1254 DEFINE_PROP_UINT32("use64", IVShmemState, not_legacy_32bit, 1),
1255 DEFINE_PROP_END_OF_LIST(),
1256};
1257
1258static void desugar_shm(IVShmemState *s)
1259{
1260 Object *obj;
1261 char *path;
1262
1263 obj = object_new("memory-backend-file");
1264 path = g_strdup_printf("/dev/shm/%s", s->shmobj);
1265 object_property_set_str(obj, path, "mem-path", &error_abort);
1266 g_free(path);
1267 object_property_set_int(obj, s->legacy_size, "size", &error_abort);
1268 object_property_set_bool(obj, true, "share", &error_abort);
1269 object_property_add_child(OBJECT(s), "internal-shm-backend", obj,
1270 &error_abort);
1271 user_creatable_complete(obj, &error_abort);
1272 s->hostmem = MEMORY_BACKEND(obj);
1273}
1274
1275static void ivshmem_realize(PCIDevice *dev, Error **errp)
1276{
1277 IVShmemState *s = IVSHMEM_COMMON(dev);
1278
1279 if (!qtest_enabled()) {
1280 error_report("ivshmem is deprecated, please use ivshmem-plain"
1281 " or ivshmem-doorbell instead");
1282 }
1283
30650701 1284 if (qemu_chr_fe_backend_connected(&s->server_chr) + !!s->shmobj != 1) {
13fd2cb6 1285 error_setg(errp, "You must specify either 'shm' or 'chardev'");
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MA
1286 return;
1287 }
1288
13fd2cb6 1289 if (s->sizearg == NULL) {
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MA
1290 s->legacy_size = 4 << 20; /* 4 MB default */
1291 } else {
f17fd4fd 1292 int ret;
f46bfdbf 1293 uint64_t size;
f17fd4fd
MA
1294
1295 ret = qemu_strtosz_MiB(s->sizearg, NULL, &size);
1296 if (ret < 0 || (size_t)size != size || !is_power_of_2(size)) {
ddc85284
MA
1297 error_setg(errp, "Invalid size %s", s->sizearg);
1298 return;
1299 }
1300 s->legacy_size = size;
1301 }
1302
1303 /* check that role is reasonable */
1304 if (s->role) {
1305 if (strncmp(s->role, "peer", 5) == 0) {
1306 s->master = ON_OFF_AUTO_OFF;
1307 } else if (strncmp(s->role, "master", 7) == 0) {
1308 s->master = ON_OFF_AUTO_ON;
1309 } else {
1310 error_setg(errp, "'role' must be 'peer' or 'master'");
1311 return;
1312 }
1313 } else {
1314 s->master = ON_OFF_AUTO_AUTO;
1315 }
1316
1317 if (s->shmobj) {
1318 desugar_shm(s);
1319 }
1320
1321 /*
1322 * Note: we don't use INTx with IVSHMEM_MSI at all, so this is a
1323 * bald-faced lie then. But it's a backwards compatible lie.
1324 */
1325 pci_config_set_interrupt_pin(dev->config, 1);
1326
1327 ivshmem_common_realize(dev, errp);
1328}
1329
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1330static void ivshmem_class_init(ObjectClass *klass, void *data)
1331{
1332 DeviceClass *dc = DEVICE_CLASS(klass);
1333 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1334
1335 k->realize = ivshmem_realize;
1336 k->revision = 0;
1337 dc->desc = "Inter-VM shared memory (legacy)";
1338 dc->props = ivshmem_properties;
1339 dc->vmsd = &ivshmem_vmsd;
1340}
1341
1342static const TypeInfo ivshmem_info = {
1343 .name = TYPE_IVSHMEM,
1344 .parent = TYPE_IVSHMEM_COMMON,
1345 .instance_size = sizeof(IVShmemState),
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MA
1346 .class_init = ivshmem_class_init,
1347};
1348
83f7d43a 1349static void ivshmem_register_types(void)
6cbf4c8c 1350{
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MA
1351 type_register_static(&ivshmem_common_info);
1352 type_register_static(&ivshmem_plain_info);
1353 type_register_static(&ivshmem_doorbell_info);
39bffca2 1354 type_register_static(&ivshmem_info);
6cbf4c8c
CM
1355}
1356
83f7d43a 1357type_init(ivshmem_register_types)