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Commit | Line | Data |
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6cbf4c8c CM |
1 | /* |
2 | * Inter-VM Shared Memory PCI device. | |
3 | * | |
4 | * Author: | |
5 | * Cam Macdonell <cam@cs.ualberta.ca> | |
6 | * | |
7 | * Based On: cirrus_vga.c | |
8 | * Copyright (c) 2004 Fabrice Bellard | |
9 | * Copyright (c) 2004 Makoto Suzuki (suzu) | |
10 | * | |
11 | * and rtl8139.c | |
12 | * Copyright (c) 2006 Igor Kovalenko | |
13 | * | |
14 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
15 | * |
16 | * Contributions after 2012-01-13 are licensed under the terms of the | |
17 | * GNU GPL, version 2 or (at your option) any later version. | |
6cbf4c8c | 18 | */ |
0b8fa32f | 19 | |
0d1c9782 | 20 | #include "qemu/osdep.h" |
519abcdf | 21 | #include "qemu/units.h" |
da34e65c | 22 | #include "qapi/error.h" |
f348b6d1 | 23 | #include "qemu/cutils.h" |
83c9f4ca | 24 | #include "hw/pci/pci.h" |
a27bd6c7 | 25 | #include "hw/qdev-properties.h" |
ce35e229 | 26 | #include "hw/qdev-properties-system.h" |
660c97ee | 27 | #include "hw/pci/msi.h" |
83c9f4ca | 28 | #include "hw/pci/msix.h" |
9c17d615 | 29 | #include "sysemu/kvm.h" |
795c40b8 | 30 | #include "migration/blocker.h" |
d6454270 | 31 | #include "migration/vmstate.h" |
d49b6836 | 32 | #include "qemu/error-report.h" |
1de7afc9 | 33 | #include "qemu/event_notifier.h" |
0b8fa32f | 34 | #include "qemu/module.h" |
5503e285 | 35 | #include "qom/object_interfaces.h" |
4d43a603 | 36 | #include "chardev/char-fe.h" |
d9453c93 MAL |
37 | #include "sysemu/hostmem.h" |
38 | #include "qapi/visitor.h" | |
6cbf4c8c | 39 | |
5105b1d8 | 40 | #include "hw/misc/ivshmem.h" |
db1015e9 | 41 | #include "qom/object.h" |
5105b1d8 | 42 | |
b8ef62a9 PB |
43 | #define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET |
44 | #define PCI_DEVICE_ID_IVSHMEM 0x1110 | |
45 | ||
cd9953f7 | 46 | #define IVSHMEM_MAX_PEERS UINT16_MAX |
6cbf4c8c CM |
47 | #define IVSHMEM_IOEVENTFD 0 |
48 | #define IVSHMEM_MSI 1 | |
49 | ||
6cbf4c8c CM |
50 | #define IVSHMEM_REG_BAR_SIZE 0x100 |
51 | ||
a4fa93bf MA |
52 | #define IVSHMEM_DEBUG 0 |
53 | #define IVSHMEM_DPRINTF(fmt, ...) \ | |
54 | do { \ | |
55 | if (IVSHMEM_DEBUG) { \ | |
56 | printf("IVSHMEM: " fmt, ## __VA_ARGS__); \ | |
57 | } \ | |
58 | } while (0) | |
6cbf4c8c | 59 | |
5400c02b | 60 | #define TYPE_IVSHMEM_COMMON "ivshmem-common" |
db1015e9 | 61 | typedef struct IVShmemState IVShmemState; |
8110fa1d EH |
62 | DECLARE_INSTANCE_CHECKER(IVShmemState, IVSHMEM_COMMON, |
63 | TYPE_IVSHMEM_COMMON) | |
5400c02b MA |
64 | |
65 | #define TYPE_IVSHMEM_PLAIN "ivshmem-plain" | |
8110fa1d EH |
66 | DECLARE_INSTANCE_CHECKER(IVShmemState, IVSHMEM_PLAIN, |
67 | TYPE_IVSHMEM_PLAIN) | |
5400c02b MA |
68 | |
69 | #define TYPE_IVSHMEM_DOORBELL "ivshmem-doorbell" | |
8110fa1d EH |
70 | DECLARE_INSTANCE_CHECKER(IVShmemState, IVSHMEM_DOORBELL, |
71 | TYPE_IVSHMEM_DOORBELL) | |
5400c02b | 72 | |
eb3fedf3 | 73 | #define TYPE_IVSHMEM "ivshmem" |
8110fa1d EH |
74 | DECLARE_INSTANCE_CHECKER(IVShmemState, IVSHMEM, |
75 | TYPE_IVSHMEM) | |
eb3fedf3 | 76 | |
6cbf4c8c CM |
77 | typedef struct Peer { |
78 | int nb_eventfds; | |
563027cc | 79 | EventNotifier *eventfds; |
6cbf4c8c CM |
80 | } Peer; |
81 | ||
0f57350e | 82 | typedef struct MSIVector { |
6cbf4c8c | 83 | PCIDevice *pdev; |
660c97ee | 84 | int virq; |
089fd803 | 85 | bool unmasked; |
0f57350e | 86 | } MSIVector; |
6cbf4c8c | 87 | |
db1015e9 | 88 | struct IVShmemState { |
b7578eaa AF |
89 | /*< private >*/ |
90 | PCIDevice parent_obj; | |
91 | /*< public >*/ | |
92 | ||
ddc85284 MA |
93 | uint32_t features; |
94 | ||
95 | /* exactly one of these two may be set */ | |
96 | HostMemoryBackend *hostmem; /* with interrupts */ | |
becdfa00 | 97 | CharBackend server_chr; /* without interrupts */ |
ddc85284 MA |
98 | |
99 | /* registers */ | |
6cbf4c8c CM |
100 | uint32_t intrmask; |
101 | uint32_t intrstatus; | |
ddc85284 | 102 | int vm_id; |
6cbf4c8c | 103 | |
ddc85284 MA |
104 | /* BARs */ |
105 | MemoryRegion ivshmem_mmio; /* BAR 0 (registers) */ | |
c2d8019c MA |
106 | MemoryRegion *ivshmem_bar2; /* BAR 2 (shared memory) */ |
107 | MemoryRegion server_bar2; /* used with server_chr */ | |
6cbf4c8c | 108 | |
ddc85284 | 109 | /* interrupt support */ |
6cbf4c8c | 110 | Peer *peers; |
cd9953f7 | 111 | int nb_peers; /* space in @peers[] */ |
6cbf4c8c | 112 | uint32_t vectors; |
0f57350e | 113 | MSIVector *msi_vectors; |
ee276391 MA |
114 | uint64_t msg_buf; /* buffer for receiving server messages */ |
115 | int msg_buffered_bytes; /* #bytes in @msg_buf */ | |
6cbf4c8c | 116 | |
ddc85284 | 117 | /* migration stuff */ |
2a845da7 | 118 | OnOffAuto master; |
38e0735e | 119 | Error *migration_blocker; |
db1015e9 | 120 | }; |
6cbf4c8c CM |
121 | |
122 | /* registers for the Inter-VM shared memory device */ | |
123 | enum ivshmem_registers { | |
124 | INTRMASK = 0, | |
125 | INTRSTATUS = 4, | |
126 | IVPOSITION = 8, | |
127 | DOORBELL = 12, | |
128 | }; | |
129 | ||
130 | static inline uint32_t ivshmem_has_feature(IVShmemState *ivs, | |
131 | unsigned int feature) { | |
132 | return (ivs->features & (1 << feature)); | |
133 | } | |
134 | ||
2a845da7 MA |
135 | static inline bool ivshmem_is_master(IVShmemState *s) |
136 | { | |
137 | assert(s->master != ON_OFF_AUTO_AUTO); | |
138 | return s->master == ON_OFF_AUTO_ON; | |
139 | } | |
140 | ||
6cbf4c8c CM |
141 | static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val) |
142 | { | |
143 | IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val); | |
144 | ||
145 | s->intrmask = val; | |
6cbf4c8c CM |
146 | } |
147 | ||
148 | static uint32_t ivshmem_IntrMask_read(IVShmemState *s) | |
149 | { | |
150 | uint32_t ret = s->intrmask; | |
151 | ||
152 | IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret); | |
6cbf4c8c CM |
153 | return ret; |
154 | } | |
155 | ||
156 | static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val) | |
157 | { | |
158 | IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val); | |
159 | ||
160 | s->intrstatus = val; | |
6cbf4c8c CM |
161 | } |
162 | ||
163 | static uint32_t ivshmem_IntrStatus_read(IVShmemState *s) | |
164 | { | |
165 | uint32_t ret = s->intrstatus; | |
166 | ||
167 | /* reading ISR clears all interrupts */ | |
168 | s->intrstatus = 0; | |
6cbf4c8c CM |
169 | return ret; |
170 | } | |
171 | ||
a8170e5e | 172 | static void ivshmem_io_write(void *opaque, hwaddr addr, |
cb06608e | 173 | uint64_t val, unsigned size) |
6cbf4c8c CM |
174 | { |
175 | IVShmemState *s = opaque; | |
176 | ||
6cbf4c8c CM |
177 | uint16_t dest = val >> 16; |
178 | uint16_t vector = val & 0xff; | |
179 | ||
180 | addr &= 0xfc; | |
181 | ||
182 | IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr); | |
183 | switch (addr) | |
184 | { | |
185 | case INTRMASK: | |
186 | ivshmem_IntrMask_write(s, val); | |
187 | break; | |
188 | ||
189 | case INTRSTATUS: | |
190 | ivshmem_IntrStatus_write(s, val); | |
191 | break; | |
192 | ||
193 | case DOORBELL: | |
194 | /* check that dest VM ID is reasonable */ | |
95c8425c | 195 | if (dest >= s->nb_peers) { |
6cbf4c8c CM |
196 | IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest); |
197 | break; | |
198 | } | |
199 | ||
200 | /* check doorbell range */ | |
1b27d7a1 | 201 | if (vector < s->peers[dest].nb_eventfds) { |
563027cc PB |
202 | IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector); |
203 | event_notifier_set(&s->peers[dest].eventfds[vector]); | |
f59bb378 MAL |
204 | } else { |
205 | IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n", | |
206 | vector, dest); | |
6cbf4c8c CM |
207 | } |
208 | break; | |
209 | default: | |
f59bb378 | 210 | IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr); |
6cbf4c8c CM |
211 | } |
212 | } | |
213 | ||
a8170e5e | 214 | static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, |
cb06608e | 215 | unsigned size) |
6cbf4c8c CM |
216 | { |
217 | ||
218 | IVShmemState *s = opaque; | |
219 | uint32_t ret; | |
220 | ||
221 | switch (addr) | |
222 | { | |
223 | case INTRMASK: | |
224 | ret = ivshmem_IntrMask_read(s); | |
225 | break; | |
226 | ||
227 | case INTRSTATUS: | |
228 | ret = ivshmem_IntrStatus_read(s); | |
229 | break; | |
230 | ||
231 | case IVPOSITION: | |
1309cf44 | 232 | ret = s->vm_id; |
6cbf4c8c CM |
233 | break; |
234 | ||
235 | default: | |
236 | IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr); | |
237 | ret = 0; | |
238 | } | |
239 | ||
240 | return ret; | |
241 | } | |
242 | ||
cb06608e AK |
243 | static const MemoryRegionOps ivshmem_mmio_ops = { |
244 | .read = ivshmem_io_read, | |
245 | .write = ivshmem_io_write, | |
ef80a708 | 246 | .endianness = DEVICE_LITTLE_ENDIAN, |
cb06608e AK |
247 | .impl = { |
248 | .min_access_size = 4, | |
249 | .max_access_size = 4, | |
250 | }, | |
6cbf4c8c CM |
251 | }; |
252 | ||
9940c323 MAL |
253 | static void ivshmem_vector_notify(void *opaque) |
254 | { | |
0f57350e | 255 | MSIVector *entry = opaque; |
6cbf4c8c | 256 | PCIDevice *pdev = entry->pdev; |
5400c02b | 257 | IVShmemState *s = IVSHMEM_COMMON(pdev); |
0f57350e | 258 | int vector = entry - s->msi_vectors; |
9940c323 MAL |
259 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
260 | ||
261 | if (!event_notifier_test_and_clear(n)) { | |
262 | return; | |
263 | } | |
6cbf4c8c | 264 | |
d160f3f7 | 265 | IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector); |
9940c323 | 266 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
082751e8 MA |
267 | if (msix_enabled(pdev)) { |
268 | msix_notify(pdev, vector); | |
269 | } | |
9940c323 MAL |
270 | } else { |
271 | ivshmem_IntrStatus_write(s, 1); | |
272 | } | |
6cbf4c8c CM |
273 | } |
274 | ||
660c97ee MAL |
275 | static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector, |
276 | MSIMessage msg) | |
277 | { | |
5400c02b | 278 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee MAL |
279 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
280 | MSIVector *v = &s->msi_vectors[vector]; | |
281 | int ret; | |
282 | ||
283 | IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector); | |
e6a354be LP |
284 | if (!v->pdev) { |
285 | error_report("ivshmem: vector %d route does not exist", vector); | |
286 | return -EINVAL; | |
287 | } | |
089fd803 | 288 | assert(!v->unmasked); |
660c97ee MAL |
289 | |
290 | ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev); | |
291 | if (ret < 0) { | |
292 | return ret; | |
293 | } | |
3f1fea0f | 294 | kvm_irqchip_commit_routes(kvm_state); |
660c97ee | 295 | |
089fd803 LP |
296 | ret = kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq); |
297 | if (ret < 0) { | |
298 | return ret; | |
299 | } | |
300 | v->unmasked = true; | |
301 | ||
302 | return 0; | |
660c97ee MAL |
303 | } |
304 | ||
305 | static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector) | |
306 | { | |
5400c02b | 307 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee | 308 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
e6a354be | 309 | MSIVector *v = &s->msi_vectors[vector]; |
660c97ee MAL |
310 | int ret; |
311 | ||
312 | IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector); | |
e6a354be LP |
313 | if (!v->pdev) { |
314 | error_report("ivshmem: vector %d route does not exist", vector); | |
315 | return; | |
316 | } | |
089fd803 | 317 | assert(v->unmasked); |
660c97ee | 318 | |
e6a354be | 319 | ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, v->virq); |
089fd803 | 320 | if (ret < 0) { |
660c97ee | 321 | error_report("remove_irqfd_notifier_gsi failed"); |
089fd803 | 322 | return; |
660c97ee | 323 | } |
089fd803 | 324 | v->unmasked = false; |
660c97ee MAL |
325 | } |
326 | ||
327 | static void ivshmem_vector_poll(PCIDevice *dev, | |
328 | unsigned int vector_start, | |
329 | unsigned int vector_end) | |
330 | { | |
5400c02b | 331 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee MAL |
332 | unsigned int vector; |
333 | ||
334 | IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end); | |
335 | ||
336 | vector_end = MIN(vector_end, s->vectors); | |
337 | ||
338 | for (vector = vector_start; vector < vector_end; vector++) { | |
339 | EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector]; | |
340 | ||
341 | if (!msix_is_masked(dev, vector)) { | |
342 | continue; | |
343 | } | |
344 | ||
345 | if (event_notifier_test_and_clear(notifier)) { | |
346 | msix_set_pending(dev, vector); | |
347 | } | |
348 | } | |
349 | } | |
350 | ||
9940c323 MAL |
351 | static void watch_vector_notifier(IVShmemState *s, EventNotifier *n, |
352 | int vector) | |
6cbf4c8c | 353 | { |
563027cc | 354 | int eventfd = event_notifier_get_fd(n); |
6cbf4c8c | 355 | |
3c27969b | 356 | assert(!s->msi_vectors[vector].pdev); |
9940c323 | 357 | s->msi_vectors[vector].pdev = PCI_DEVICE(s); |
6cbf4c8c | 358 | |
9940c323 MAL |
359 | qemu_set_fd_handler(eventfd, ivshmem_vector_notify, |
360 | NULL, &s->msi_vectors[vector]); | |
6cbf4c8c CM |
361 | } |
362 | ||
563027cc PB |
363 | static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i) |
364 | { | |
365 | memory_region_add_eventfd(&s->ivshmem_mmio, | |
366 | DOORBELL, | |
367 | 4, | |
368 | true, | |
369 | (posn << 16) | i, | |
753d5e14 | 370 | &s->peers[posn].eventfds[i]); |
563027cc PB |
371 | } |
372 | ||
373 | static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i) | |
374 | { | |
375 | memory_region_del_eventfd(&s->ivshmem_mmio, | |
376 | DOORBELL, | |
377 | 4, | |
378 | true, | |
379 | (posn << 16) | i, | |
753d5e14 | 380 | &s->peers[posn].eventfds[i]); |
563027cc PB |
381 | } |
382 | ||
f456179f | 383 | static void close_peer_eventfds(IVShmemState *s, int posn) |
6cbf4c8c | 384 | { |
f456179f | 385 | int i, n; |
6cbf4c8c | 386 | |
9db51b4d | 387 | assert(posn >= 0 && posn < s->nb_peers); |
f456179f | 388 | n = s->peers[posn].nb_eventfds; |
6cbf4c8c | 389 | |
9db51b4d MA |
390 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
391 | memory_region_transaction_begin(); | |
392 | for (i = 0; i < n; i++) { | |
393 | ivshmem_del_eventfd(s, posn, i); | |
394 | } | |
395 | memory_region_transaction_commit(); | |
b6a1f3a5 | 396 | } |
9db51b4d | 397 | |
f456179f | 398 | for (i = 0; i < n; i++) { |
563027cc | 399 | event_notifier_cleanup(&s->peers[posn].eventfds[i]); |
6cbf4c8c CM |
400 | } |
401 | ||
7267c094 | 402 | g_free(s->peers[posn].eventfds); |
6cbf4c8c CM |
403 | s->peers[posn].nb_eventfds = 0; |
404 | } | |
405 | ||
cd9953f7 | 406 | static void resize_peers(IVShmemState *s, int nb_peers) |
34bc07c5 | 407 | { |
cd9953f7 MA |
408 | int old_nb_peers = s->nb_peers; |
409 | int i; | |
6cbf4c8c | 410 | |
cd9953f7 MA |
411 | assert(nb_peers > old_nb_peers); |
412 | IVSHMEM_DPRINTF("bumping storage to %d peers\n", nb_peers); | |
6cbf4c8c | 413 | |
b21e2380 | 414 | s->peers = g_renew(Peer, s->peers, nb_peers); |
cd9953f7 | 415 | s->nb_peers = nb_peers; |
1300b273 | 416 | |
cd9953f7 MA |
417 | for (i = old_nb_peers; i < nb_peers; i++) { |
418 | s->peers[i].eventfds = g_new0(EventNotifier, s->vectors); | |
419 | s->peers[i].nb_eventfds = 0; | |
6cbf4c8c CM |
420 | } |
421 | } | |
422 | ||
1309cf44 MA |
423 | static void ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector, |
424 | Error **errp) | |
660c97ee MAL |
425 | { |
426 | PCIDevice *pdev = PCI_DEVICE(s); | |
def4c557 | 427 | KVMRouteChange c; |
660c97ee MAL |
428 | int ret; |
429 | ||
430 | IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector); | |
3c27969b | 431 | assert(!s->msi_vectors[vector].pdev); |
660c97ee | 432 | |
def4c557 LM |
433 | c = kvm_irqchip_begin_route_changes(kvm_state); |
434 | ret = kvm_irqchip_add_msi_route(&c, vector, pdev); | |
660c97ee | 435 | if (ret < 0) { |
1309cf44 MA |
436 | error_setg(errp, "kvm_irqchip_add_msi_route failed"); |
437 | return; | |
660c97ee | 438 | } |
def4c557 | 439 | kvm_irqchip_commit_route_changes(&c); |
660c97ee MAL |
440 | |
441 | s->msi_vectors[vector].virq = ret; | |
442 | s->msi_vectors[vector].pdev = pdev; | |
660c97ee MAL |
443 | } |
444 | ||
1309cf44 | 445 | static void setup_interrupt(IVShmemState *s, int vector, Error **errp) |
660c97ee MAL |
446 | { |
447 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
448 | bool with_irqfd = kvm_msi_via_irqfd_enabled() && | |
449 | ivshmem_has_feature(s, IVSHMEM_MSI); | |
450 | PCIDevice *pdev = PCI_DEVICE(s); | |
1309cf44 | 451 | Error *err = NULL; |
660c97ee MAL |
452 | |
453 | IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector); | |
454 | ||
455 | if (!with_irqfd) { | |
97553976 | 456 | IVSHMEM_DPRINTF("with eventfd\n"); |
9940c323 | 457 | watch_vector_notifier(s, n, vector); |
660c97ee | 458 | } else if (msix_enabled(pdev)) { |
97553976 | 459 | IVSHMEM_DPRINTF("with irqfd\n"); |
1309cf44 MA |
460 | ivshmem_add_kvm_msi_virq(s, vector, &err); |
461 | if (err) { | |
462 | error_propagate(errp, err); | |
660c97ee MAL |
463 | return; |
464 | } | |
465 | ||
466 | if (!msix_is_masked(pdev, vector)) { | |
467 | kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, | |
468 | s->msi_vectors[vector].virq); | |
1309cf44 | 469 | /* TODO handle error */ |
660c97ee MAL |
470 | } |
471 | } else { | |
472 | /* it will be delayed until msix is enabled, in write_config */ | |
97553976 | 473 | IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n"); |
660c97ee MAL |
474 | } |
475 | } | |
476 | ||
1309cf44 | 477 | static void process_msg_shmem(IVShmemState *s, int fd, Error **errp) |
6cbf4c8c | 478 | { |
8381d89b | 479 | Error *local_err = NULL; |
8baeb22b | 480 | struct stat buf; |
5400c02b | 481 | size_t size; |
6cbf4c8c | 482 | |
c2d8019c | 483 | if (s->ivshmem_bar2) { |
1309cf44 | 484 | error_setg(errp, "server sent unexpected shared memory message"); |
ca0b7566 | 485 | close(fd); |
0f14fd71 | 486 | return; |
a2e9011b SH |
487 | } |
488 | ||
8baeb22b MA |
489 | if (fstat(fd, &buf) < 0) { |
490 | error_setg_errno(errp, errno, | |
491 | "can't determine size of shared memory sent by server"); | |
492 | close(fd); | |
493 | return; | |
494 | } | |
495 | ||
5400c02b MA |
496 | size = buf.st_size; |
497 | ||
ca0b7566 | 498 | /* mmap the region and map into the BAR2 */ |
d5015b80 DH |
499 | memory_region_init_ram_from_fd(&s->server_bar2, OBJECT(s), "ivshmem.bar2", |
500 | size, RAM_SHARED, fd, 0, &local_err); | |
8381d89b MAL |
501 | if (local_err) { |
502 | error_propagate(errp, local_err); | |
ca0b7566 | 503 | return; |
6cbf4c8c | 504 | } |
8381d89b | 505 | |
c2d8019c | 506 | s->ivshmem_bar2 = &s->server_bar2; |
ca0b7566 MA |
507 | } |
508 | ||
1309cf44 MA |
509 | static void process_msg_disconnect(IVShmemState *s, uint16_t posn, |
510 | Error **errp) | |
ca0b7566 MA |
511 | { |
512 | IVSHMEM_DPRINTF("posn %d has gone away\n", posn); | |
9db51b4d | 513 | if (posn >= s->nb_peers || posn == s->vm_id) { |
1309cf44 | 514 | error_setg(errp, "invalid peer %d", posn); |
9db51b4d MA |
515 | return; |
516 | } | |
ca0b7566 MA |
517 | close_peer_eventfds(s, posn); |
518 | } | |
6cbf4c8c | 519 | |
1309cf44 MA |
520 | static void process_msg_connect(IVShmemState *s, uint16_t posn, int fd, |
521 | Error **errp) | |
ca0b7566 MA |
522 | { |
523 | Peer *peer = &s->peers[posn]; | |
524 | int vector; | |
9a2f0e64 | 525 | |
ca0b7566 MA |
526 | /* |
527 | * The N-th connect message for this peer comes with the file | |
528 | * descriptor for vector N-1. Count messages to find the vector. | |
529 | */ | |
530 | if (peer->nb_eventfds >= s->vectors) { | |
1309cf44 MA |
531 | error_setg(errp, "Too many eventfd received, device has %d vectors", |
532 | s->vectors); | |
ca0b7566 | 533 | close(fd); |
6f8a16d5 | 534 | return; |
6cbf4c8c | 535 | } |
ca0b7566 | 536 | vector = peer->nb_eventfds++; |
6cbf4c8c | 537 | |
ca0b7566 MA |
538 | IVSHMEM_DPRINTF("eventfds[%d][%d] = %d\n", posn, vector, fd); |
539 | event_notifier_init_fd(&peer->eventfds[vector], fd); | |
4d14cb0c | 540 | g_unix_set_fd_nonblocking(fd, true, NULL); /* msix/irqfd poll non block */ |
945001a1 | 541 | |
ca0b7566 | 542 | if (posn == s->vm_id) { |
1309cf44 MA |
543 | setup_interrupt(s, vector, errp); |
544 | /* TODO do we need to handle the error? */ | |
ca0b7566 | 545 | } |
6cbf4c8c | 546 | |
ca0b7566 MA |
547 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
548 | ivshmem_add_eventfd(s, posn, vector); | |
549 | } | |
550 | } | |
6cbf4c8c | 551 | |
1309cf44 | 552 | static void process_msg(IVShmemState *s, int64_t msg, int fd, Error **errp) |
ca0b7566 MA |
553 | { |
554 | IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd); | |
6cbf4c8c | 555 | |
ca0b7566 | 556 | if (msg < -1 || msg > IVSHMEM_MAX_PEERS) { |
1309cf44 | 557 | error_setg(errp, "server sent invalid message %" PRId64, msg); |
ca0b7566 | 558 | close(fd); |
6cbf4c8c CM |
559 | return; |
560 | } | |
561 | ||
ca0b7566 | 562 | if (msg == -1) { |
1309cf44 | 563 | process_msg_shmem(s, fd, errp); |
1ee57de4 MAL |
564 | return; |
565 | } | |
566 | ||
ca0b7566 MA |
567 | if (msg >= s->nb_peers) { |
568 | resize_peers(s, msg + 1); | |
569 | } | |
6cbf4c8c | 570 | |
ca0b7566 | 571 | if (fd >= 0) { |
1309cf44 | 572 | process_msg_connect(s, msg, fd, errp); |
ca0b7566 | 573 | } else { |
1309cf44 | 574 | process_msg_disconnect(s, msg, errp); |
6cbf4c8c | 575 | } |
ca0b7566 | 576 | } |
6cbf4c8c | 577 | |
ee276391 MA |
578 | static int ivshmem_can_receive(void *opaque) |
579 | { | |
580 | IVShmemState *s = opaque; | |
581 | ||
582 | assert(s->msg_buffered_bytes < sizeof(s->msg_buf)); | |
583 | return sizeof(s->msg_buf) - s->msg_buffered_bytes; | |
584 | } | |
585 | ||
ca0b7566 MA |
586 | static void ivshmem_read(void *opaque, const uint8_t *buf, int size) |
587 | { | |
588 | IVShmemState *s = opaque; | |
1309cf44 | 589 | Error *err = NULL; |
ca0b7566 MA |
590 | int fd; |
591 | int64_t msg; | |
592 | ||
ee276391 MA |
593 | assert(size >= 0 && s->msg_buffered_bytes + size <= sizeof(s->msg_buf)); |
594 | memcpy((unsigned char *)&s->msg_buf + s->msg_buffered_bytes, buf, size); | |
595 | s->msg_buffered_bytes += size; | |
596 | if (s->msg_buffered_bytes < sizeof(s->msg_buf)) { | |
ca0b7566 | 597 | return; |
6cbf4c8c | 598 | } |
ee276391 MA |
599 | msg = le64_to_cpu(s->msg_buf); |
600 | s->msg_buffered_bytes = 0; | |
ca0b7566 | 601 | |
5345fdb4 | 602 | fd = qemu_chr_fe_get_msgfd(&s->server_chr); |
ca0b7566 | 603 | |
1309cf44 MA |
604 | process_msg(s, msg, fd, &err); |
605 | if (err) { | |
606 | error_report_err(err); | |
607 | } | |
6cbf4c8c CM |
608 | } |
609 | ||
1309cf44 | 610 | static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp) |
5105b1d8 | 611 | { |
3a55fc0f MA |
612 | int64_t msg; |
613 | int n, ret; | |
614 | ||
615 | n = 0; | |
616 | do { | |
5345fdb4 MAL |
617 | ret = qemu_chr_fe_read_all(&s->server_chr, (uint8_t *)&msg + n, |
618 | sizeof(msg) - n); | |
b7b1e9dd PMD |
619 | if (ret < 0) { |
620 | if (ret == -EINTR) { | |
621 | continue; | |
622 | } | |
1309cf44 | 623 | error_setg_errno(errp, -ret, "read from server failed"); |
3a55fc0f MA |
624 | return INT64_MIN; |
625 | } | |
626 | n += ret; | |
627 | } while (n < sizeof(msg)); | |
5105b1d8 | 628 | |
5345fdb4 | 629 | *pfd = qemu_chr_fe_get_msgfd(&s->server_chr); |
51af0ec9 | 630 | return le64_to_cpu(msg); |
3a55fc0f | 631 | } |
5105b1d8 | 632 | |
1309cf44 | 633 | static void ivshmem_recv_setup(IVShmemState *s, Error **errp) |
3a55fc0f | 634 | { |
1309cf44 | 635 | Error *err = NULL; |
3a55fc0f MA |
636 | int64_t msg; |
637 | int fd; | |
638 | ||
1309cf44 MA |
639 | msg = ivshmem_recv_msg(s, &fd, &err); |
640 | if (err) { | |
641 | error_propagate(errp, err); | |
642 | return; | |
643 | } | |
644 | if (msg != IVSHMEM_PROTOCOL_VERSION) { | |
645 | error_setg(errp, "server sent version %" PRId64 ", expecting %d", | |
646 | msg, IVSHMEM_PROTOCOL_VERSION); | |
647 | return; | |
648 | } | |
649 | if (fd != -1) { | |
650 | error_setg(errp, "server sent invalid version message"); | |
5105b1d8 DM |
651 | return; |
652 | } | |
653 | ||
a3feb086 MA |
654 | /* |
655 | * ivshmem-server sends the remaining initial messages in a fixed | |
656 | * order, but the device has always accepted them in any order. | |
657 | * Stay as compatible as practical, just in case people use | |
658 | * servers that behave differently. | |
659 | */ | |
660 | ||
661 | /* | |
662 | * ivshmem_device_spec.txt has always required the ID message | |
663 | * right here, and ivshmem-server has always complied. However, | |
664 | * older versions of the device accepted it out of order, but | |
665 | * broke when an interrupt setup message arrived before it. | |
666 | */ | |
667 | msg = ivshmem_recv_msg(s, &fd, &err); | |
668 | if (err) { | |
669 | error_propagate(errp, err); | |
670 | return; | |
671 | } | |
672 | if (fd != -1 || msg < 0 || msg > IVSHMEM_MAX_PEERS) { | |
673 | error_setg(errp, "server sent invalid ID message"); | |
674 | return; | |
675 | } | |
676 | s->vm_id = msg; | |
677 | ||
3a55fc0f MA |
678 | /* |
679 | * Receive more messages until we got shared memory. | |
680 | */ | |
681 | do { | |
1309cf44 MA |
682 | msg = ivshmem_recv_msg(s, &fd, &err); |
683 | if (err) { | |
684 | error_propagate(errp, err); | |
685 | return; | |
686 | } | |
687 | process_msg(s, msg, fd, &err); | |
688 | if (err) { | |
689 | error_propagate(errp, err); | |
690 | return; | |
691 | } | |
3a55fc0f | 692 | } while (msg != -1); |
1309cf44 MA |
693 | |
694 | /* | |
695 | * This function must either map the shared memory or fail. The | |
696 | * loop above ensures that: it terminates normally only after it | |
697 | * successfully processed the server's shared memory message. | |
698 | * Assert that actually mapped the shared memory: | |
699 | */ | |
c2d8019c | 700 | assert(s->ivshmem_bar2); |
5105b1d8 DM |
701 | } |
702 | ||
4490c711 MT |
703 | /* Select the MSI-X vectors used by device. |
704 | * ivshmem maps events to vectors statically, so | |
705 | * we just enable all vectors on init and after reset. */ | |
082751e8 | 706 | static void ivshmem_msix_vector_use(IVShmemState *s) |
4490c711 | 707 | { |
b7578eaa | 708 | PCIDevice *d = PCI_DEVICE(s); |
4490c711 MT |
709 | int i; |
710 | ||
4490c711 | 711 | for (i = 0; i < s->vectors; i++) { |
b7578eaa | 712 | msix_vector_use(d, i); |
4490c711 MT |
713 | } |
714 | } | |
715 | ||
a4022791 LP |
716 | static void ivshmem_disable_irqfd(IVShmemState *s); |
717 | ||
6cbf4c8c CM |
718 | static void ivshmem_reset(DeviceState *d) |
719 | { | |
5400c02b | 720 | IVShmemState *s = IVSHMEM_COMMON(d); |
6cbf4c8c | 721 | |
a4022791 LP |
722 | ivshmem_disable_irqfd(s); |
723 | ||
6cbf4c8c | 724 | s->intrstatus = 0; |
972ad215 | 725 | s->intrmask = 0; |
082751e8 MA |
726 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
727 | ivshmem_msix_vector_use(s); | |
728 | } | |
6cbf4c8c CM |
729 | } |
730 | ||
ee640c62 | 731 | static int ivshmem_setup_interrupts(IVShmemState *s, Error **errp) |
4490c711 | 732 | { |
fd47bfe5 | 733 | /* allocate QEMU callback data for receiving interrupts */ |
b21e2380 | 734 | s->msi_vectors = g_new0(MSIVector, s->vectors); |
6cbf4c8c | 735 | |
fd47bfe5 | 736 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
ee640c62 | 737 | if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1, errp)) { |
fd47bfe5 MAL |
738 | return -1; |
739 | } | |
1116b539 | 740 | |
fd47bfe5 | 741 | IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors); |
082751e8 | 742 | ivshmem_msix_vector_use(s); |
fd47bfe5 | 743 | } |
4490c711 | 744 | |
d58d7e84 | 745 | return 0; |
6cbf4c8c CM |
746 | } |
747 | ||
0b88dd94 LP |
748 | static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector) |
749 | { | |
750 | IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector); | |
751 | ||
752 | if (s->msi_vectors[vector].pdev == NULL) { | |
753 | return; | |
754 | } | |
755 | ||
756 | /* it was cleaned when masked in the frontend. */ | |
757 | kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq); | |
758 | ||
759 | s->msi_vectors[vector].pdev = NULL; | |
760 | } | |
761 | ||
660c97ee MAL |
762 | static void ivshmem_enable_irqfd(IVShmemState *s) |
763 | { | |
764 | PCIDevice *pdev = PCI_DEVICE(s); | |
765 | int i; | |
766 | ||
767 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
1309cf44 MA |
768 | Error *err = NULL; |
769 | ||
770 | ivshmem_add_kvm_msi_virq(s, i, &err); | |
771 | if (err) { | |
772 | error_report_err(err); | |
0b88dd94 | 773 | goto undo; |
1309cf44 | 774 | } |
660c97ee MAL |
775 | } |
776 | ||
777 | if (msix_set_vector_notifiers(pdev, | |
778 | ivshmem_vector_unmask, | |
779 | ivshmem_vector_mask, | |
780 | ivshmem_vector_poll)) { | |
781 | error_report("ivshmem: msix_set_vector_notifiers failed"); | |
0b88dd94 | 782 | goto undo; |
660c97ee | 783 | } |
0b88dd94 | 784 | return; |
660c97ee | 785 | |
0b88dd94 LP |
786 | undo: |
787 | while (--i >= 0) { | |
788 | ivshmem_remove_kvm_msi_virq(s, i); | |
660c97ee | 789 | } |
660c97ee MAL |
790 | } |
791 | ||
792 | static void ivshmem_disable_irqfd(IVShmemState *s) | |
793 | { | |
794 | PCIDevice *pdev = PCI_DEVICE(s); | |
795 | int i; | |
796 | ||
0b88dd94 LP |
797 | if (!pdev->msix_vector_use_notifier) { |
798 | return; | |
799 | } | |
800 | ||
089fd803 LP |
801 | msix_unset_vector_notifiers(pdev); |
802 | ||
660c97ee | 803 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { |
089fd803 LP |
804 | /* |
805 | * MSI-X is already disabled here so msix_unset_vector_notifiers() | |
806 | * didn't call our release notifier. Do it now to keep our masks and | |
807 | * unmasks balanced. | |
808 | */ | |
809 | if (s->msi_vectors[i].unmasked) { | |
810 | ivshmem_vector_mask(pdev, i); | |
811 | } | |
660c97ee MAL |
812 | ivshmem_remove_kvm_msi_virq(s, i); |
813 | } | |
814 | ||
660c97ee MAL |
815 | } |
816 | ||
817 | static void ivshmem_write_config(PCIDevice *pdev, uint32_t address, | |
d58d7e84 | 818 | uint32_t val, int len) |
4490c711 | 819 | { |
5400c02b | 820 | IVShmemState *s = IVSHMEM_COMMON(pdev); |
660c97ee MAL |
821 | int is_enabled, was_enabled = msix_enabled(pdev); |
822 | ||
823 | pci_default_write_config(pdev, address, val, len); | |
824 | is_enabled = msix_enabled(pdev); | |
825 | ||
1309cf44 | 826 | if (kvm_msi_via_irqfd_enabled()) { |
660c97ee MAL |
827 | if (!was_enabled && is_enabled) { |
828 | ivshmem_enable_irqfd(s); | |
829 | } else if (was_enabled && !is_enabled) { | |
830 | ivshmem_disable_irqfd(s); | |
831 | } | |
832 | } | |
4490c711 MT |
833 | } |
834 | ||
5400c02b | 835 | static void ivshmem_common_realize(PCIDevice *dev, Error **errp) |
6cbf4c8c | 836 | { |
5400c02b | 837 | IVShmemState *s = IVSHMEM_COMMON(dev); |
d855e275 | 838 | Error *err = NULL; |
6cbf4c8c CM |
839 | uint8_t *pci_conf; |
840 | ||
6cbf4c8c CM |
841 | /* IRQFD requires MSI */ |
842 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) && | |
843 | !ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
d58d7e84 MAL |
844 | error_setg(errp, "ioeventfd/irqfd requires MSI"); |
845 | return; | |
6cbf4c8c CM |
846 | } |
847 | ||
b7578eaa | 848 | pci_conf = dev->config; |
6cbf4c8c | 849 | pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
6cbf4c8c | 850 | |
3c161542 | 851 | memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s, |
cb06608e AK |
852 | "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE); |
853 | ||
6cbf4c8c | 854 | /* region for registers*/ |
b7578eaa | 855 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, |
e824b2cc | 856 | &s->ivshmem_mmio); |
cb06608e | 857 | |
d9453c93 | 858 | if (s->hostmem != NULL) { |
d9453c93 MAL |
859 | IVSHMEM_DPRINTF("using hostmem\n"); |
860 | ||
7943e97b | 861 | s->ivshmem_bar2 = host_memory_backend_get_memory(s->hostmem); |
b266f1d1 | 862 | host_memory_backend_set_mapped(s->hostmem, true); |
5503e285 | 863 | } else { |
0ec7b3e7 | 864 | Chardev *chr = qemu_chr_fe_get_driver(&s->server_chr); |
5345fdb4 | 865 | assert(chr); |
6dc64780 | 866 | |
6cbf4c8c | 867 | IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n", |
5345fdb4 | 868 | chr->filename); |
6cbf4c8c | 869 | |
f456179f | 870 | /* we allocate enough space for 16 peers and grow as needed */ |
1300b273 | 871 | resize_peers(s, 16); |
6cbf4c8c | 872 | |
3a55fc0f MA |
873 | /* |
874 | * Receive setup messages from server synchronously. | |
875 | * Older versions did it asynchronously, but that creates a | |
876 | * number of entertaining race conditions. | |
3a55fc0f | 877 | */ |
1309cf44 MA |
878 | ivshmem_recv_setup(s, &err); |
879 | if (err) { | |
880 | error_propagate(errp, err); | |
881 | return; | |
3a55fc0f MA |
882 | } |
883 | ||
62a830b6 MA |
884 | if (s->master == ON_OFF_AUTO_ON && s->vm_id != 0) { |
885 | error_setg(errp, | |
886 | "master must connect to the server before any peers"); | |
887 | return; | |
888 | } | |
889 | ||
5345fdb4 | 890 | qemu_chr_fe_set_handlers(&s->server_chr, ivshmem_can_receive, |
81517ba3 | 891 | ivshmem_read, NULL, NULL, s, NULL, true); |
1309cf44 | 892 | |
ee640c62 C |
893 | if (ivshmem_setup_interrupts(s, errp) < 0) { |
894 | error_prepend(errp, "Failed to initialize interrupts: "); | |
3a55fc0f MA |
895 | return; |
896 | } | |
d855e275 MA |
897 | } |
898 | ||
2a845da7 MA |
899 | if (s->master == ON_OFF_AUTO_AUTO) { |
900 | s->master = s->vm_id == 0 ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; | |
901 | } | |
902 | ||
903 | if (!ivshmem_is_master(s)) { | |
d855e275 MA |
904 | error_setg(&s->migration_blocker, |
905 | "Migration is disabled when using feature 'peer mode' in device 'ivshmem'"); | |
386f6c07 | 906 | if (migrate_add_blocker(s->migration_blocker, errp) < 0) { |
fe44dc91 AA |
907 | error_free(s->migration_blocker); |
908 | return; | |
909 | } | |
6cbf4c8c | 910 | } |
fe44dc91 AA |
911 | |
912 | vmstate_register_ram(s->ivshmem_bar2, DEVICE(s)); | |
5a0e75f0 TH |
913 | pci_register_bar(PCI_DEVICE(s), 2, |
914 | PCI_BASE_ADDRESS_SPACE_MEMORY | | |
915 | PCI_BASE_ADDRESS_MEM_PREFETCH | | |
916 | PCI_BASE_ADDRESS_MEM_TYPE_64, | |
917 | s->ivshmem_bar2); | |
6cbf4c8c CM |
918 | } |
919 | ||
5400c02b MA |
920 | static void ivshmem_exit(PCIDevice *dev) |
921 | { | |
922 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
f64a078d MAL |
923 | int i; |
924 | ||
38e0735e AL |
925 | if (s->migration_blocker) { |
926 | migrate_del_blocker(s->migration_blocker); | |
927 | error_free(s->migration_blocker); | |
928 | } | |
929 | ||
c2d8019c | 930 | if (memory_region_is_mapped(s->ivshmem_bar2)) { |
d9453c93 | 931 | if (!s->hostmem) { |
c2d8019c | 932 | void *addr = memory_region_get_ram_ptr(s->ivshmem_bar2); |
56a571d9 | 933 | int fd; |
d9453c93 | 934 | |
5400c02b | 935 | if (munmap(addr, memory_region_size(s->ivshmem_bar2) == -1)) { |
d9453c93 MAL |
936 | error_report("Failed to munmap shared memory %s", |
937 | strerror(errno)); | |
938 | } | |
56a571d9 | 939 | |
4ff87573 | 940 | fd = memory_region_get_fd(s->ivshmem_bar2); |
c2d8019c | 941 | close(fd); |
d9453c93 | 942 | } |
f64a078d | 943 | |
c2d8019c | 944 | vmstate_unregister_ram(s->ivshmem_bar2, DEVICE(dev)); |
f64a078d MAL |
945 | } |
946 | ||
b266f1d1 MA |
947 | if (s->hostmem) { |
948 | host_memory_backend_set_mapped(s->hostmem, false); | |
949 | } | |
950 | ||
f64a078d MAL |
951 | if (s->peers) { |
952 | for (i = 0; i < s->nb_peers; i++) { | |
f456179f | 953 | close_peer_eventfds(s, i); |
f64a078d MAL |
954 | } |
955 | g_free(s->peers); | |
956 | } | |
957 | ||
958 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
959 | msix_uninit_exclusive_bar(dev); | |
960 | } | |
961 | ||
0f57350e | 962 | g_free(s->msi_vectors); |
6cbf4c8c CM |
963 | } |
964 | ||
1f8552df MAL |
965 | static int ivshmem_pre_load(void *opaque) |
966 | { | |
967 | IVShmemState *s = opaque; | |
968 | ||
2a845da7 | 969 | if (!ivshmem_is_master(s)) { |
1f8552df MAL |
970 | error_report("'peer' devices are not migratable"); |
971 | return -EINVAL; | |
972 | } | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
977 | static int ivshmem_post_load(void *opaque, int version_id) | |
978 | { | |
979 | IVShmemState *s = opaque; | |
980 | ||
981 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
082751e8 | 982 | ivshmem_msix_vector_use(s); |
1f8552df | 983 | } |
1f8552df MAL |
984 | return 0; |
985 | } | |
986 | ||
5400c02b | 987 | static void ivshmem_common_class_init(ObjectClass *klass, void *data) |
40021f08 | 988 | { |
39bffca2 | 989 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
990 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
991 | ||
5400c02b MA |
992 | k->realize = ivshmem_common_realize; |
993 | k->exit = ivshmem_exit; | |
d58d7e84 | 994 | k->config_write = ivshmem_write_config; |
b8ef62a9 PB |
995 | k->vendor_id = PCI_VENDOR_ID_IVSHMEM; |
996 | k->device_id = PCI_DEVICE_ID_IVSHMEM; | |
40021f08 | 997 | k->class_id = PCI_CLASS_MEMORY_RAM; |
5400c02b | 998 | k->revision = 1; |
39bffca2 | 999 | dc->reset = ivshmem_reset; |
125ee0ed | 1000 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
d383537d | 1001 | dc->desc = "Inter-VM shared memory"; |
40021f08 AL |
1002 | } |
1003 | ||
ddc85284 MA |
1004 | static const TypeInfo ivshmem_common_info = { |
1005 | .name = TYPE_IVSHMEM_COMMON, | |
1006 | .parent = TYPE_PCI_DEVICE, | |
1007 | .instance_size = sizeof(IVShmemState), | |
1008 | .abstract = true, | |
1009 | .class_init = ivshmem_common_class_init, | |
fd3b02c8 EH |
1010 | .interfaces = (InterfaceInfo[]) { |
1011 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
1012 | { }, | |
1013 | }, | |
ddc85284 | 1014 | }; |
5400c02b | 1015 | |
5400c02b MA |
1016 | static const VMStateDescription ivshmem_plain_vmsd = { |
1017 | .name = TYPE_IVSHMEM_PLAIN, | |
1018 | .version_id = 0, | |
1019 | .minimum_version_id = 0, | |
1020 | .pre_load = ivshmem_pre_load, | |
1021 | .post_load = ivshmem_post_load, | |
1022 | .fields = (VMStateField[]) { | |
1023 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1024 | VMSTATE_UINT32(intrstatus, IVShmemState), | |
1025 | VMSTATE_UINT32(intrmask, IVShmemState), | |
1026 | VMSTATE_END_OF_LIST() | |
1027 | }, | |
1028 | }; | |
1029 | ||
1030 | static Property ivshmem_plain_properties[] = { | |
1031 | DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), | |
e9cb190a FZ |
1032 | DEFINE_PROP_LINK("memdev", IVShmemState, hostmem, TYPE_MEMORY_BACKEND, |
1033 | HostMemoryBackend *), | |
5400c02b MA |
1034 | DEFINE_PROP_END_OF_LIST(), |
1035 | }; | |
1036 | ||
6dc64780 MAL |
1037 | static void ivshmem_plain_realize(PCIDevice *dev, Error **errp) |
1038 | { | |
1039 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
1040 | ||
1041 | if (!s->hostmem) { | |
1042 | error_setg(errp, "You must specify a 'memdev'"); | |
1043 | return; | |
e9cb190a | 1044 | } else if (host_memory_backend_is_mapped(s->hostmem)) { |
7a309cc9 MA |
1045 | error_setg(errp, "can't use already busy memdev: %s", |
1046 | object_get_canonical_path_component(OBJECT(s->hostmem))); | |
e9cb190a | 1047 | return; |
6dc64780 MAL |
1048 | } |
1049 | ||
1050 | ivshmem_common_realize(dev, errp); | |
1051 | } | |
1052 | ||
5400c02b MA |
1053 | static void ivshmem_plain_class_init(ObjectClass *klass, void *data) |
1054 | { | |
1055 | DeviceClass *dc = DEVICE_CLASS(klass); | |
6dc64780 | 1056 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
5400c02b | 1057 | |
6dc64780 | 1058 | k->realize = ivshmem_plain_realize; |
4f67d30b | 1059 | device_class_set_props(dc, ivshmem_plain_properties); |
5400c02b MA |
1060 | dc->vmsd = &ivshmem_plain_vmsd; |
1061 | } | |
1062 | ||
1063 | static const TypeInfo ivshmem_plain_info = { | |
1064 | .name = TYPE_IVSHMEM_PLAIN, | |
1065 | .parent = TYPE_IVSHMEM_COMMON, | |
1066 | .instance_size = sizeof(IVShmemState), | |
5400c02b MA |
1067 | .class_init = ivshmem_plain_class_init, |
1068 | }; | |
1069 | ||
1070 | static const VMStateDescription ivshmem_doorbell_vmsd = { | |
1071 | .name = TYPE_IVSHMEM_DOORBELL, | |
1072 | .version_id = 0, | |
1073 | .minimum_version_id = 0, | |
1074 | .pre_load = ivshmem_pre_load, | |
1075 | .post_load = ivshmem_post_load, | |
1076 | .fields = (VMStateField[]) { | |
1077 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1078 | VMSTATE_MSIX(parent_obj, IVShmemState), | |
1079 | VMSTATE_UINT32(intrstatus, IVShmemState), | |
1080 | VMSTATE_UINT32(intrmask, IVShmemState), | |
1081 | VMSTATE_END_OF_LIST() | |
1082 | }, | |
1083 | }; | |
1084 | ||
1085 | static Property ivshmem_doorbell_properties[] = { | |
1086 | DEFINE_PROP_CHR("chardev", IVShmemState, server_chr), | |
1087 | DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1), | |
1088 | DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, | |
1089 | true), | |
1090 | DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), | |
1091 | DEFINE_PROP_END_OF_LIST(), | |
1092 | }; | |
1093 | ||
1094 | static void ivshmem_doorbell_init(Object *obj) | |
1095 | { | |
1096 | IVShmemState *s = IVSHMEM_DOORBELL(obj); | |
1097 | ||
1098 | s->features |= (1 << IVSHMEM_MSI); | |
5400c02b MA |
1099 | } |
1100 | ||
6dc64780 MAL |
1101 | static void ivshmem_doorbell_realize(PCIDevice *dev, Error **errp) |
1102 | { | |
1103 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
1104 | ||
30650701 | 1105 | if (!qemu_chr_fe_backend_connected(&s->server_chr)) { |
6dc64780 MAL |
1106 | error_setg(errp, "You must specify a 'chardev'"); |
1107 | return; | |
1108 | } | |
1109 | ||
1110 | ivshmem_common_realize(dev, errp); | |
1111 | } | |
1112 | ||
5400c02b MA |
1113 | static void ivshmem_doorbell_class_init(ObjectClass *klass, void *data) |
1114 | { | |
1115 | DeviceClass *dc = DEVICE_CLASS(klass); | |
6dc64780 | 1116 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
5400c02b | 1117 | |
6dc64780 | 1118 | k->realize = ivshmem_doorbell_realize; |
4f67d30b | 1119 | device_class_set_props(dc, ivshmem_doorbell_properties); |
5400c02b MA |
1120 | dc->vmsd = &ivshmem_doorbell_vmsd; |
1121 | } | |
1122 | ||
1123 | static const TypeInfo ivshmem_doorbell_info = { | |
1124 | .name = TYPE_IVSHMEM_DOORBELL, | |
1125 | .parent = TYPE_IVSHMEM_COMMON, | |
1126 | .instance_size = sizeof(IVShmemState), | |
1127 | .instance_init = ivshmem_doorbell_init, | |
1128 | .class_init = ivshmem_doorbell_class_init, | |
1129 | }; | |
1130 | ||
83f7d43a | 1131 | static void ivshmem_register_types(void) |
6cbf4c8c | 1132 | { |
5400c02b MA |
1133 | type_register_static(&ivshmem_common_info); |
1134 | type_register_static(&ivshmem_plain_info); | |
1135 | type_register_static(&ivshmem_doorbell_info); | |
6cbf4c8c CM |
1136 | } |
1137 | ||
83f7d43a | 1138 | type_init(ivshmem_register_types) |