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Commit | Line | Data |
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6cbf4c8c CM |
1 | /* |
2 | * Inter-VM Shared Memory PCI device. | |
3 | * | |
4 | * Author: | |
5 | * Cam Macdonell <cam@cs.ualberta.ca> | |
6 | * | |
7 | * Based On: cirrus_vga.c | |
8 | * Copyright (c) 2004 Fabrice Bellard | |
9 | * Copyright (c) 2004 Makoto Suzuki (suzu) | |
10 | * | |
11 | * and rtl8139.c | |
12 | * Copyright (c) 2006 Igor Kovalenko | |
13 | * | |
14 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
15 | * |
16 | * Contributions after 2012-01-13 are licensed under the terms of the | |
17 | * GNU GPL, version 2 or (at your option) any later version. | |
6cbf4c8c | 18 | */ |
0d1c9782 | 19 | #include "qemu/osdep.h" |
83c9f4ca | 20 | #include "hw/hw.h" |
0d09e41a | 21 | #include "hw/i386/pc.h" |
83c9f4ca | 22 | #include "hw/pci/pci.h" |
660c97ee | 23 | #include "hw/pci/msi.h" |
83c9f4ca | 24 | #include "hw/pci/msix.h" |
9c17d615 | 25 | #include "sysemu/kvm.h" |
caf71f86 | 26 | #include "migration/migration.h" |
d49b6836 | 27 | #include "qemu/error-report.h" |
1de7afc9 | 28 | #include "qemu/event_notifier.h" |
a2e9011b | 29 | #include "qemu/fifo8.h" |
dccfcd0e | 30 | #include "sysemu/char.h" |
d9453c93 MAL |
31 | #include "sysemu/hostmem.h" |
32 | #include "qapi/visitor.h" | |
56a571d9 | 33 | #include "exec/ram_addr.h" |
6cbf4c8c | 34 | |
5105b1d8 DM |
35 | #include "hw/misc/ivshmem.h" |
36 | ||
6cbf4c8c | 37 | #include <sys/mman.h> |
6cbf4c8c | 38 | |
b8ef62a9 PB |
39 | #define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET |
40 | #define PCI_DEVICE_ID_IVSHMEM 0x1110 | |
41 | ||
61ea2d86 | 42 | #define IVSHMEM_MAX_PEERS G_MAXUINT16 |
6cbf4c8c CM |
43 | #define IVSHMEM_IOEVENTFD 0 |
44 | #define IVSHMEM_MSI 1 | |
45 | ||
46 | #define IVSHMEM_PEER 0 | |
47 | #define IVSHMEM_MASTER 1 | |
48 | ||
49 | #define IVSHMEM_REG_BAR_SIZE 0x100 | |
50 | ||
51 | //#define DEBUG_IVSHMEM | |
52 | #ifdef DEBUG_IVSHMEM | |
53 | #define IVSHMEM_DPRINTF(fmt, ...) \ | |
54 | do {printf("IVSHMEM: " fmt, ## __VA_ARGS__); } while (0) | |
55 | #else | |
56 | #define IVSHMEM_DPRINTF(fmt, ...) | |
57 | #endif | |
58 | ||
eb3fedf3 PC |
59 | #define TYPE_IVSHMEM "ivshmem" |
60 | #define IVSHMEM(obj) \ | |
61 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM) | |
62 | ||
6cbf4c8c CM |
63 | typedef struct Peer { |
64 | int nb_eventfds; | |
563027cc | 65 | EventNotifier *eventfds; |
6cbf4c8c CM |
66 | } Peer; |
67 | ||
0f57350e | 68 | typedef struct MSIVector { |
6cbf4c8c | 69 | PCIDevice *pdev; |
660c97ee | 70 | int virq; |
0f57350e | 71 | } MSIVector; |
6cbf4c8c CM |
72 | |
73 | typedef struct IVShmemState { | |
b7578eaa AF |
74 | /*< private >*/ |
75 | PCIDevice parent_obj; | |
76 | /*< public >*/ | |
77 | ||
d9453c93 | 78 | HostMemoryBackend *hostmem; |
6cbf4c8c CM |
79 | uint32_t intrmask; |
80 | uint32_t intrstatus; | |
6cbf4c8c CM |
81 | |
82 | CharDriverState **eventfd_chr; | |
83 | CharDriverState *server_chr; | |
a2e9011b | 84 | Fifo8 incoming_fifo; |
cb06608e | 85 | MemoryRegion ivshmem_mmio; |
6cbf4c8c | 86 | |
cb06608e AK |
87 | /* We might need to register the BAR before we actually have the memory. |
88 | * So prepare a container MemoryRegion for the BAR immediately and | |
89 | * add a subregion when we have the memory. | |
90 | */ | |
91 | MemoryRegion bar; | |
92 | MemoryRegion ivshmem; | |
6cbf4c8c | 93 | uint64_t ivshmem_size; /* size of shared memory region */ |
c08ba66f | 94 | uint32_t ivshmem_64bit; |
6cbf4c8c CM |
95 | |
96 | Peer *peers; | |
f456179f | 97 | int nb_peers; /* how many peers we have space for */ |
6cbf4c8c CM |
98 | |
99 | int vm_id; | |
100 | uint32_t vectors; | |
101 | uint32_t features; | |
0f57350e | 102 | MSIVector *msi_vectors; |
6cbf4c8c | 103 | |
38e0735e AL |
104 | Error *migration_blocker; |
105 | ||
6cbf4c8c CM |
106 | char * shmobj; |
107 | char * sizearg; | |
108 | char * role; | |
109 | int role_val; /* scalar to avoid multiple string comparisons */ | |
110 | } IVShmemState; | |
111 | ||
112 | /* registers for the Inter-VM shared memory device */ | |
113 | enum ivshmem_registers { | |
114 | INTRMASK = 0, | |
115 | INTRSTATUS = 4, | |
116 | IVPOSITION = 8, | |
117 | DOORBELL = 12, | |
118 | }; | |
119 | ||
120 | static inline uint32_t ivshmem_has_feature(IVShmemState *ivs, | |
121 | unsigned int feature) { | |
122 | return (ivs->features & (1 << feature)); | |
123 | } | |
124 | ||
6cbf4c8c | 125 | /* accessing registers - based on rtl8139 */ |
d8a5da07 | 126 | static void ivshmem_update_irq(IVShmemState *s) |
6cbf4c8c | 127 | { |
b7578eaa | 128 | PCIDevice *d = PCI_DEVICE(s); |
6cbf4c8c CM |
129 | int isr; |
130 | isr = (s->intrstatus & s->intrmask) & 0xffffffff; | |
131 | ||
132 | /* don't print ISR resets */ | |
133 | if (isr) { | |
134 | IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n", | |
dbc464d4 | 135 | isr ? 1 : 0, s->intrstatus, s->intrmask); |
6cbf4c8c CM |
136 | } |
137 | ||
9e64f8a3 | 138 | pci_set_irq(d, (isr != 0)); |
6cbf4c8c CM |
139 | } |
140 | ||
141 | static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val) | |
142 | { | |
143 | IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val); | |
144 | ||
145 | s->intrmask = val; | |
146 | ||
d8a5da07 | 147 | ivshmem_update_irq(s); |
6cbf4c8c CM |
148 | } |
149 | ||
150 | static uint32_t ivshmem_IntrMask_read(IVShmemState *s) | |
151 | { | |
152 | uint32_t ret = s->intrmask; | |
153 | ||
154 | IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret); | |
155 | ||
156 | return ret; | |
157 | } | |
158 | ||
159 | static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val) | |
160 | { | |
161 | IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val); | |
162 | ||
163 | s->intrstatus = val; | |
164 | ||
d8a5da07 | 165 | ivshmem_update_irq(s); |
6cbf4c8c CM |
166 | } |
167 | ||
168 | static uint32_t ivshmem_IntrStatus_read(IVShmemState *s) | |
169 | { | |
170 | uint32_t ret = s->intrstatus; | |
171 | ||
172 | /* reading ISR clears all interrupts */ | |
173 | s->intrstatus = 0; | |
174 | ||
d8a5da07 | 175 | ivshmem_update_irq(s); |
6cbf4c8c CM |
176 | |
177 | return ret; | |
178 | } | |
179 | ||
a8170e5e | 180 | static void ivshmem_io_write(void *opaque, hwaddr addr, |
cb06608e | 181 | uint64_t val, unsigned size) |
6cbf4c8c CM |
182 | { |
183 | IVShmemState *s = opaque; | |
184 | ||
6cbf4c8c CM |
185 | uint16_t dest = val >> 16; |
186 | uint16_t vector = val & 0xff; | |
187 | ||
188 | addr &= 0xfc; | |
189 | ||
190 | IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr); | |
191 | switch (addr) | |
192 | { | |
193 | case INTRMASK: | |
194 | ivshmem_IntrMask_write(s, val); | |
195 | break; | |
196 | ||
197 | case INTRSTATUS: | |
198 | ivshmem_IntrStatus_write(s, val); | |
199 | break; | |
200 | ||
201 | case DOORBELL: | |
202 | /* check that dest VM ID is reasonable */ | |
95c8425c | 203 | if (dest >= s->nb_peers) { |
6cbf4c8c CM |
204 | IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest); |
205 | break; | |
206 | } | |
207 | ||
208 | /* check doorbell range */ | |
1b27d7a1 | 209 | if (vector < s->peers[dest].nb_eventfds) { |
563027cc PB |
210 | IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector); |
211 | event_notifier_set(&s->peers[dest].eventfds[vector]); | |
f59bb378 MAL |
212 | } else { |
213 | IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n", | |
214 | vector, dest); | |
6cbf4c8c CM |
215 | } |
216 | break; | |
217 | default: | |
f59bb378 | 218 | IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr); |
6cbf4c8c CM |
219 | } |
220 | } | |
221 | ||
a8170e5e | 222 | static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, |
cb06608e | 223 | unsigned size) |
6cbf4c8c CM |
224 | { |
225 | ||
226 | IVShmemState *s = opaque; | |
227 | uint32_t ret; | |
228 | ||
229 | switch (addr) | |
230 | { | |
231 | case INTRMASK: | |
232 | ret = ivshmem_IntrMask_read(s); | |
233 | break; | |
234 | ||
235 | case INTRSTATUS: | |
236 | ret = ivshmem_IntrStatus_read(s); | |
237 | break; | |
238 | ||
239 | case IVPOSITION: | |
240 | /* return my VM ID if the memory is mapped */ | |
f689d281 | 241 | if (memory_region_is_mapped(&s->ivshmem)) { |
6cbf4c8c CM |
242 | ret = s->vm_id; |
243 | } else { | |
244 | ret = -1; | |
245 | } | |
246 | break; | |
247 | ||
248 | default: | |
249 | IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr); | |
250 | ret = 0; | |
251 | } | |
252 | ||
253 | return ret; | |
254 | } | |
255 | ||
cb06608e AK |
256 | static const MemoryRegionOps ivshmem_mmio_ops = { |
257 | .read = ivshmem_io_read, | |
258 | .write = ivshmem_io_write, | |
259 | .endianness = DEVICE_NATIVE_ENDIAN, | |
260 | .impl = { | |
261 | .min_access_size = 4, | |
262 | .max_access_size = 4, | |
263 | }, | |
6cbf4c8c CM |
264 | }; |
265 | ||
6cbf4c8c CM |
266 | static int ivshmem_can_receive(void * opaque) |
267 | { | |
f7a199b2 | 268 | return sizeof(int64_t); |
6cbf4c8c CM |
269 | } |
270 | ||
271 | static void ivshmem_event(void *opaque, int event) | |
272 | { | |
273 | IVSHMEM_DPRINTF("ivshmem_event %d\n", event); | |
274 | } | |
275 | ||
9940c323 MAL |
276 | static void ivshmem_vector_notify(void *opaque) |
277 | { | |
0f57350e | 278 | MSIVector *entry = opaque; |
6cbf4c8c | 279 | PCIDevice *pdev = entry->pdev; |
d160f3f7 | 280 | IVShmemState *s = IVSHMEM(pdev); |
0f57350e | 281 | int vector = entry - s->msi_vectors; |
9940c323 MAL |
282 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
283 | ||
284 | if (!event_notifier_test_and_clear(n)) { | |
285 | return; | |
286 | } | |
6cbf4c8c | 287 | |
d160f3f7 | 288 | IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector); |
9940c323 MAL |
289 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
290 | msix_notify(pdev, vector); | |
291 | } else { | |
292 | ivshmem_IntrStatus_write(s, 1); | |
293 | } | |
6cbf4c8c CM |
294 | } |
295 | ||
660c97ee MAL |
296 | static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector, |
297 | MSIMessage msg) | |
298 | { | |
299 | IVShmemState *s = IVSHMEM(dev); | |
300 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
301 | MSIVector *v = &s->msi_vectors[vector]; | |
302 | int ret; | |
303 | ||
304 | IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector); | |
305 | ||
306 | ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev); | |
307 | if (ret < 0) { | |
308 | return ret; | |
309 | } | |
310 | ||
311 | return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq); | |
312 | } | |
313 | ||
314 | static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector) | |
315 | { | |
316 | IVShmemState *s = IVSHMEM(dev); | |
317 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
318 | int ret; | |
319 | ||
320 | IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector); | |
321 | ||
322 | ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, | |
323 | s->msi_vectors[vector].virq); | |
324 | if (ret != 0) { | |
325 | error_report("remove_irqfd_notifier_gsi failed"); | |
326 | } | |
327 | } | |
328 | ||
329 | static void ivshmem_vector_poll(PCIDevice *dev, | |
330 | unsigned int vector_start, | |
331 | unsigned int vector_end) | |
332 | { | |
333 | IVShmemState *s = IVSHMEM(dev); | |
334 | unsigned int vector; | |
335 | ||
336 | IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end); | |
337 | ||
338 | vector_end = MIN(vector_end, s->vectors); | |
339 | ||
340 | for (vector = vector_start; vector < vector_end; vector++) { | |
341 | EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector]; | |
342 | ||
343 | if (!msix_is_masked(dev, vector)) { | |
344 | continue; | |
345 | } | |
346 | ||
347 | if (event_notifier_test_and_clear(notifier)) { | |
348 | msix_set_pending(dev, vector); | |
349 | } | |
350 | } | |
351 | } | |
352 | ||
9940c323 MAL |
353 | static void watch_vector_notifier(IVShmemState *s, EventNotifier *n, |
354 | int vector) | |
6cbf4c8c | 355 | { |
563027cc | 356 | int eventfd = event_notifier_get_fd(n); |
6cbf4c8c CM |
357 | |
358 | /* if MSI is supported we need multiple interrupts */ | |
9940c323 | 359 | s->msi_vectors[vector].pdev = PCI_DEVICE(s); |
6cbf4c8c | 360 | |
9940c323 MAL |
361 | qemu_set_fd_handler(eventfd, ivshmem_vector_notify, |
362 | NULL, &s->msi_vectors[vector]); | |
6cbf4c8c CM |
363 | } |
364 | ||
d58d7e84 MAL |
365 | static int check_shm_size(IVShmemState *s, int fd, Error **errp) |
366 | { | |
6cbf4c8c CM |
367 | /* check that the guest isn't going to try and map more memory than the |
368 | * the object has allocated return -1 to indicate error */ | |
369 | ||
370 | struct stat buf; | |
371 | ||
5edbdbcd | 372 | if (fstat(fd, &buf) < 0) { |
d58d7e84 MAL |
373 | error_setg(errp, "exiting: fstat on fd %d failed: %s", |
374 | fd, strerror(errno)); | |
5edbdbcd HZ |
375 | return -1; |
376 | } | |
6cbf4c8c CM |
377 | |
378 | if (s->ivshmem_size > buf.st_size) { | |
d58d7e84 MAL |
379 | error_setg(errp, "Requested memory size greater" |
380 | " than shared object size (%" PRIu64 " > %" PRIu64")", | |
381 | s->ivshmem_size, (uint64_t)buf.st_size); | |
6cbf4c8c CM |
382 | return -1; |
383 | } else { | |
384 | return 0; | |
385 | } | |
386 | } | |
387 | ||
388 | /* create the shared memory BAR when we are not using the server, so we can | |
389 | * create the BAR and map the memory immediately */ | |
d58d7e84 MAL |
390 | static int create_shared_memory_BAR(IVShmemState *s, int fd, uint8_t attr, |
391 | Error **errp) | |
392 | { | |
6cbf4c8c CM |
393 | void * ptr; |
394 | ||
6cbf4c8c | 395 | ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); |
d58d7e84 MAL |
396 | if (ptr == MAP_FAILED) { |
397 | error_setg_errno(errp, errno, "Failed to mmap shared memory"); | |
398 | return -1; | |
399 | } | |
400 | ||
3c161542 | 401 | memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s), "ivshmem.bar2", |
cb06608e | 402 | s->ivshmem_size, ptr); |
8e41fb63 | 403 | qemu_set_ram_fd(memory_region_get_ram_addr(&s->ivshmem), fd); |
eb3fedf3 | 404 | vmstate_register_ram(&s->ivshmem, DEVICE(s)); |
cb06608e | 405 | memory_region_add_subregion(&s->bar, 0, &s->ivshmem); |
6cbf4c8c CM |
406 | |
407 | /* region for shared memory */ | |
9113e3f3 | 408 | pci_register_bar(PCI_DEVICE(s), 2, attr, &s->bar); |
d58d7e84 MAL |
409 | |
410 | return 0; | |
6cbf4c8c CM |
411 | } |
412 | ||
563027cc PB |
413 | static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i) |
414 | { | |
415 | memory_region_add_eventfd(&s->ivshmem_mmio, | |
416 | DOORBELL, | |
417 | 4, | |
418 | true, | |
419 | (posn << 16) | i, | |
753d5e14 | 420 | &s->peers[posn].eventfds[i]); |
563027cc PB |
421 | } |
422 | ||
423 | static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i) | |
424 | { | |
425 | memory_region_del_eventfd(&s->ivshmem_mmio, | |
426 | DOORBELL, | |
427 | 4, | |
428 | true, | |
429 | (posn << 16) | i, | |
753d5e14 | 430 | &s->peers[posn].eventfds[i]); |
563027cc PB |
431 | } |
432 | ||
f456179f | 433 | static void close_peer_eventfds(IVShmemState *s, int posn) |
6cbf4c8c | 434 | { |
f456179f | 435 | int i, n; |
6cbf4c8c | 436 | |
98609cd8 PB |
437 | if (!ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
438 | return; | |
439 | } | |
363ba1c7 | 440 | if (posn < 0 || posn >= s->nb_peers) { |
ffa99afd | 441 | error_report("invalid peer %d", posn); |
363ba1c7 SH |
442 | return; |
443 | } | |
98609cd8 | 444 | |
f456179f | 445 | n = s->peers[posn].nb_eventfds; |
6cbf4c8c | 446 | |
b6a1f3a5 | 447 | memory_region_transaction_begin(); |
f456179f | 448 | for (i = 0; i < n; i++) { |
563027cc | 449 | ivshmem_del_eventfd(s, posn, i); |
b6a1f3a5 PB |
450 | } |
451 | memory_region_transaction_commit(); | |
f456179f | 452 | for (i = 0; i < n; i++) { |
563027cc | 453 | event_notifier_cleanup(&s->peers[posn].eventfds[i]); |
6cbf4c8c CM |
454 | } |
455 | ||
7267c094 | 456 | g_free(s->peers[posn].eventfds); |
6cbf4c8c CM |
457 | s->peers[posn].nb_eventfds = 0; |
458 | } | |
459 | ||
6cbf4c8c | 460 | /* this function increase the dynamic storage need to store data about other |
f456179f | 461 | * peers */ |
1300b273 | 462 | static int resize_peers(IVShmemState *s, int new_min_size) |
34bc07c5 | 463 | { |
6cbf4c8c | 464 | |
1300b273 | 465 | int j, old_size; |
6cbf4c8c | 466 | |
61ea2d86 MAL |
467 | /* limit number of max peers */ |
468 | if (new_min_size <= 0 || new_min_size > IVSHMEM_MAX_PEERS) { | |
34bc07c5 SK |
469 | return -1; |
470 | } | |
1300b273 | 471 | if (new_min_size <= s->nb_peers) { |
34bc07c5 SK |
472 | return 0; |
473 | } | |
6cbf4c8c | 474 | |
1300b273 MAL |
475 | old_size = s->nb_peers; |
476 | s->nb_peers = new_min_size; | |
477 | ||
f456179f | 478 | IVSHMEM_DPRINTF("bumping storage to %d peers\n", s->nb_peers); |
1300b273 | 479 | |
7267c094 | 480 | s->peers = g_realloc(s->peers, s->nb_peers * sizeof(Peer)); |
6cbf4c8c | 481 | |
1300b273 | 482 | for (j = old_size; j < s->nb_peers; j++) { |
81e507f0 | 483 | s->peers[j].eventfds = g_new0(EventNotifier, s->vectors); |
6cbf4c8c CM |
484 | s->peers[j].nb_eventfds = 0; |
485 | } | |
34bc07c5 SK |
486 | |
487 | return 0; | |
6cbf4c8c CM |
488 | } |
489 | ||
0f14fd71 MAL |
490 | static bool fifo_update_and_get(IVShmemState *s, const uint8_t *buf, int size, |
491 | void *data, size_t len) | |
492 | { | |
493 | const uint8_t *p; | |
494 | uint32_t num; | |
495 | ||
f7a199b2 | 496 | assert(len <= sizeof(int64_t)); /* limitation of the fifo */ |
0f14fd71 MAL |
497 | if (fifo8_is_empty(&s->incoming_fifo) && size == len) { |
498 | memcpy(data, buf, size); | |
499 | return true; | |
500 | } | |
501 | ||
502 | IVSHMEM_DPRINTF("short read of %d bytes\n", size); | |
503 | ||
f7a199b2 | 504 | num = MIN(size, sizeof(int64_t) - fifo8_num_used(&s->incoming_fifo)); |
0f14fd71 MAL |
505 | fifo8_push_all(&s->incoming_fifo, buf, num); |
506 | ||
507 | if (fifo8_num_used(&s->incoming_fifo) < len) { | |
508 | assert(num == 0); | |
509 | return false; | |
510 | } | |
511 | ||
512 | size -= num; | |
513 | buf += num; | |
514 | p = fifo8_pop_buf(&s->incoming_fifo, len, &num); | |
515 | assert(num == len); | |
516 | ||
517 | memcpy(data, p, len); | |
518 | ||
519 | if (size > 0) { | |
520 | fifo8_push_all(&s->incoming_fifo, buf, size); | |
521 | } | |
522 | ||
523 | return true; | |
524 | } | |
525 | ||
f7a199b2 MAL |
526 | static bool fifo_update_and_get_i64(IVShmemState *s, |
527 | const uint8_t *buf, int size, int64_t *i64) | |
528 | { | |
529 | if (fifo_update_and_get(s, buf, size, i64, sizeof(*i64))) { | |
530 | *i64 = GINT64_FROM_LE(*i64); | |
531 | return true; | |
532 | } | |
533 | ||
534 | return false; | |
535 | } | |
536 | ||
660c97ee MAL |
537 | static int ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector) |
538 | { | |
539 | PCIDevice *pdev = PCI_DEVICE(s); | |
540 | MSIMessage msg = msix_get_message(pdev, vector); | |
541 | int ret; | |
542 | ||
543 | IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector); | |
544 | ||
545 | if (s->msi_vectors[vector].pdev != NULL) { | |
546 | return 0; | |
547 | } | |
548 | ||
549 | ret = kvm_irqchip_add_msi_route(kvm_state, msg, pdev); | |
550 | if (ret < 0) { | |
551 | error_report("ivshmem: kvm_irqchip_add_msi_route failed"); | |
552 | return -1; | |
553 | } | |
554 | ||
555 | s->msi_vectors[vector].virq = ret; | |
556 | s->msi_vectors[vector].pdev = pdev; | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
561 | static void setup_interrupt(IVShmemState *s, int vector) | |
562 | { | |
563 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
564 | bool with_irqfd = kvm_msi_via_irqfd_enabled() && | |
565 | ivshmem_has_feature(s, IVSHMEM_MSI); | |
566 | PCIDevice *pdev = PCI_DEVICE(s); | |
567 | ||
568 | IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector); | |
569 | ||
570 | if (!with_irqfd) { | |
97553976 | 571 | IVSHMEM_DPRINTF("with eventfd\n"); |
9940c323 | 572 | watch_vector_notifier(s, n, vector); |
660c97ee | 573 | } else if (msix_enabled(pdev)) { |
97553976 | 574 | IVSHMEM_DPRINTF("with irqfd\n"); |
660c97ee MAL |
575 | if (ivshmem_add_kvm_msi_virq(s, vector) < 0) { |
576 | return; | |
577 | } | |
578 | ||
579 | if (!msix_is_masked(pdev, vector)) { | |
580 | kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, | |
581 | s->msi_vectors[vector].virq); | |
582 | } | |
583 | } else { | |
584 | /* it will be delayed until msix is enabled, in write_config */ | |
97553976 | 585 | IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n"); |
660c97ee MAL |
586 | } |
587 | } | |
588 | ||
a2e9011b | 589 | static void ivshmem_read(void *opaque, const uint8_t *buf, int size) |
6cbf4c8c CM |
590 | { |
591 | IVShmemState *s = opaque; | |
dee2151e | 592 | int incoming_fd; |
9a2f0e64 | 593 | int new_eventfd; |
f7a199b2 | 594 | int64_t incoming_posn; |
d58d7e84 | 595 | Error *err = NULL; |
9a2f0e64 | 596 | Peer *peer; |
6cbf4c8c | 597 | |
f7a199b2 | 598 | if (!fifo_update_and_get_i64(s, buf, size, &incoming_posn)) { |
0f14fd71 | 599 | return; |
a2e9011b SH |
600 | } |
601 | ||
363ba1c7 | 602 | if (incoming_posn < -1) { |
f7a199b2 | 603 | IVSHMEM_DPRINTF("invalid incoming_posn %" PRId64 "\n", incoming_posn); |
363ba1c7 SH |
604 | return; |
605 | } | |
606 | ||
6cbf4c8c | 607 | /* pick off s->server_chr->msgfd and store it, posn should accompany msg */ |
dee2151e | 608 | incoming_fd = qemu_chr_fe_get_msgfd(s->server_chr); |
f7a199b2 MAL |
609 | IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", |
610 | incoming_posn, incoming_fd); | |
6cbf4c8c | 611 | |
f456179f | 612 | /* make sure we have enough space for this peer */ |
6cbf4c8c | 613 | if (incoming_posn >= s->nb_peers) { |
1300b273 MAL |
614 | if (resize_peers(s, incoming_posn + 1) < 0) { |
615 | error_report("failed to resize peers array"); | |
dee2151e MAL |
616 | if (incoming_fd != -1) { |
617 | close(incoming_fd); | |
34bc07c5 SK |
618 | } |
619 | return; | |
620 | } | |
6cbf4c8c CM |
621 | } |
622 | ||
9a2f0e64 MAL |
623 | peer = &s->peers[incoming_posn]; |
624 | ||
dee2151e | 625 | if (incoming_fd == -1) { |
6cbf4c8c | 626 | /* if posn is positive and unseen before then this is our posn*/ |
81e507f0 | 627 | if (incoming_posn >= 0 && s->vm_id == -1) { |
6cbf4c8c CM |
628 | /* receive our posn */ |
629 | s->vm_id = incoming_posn; | |
6cbf4c8c | 630 | } else { |
f456179f | 631 | /* otherwise an fd == -1 means an existing peer has gone away */ |
f7a199b2 | 632 | IVSHMEM_DPRINTF("posn %" PRId64 " has gone away\n", incoming_posn); |
f456179f | 633 | close_peer_eventfds(s, incoming_posn); |
6cbf4c8c | 634 | } |
6f8a16d5 | 635 | return; |
6cbf4c8c CM |
636 | } |
637 | ||
6cbf4c8c CM |
638 | /* if the position is -1, then it's shared memory region fd */ |
639 | if (incoming_posn == -1) { | |
6cbf4c8c CM |
640 | void * map_ptr; |
641 | ||
f689d281 | 642 | if (memory_region_is_mapped(&s->ivshmem)) { |
945001a1 MAL |
643 | error_report("shm already initialized"); |
644 | close(incoming_fd); | |
645 | return; | |
646 | } | |
647 | ||
d58d7e84 MAL |
648 | if (check_shm_size(s, incoming_fd, &err) == -1) { |
649 | error_report_err(err); | |
650 | close(incoming_fd); | |
651 | return; | |
6cbf4c8c CM |
652 | } |
653 | ||
654 | /* mmap the region and map into the BAR2 */ | |
655 | map_ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED, | |
656 | incoming_fd, 0); | |
d58d7e84 MAL |
657 | if (map_ptr == MAP_FAILED) { |
658 | error_report("Failed to mmap shared memory %s", strerror(errno)); | |
659 | close(incoming_fd); | |
660 | return; | |
661 | } | |
3c161542 | 662 | memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s), |
cb06608e | 663 | "ivshmem.bar2", s->ivshmem_size, map_ptr); |
8e41fb63 FZ |
664 | qemu_set_ram_fd(memory_region_get_ram_addr(&s->ivshmem), |
665 | incoming_fd); | |
eb3fedf3 | 666 | vmstate_register_ram(&s->ivshmem, DEVICE(s)); |
6cbf4c8c | 667 | |
7f9efb6b | 668 | IVSHMEM_DPRINTF("guest h/w addr = %p, size = %" PRIu64 "\n", |
dbc464d4 | 669 | map_ptr, s->ivshmem_size); |
6cbf4c8c | 670 | |
cb06608e | 671 | memory_region_add_subregion(&s->bar, 0, &s->ivshmem); |
6cbf4c8c | 672 | |
6cbf4c8c CM |
673 | return; |
674 | } | |
675 | ||
9a2f0e64 MAL |
676 | /* each peer has an associated array of eventfds, and we keep |
677 | * track of how many eventfds received so far */ | |
678 | /* get a new eventfd: */ | |
1ee57de4 MAL |
679 | if (peer->nb_eventfds >= s->vectors) { |
680 | error_report("Too many eventfd received, device has %d vectors", | |
681 | s->vectors); | |
682 | close(incoming_fd); | |
683 | return; | |
684 | } | |
685 | ||
9a2f0e64 | 686 | new_eventfd = peer->nb_eventfds++; |
6cbf4c8c | 687 | |
f456179f | 688 | /* this is an eventfd for a particular peer VM */ |
f7a199b2 | 689 | IVSHMEM_DPRINTF("eventfds[%" PRId64 "][%d] = %d\n", incoming_posn, |
9a2f0e64 MAL |
690 | new_eventfd, incoming_fd); |
691 | event_notifier_init_fd(&peer->eventfds[new_eventfd], incoming_fd); | |
660c97ee | 692 | fcntl_setfl(incoming_fd, O_NONBLOCK); /* msix/irqfd poll non block */ |
6cbf4c8c | 693 | |
6cbf4c8c | 694 | if (incoming_posn == s->vm_id) { |
660c97ee | 695 | setup_interrupt(s, new_eventfd); |
6cbf4c8c CM |
696 | } |
697 | ||
698 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { | |
9a2f0e64 | 699 | ivshmem_add_eventfd(s, incoming_posn, new_eventfd); |
6cbf4c8c | 700 | } |
6cbf4c8c CM |
701 | } |
702 | ||
5105b1d8 DM |
703 | static void ivshmem_check_version(void *opaque, const uint8_t * buf, int size) |
704 | { | |
705 | IVShmemState *s = opaque; | |
706 | int tmp; | |
f7a199b2 | 707 | int64_t version; |
5105b1d8 | 708 | |
f7a199b2 | 709 | if (!fifo_update_and_get_i64(s, buf, size, &version)) { |
5105b1d8 DM |
710 | return; |
711 | } | |
712 | ||
713 | tmp = qemu_chr_fe_get_msgfd(s->server_chr); | |
714 | if (tmp != -1 || version != IVSHMEM_PROTOCOL_VERSION) { | |
715 | fprintf(stderr, "incompatible version, you are connecting to a ivshmem-" | |
716 | "server using a different protocol please check your setup\n"); | |
717 | qemu_chr_delete(s->server_chr); | |
718 | s->server_chr = NULL; | |
719 | return; | |
720 | } | |
721 | ||
722 | IVSHMEM_DPRINTF("version check ok, switch to real chardev handler\n"); | |
723 | qemu_chr_add_handlers(s->server_chr, ivshmem_can_receive, ivshmem_read, | |
724 | ivshmem_event, s); | |
725 | } | |
726 | ||
4490c711 MT |
727 | /* Select the MSI-X vectors used by device. |
728 | * ivshmem maps events to vectors statically, so | |
729 | * we just enable all vectors on init and after reset. */ | |
730 | static void ivshmem_use_msix(IVShmemState * s) | |
731 | { | |
b7578eaa | 732 | PCIDevice *d = PCI_DEVICE(s); |
4490c711 MT |
733 | int i; |
734 | ||
f59bb378 | 735 | IVSHMEM_DPRINTF("%s, msix present: %d\n", __func__, msix_present(d)); |
b7578eaa | 736 | if (!msix_present(d)) { |
4490c711 MT |
737 | return; |
738 | } | |
739 | ||
740 | for (i = 0; i < s->vectors; i++) { | |
b7578eaa | 741 | msix_vector_use(d, i); |
4490c711 MT |
742 | } |
743 | } | |
744 | ||
6cbf4c8c CM |
745 | static void ivshmem_reset(DeviceState *d) |
746 | { | |
eb3fedf3 | 747 | IVShmemState *s = IVSHMEM(d); |
6cbf4c8c CM |
748 | |
749 | s->intrstatus = 0; | |
972ad215 | 750 | s->intrmask = 0; |
4490c711 | 751 | ivshmem_use_msix(s); |
6cbf4c8c CM |
752 | } |
753 | ||
fd47bfe5 | 754 | static int ivshmem_setup_interrupts(IVShmemState *s) |
4490c711 | 755 | { |
fd47bfe5 MAL |
756 | /* allocate QEMU callback data for receiving interrupts */ |
757 | s->msi_vectors = g_malloc0(s->vectors * sizeof(MSIVector)); | |
6cbf4c8c | 758 | |
fd47bfe5 MAL |
759 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
760 | if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1)) { | |
761 | return -1; | |
762 | } | |
1116b539 | 763 | |
fd47bfe5 MAL |
764 | IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors); |
765 | ivshmem_use_msix(s); | |
766 | } | |
4490c711 | 767 | |
d58d7e84 | 768 | return 0; |
6cbf4c8c CM |
769 | } |
770 | ||
660c97ee MAL |
771 | static void ivshmem_enable_irqfd(IVShmemState *s) |
772 | { | |
773 | PCIDevice *pdev = PCI_DEVICE(s); | |
774 | int i; | |
775 | ||
776 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
777 | ivshmem_add_kvm_msi_virq(s, i); | |
778 | } | |
779 | ||
780 | if (msix_set_vector_notifiers(pdev, | |
781 | ivshmem_vector_unmask, | |
782 | ivshmem_vector_mask, | |
783 | ivshmem_vector_poll)) { | |
784 | error_report("ivshmem: msix_set_vector_notifiers failed"); | |
785 | } | |
786 | } | |
787 | ||
788 | static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector) | |
789 | { | |
790 | IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector); | |
791 | ||
792 | if (s->msi_vectors[vector].pdev == NULL) { | |
793 | return; | |
794 | } | |
795 | ||
796 | /* it was cleaned when masked in the frontend. */ | |
797 | kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq); | |
798 | ||
799 | s->msi_vectors[vector].pdev = NULL; | |
800 | } | |
801 | ||
802 | static void ivshmem_disable_irqfd(IVShmemState *s) | |
803 | { | |
804 | PCIDevice *pdev = PCI_DEVICE(s); | |
805 | int i; | |
806 | ||
807 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
808 | ivshmem_remove_kvm_msi_virq(s, i); | |
809 | } | |
810 | ||
811 | msix_unset_vector_notifiers(pdev); | |
812 | } | |
813 | ||
814 | static void ivshmem_write_config(PCIDevice *pdev, uint32_t address, | |
d58d7e84 | 815 | uint32_t val, int len) |
4490c711 | 816 | { |
660c97ee MAL |
817 | IVShmemState *s = IVSHMEM(pdev); |
818 | int is_enabled, was_enabled = msix_enabled(pdev); | |
819 | ||
820 | pci_default_write_config(pdev, address, val, len); | |
821 | is_enabled = msix_enabled(pdev); | |
822 | ||
823 | if (kvm_msi_via_irqfd_enabled() && s->vm_id != -1) { | |
824 | if (!was_enabled && is_enabled) { | |
825 | ivshmem_enable_irqfd(s); | |
826 | } else if (was_enabled && !is_enabled) { | |
827 | ivshmem_disable_irqfd(s); | |
828 | } | |
829 | } | |
4490c711 MT |
830 | } |
831 | ||
d58d7e84 | 832 | static void pci_ivshmem_realize(PCIDevice *dev, Error **errp) |
6cbf4c8c | 833 | { |
eb3fedf3 | 834 | IVShmemState *s = IVSHMEM(dev); |
6cbf4c8c | 835 | uint8_t *pci_conf; |
9113e3f3 MAL |
836 | uint8_t attr = PCI_BASE_ADDRESS_SPACE_MEMORY | |
837 | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
6cbf4c8c | 838 | |
d9453c93 | 839 | if (!!s->server_chr + !!s->shmobj + !!s->hostmem != 1) { |
1d649244 MA |
840 | error_setg(errp, |
841 | "You must specify either 'shm', 'chardev' or 'x-memdev'"); | |
d9453c93 MAL |
842 | return; |
843 | } | |
844 | ||
845 | if (s->hostmem) { | |
846 | MemoryRegion *mr; | |
847 | ||
848 | if (s->sizearg) { | |
849 | g_warning("size argument ignored with hostmem"); | |
850 | } | |
851 | ||
852 | mr = host_memory_backend_get_memory(s->hostmem, errp); | |
853 | s->ivshmem_size = memory_region_size(mr); | |
854 | } else if (s->sizearg == NULL) { | |
6cbf4c8c | 855 | s->ivshmem_size = 4 << 20; /* 4 MB default */ |
d58d7e84 | 856 | } else { |
2c04752c MAL |
857 | char *end; |
858 | int64_t size = qemu_strtosz(s->sizearg, &end); | |
859 | if (size < 0 || *end != '\0' || !is_power_of_2(size)) { | |
860 | error_setg(errp, "Invalid size %s", s->sizearg); | |
d58d7e84 MAL |
861 | return; |
862 | } | |
2c04752c | 863 | s->ivshmem_size = size; |
6cbf4c8c CM |
864 | } |
865 | ||
f7a199b2 | 866 | fifo8_create(&s->incoming_fifo, sizeof(int64_t)); |
1f8552df | 867 | |
6cbf4c8c CM |
868 | /* IRQFD requires MSI */ |
869 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) && | |
870 | !ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
d58d7e84 MAL |
871 | error_setg(errp, "ioeventfd/irqfd requires MSI"); |
872 | return; | |
6cbf4c8c CM |
873 | } |
874 | ||
875 | /* check that role is reasonable */ | |
876 | if (s->role) { | |
877 | if (strncmp(s->role, "peer", 5) == 0) { | |
878 | s->role_val = IVSHMEM_PEER; | |
879 | } else if (strncmp(s->role, "master", 7) == 0) { | |
880 | s->role_val = IVSHMEM_MASTER; | |
881 | } else { | |
d58d7e84 MAL |
882 | error_setg(errp, "'role' must be 'peer' or 'master'"); |
883 | return; | |
6cbf4c8c CM |
884 | } |
885 | } else { | |
886 | s->role_val = IVSHMEM_MASTER; /* default */ | |
887 | } | |
888 | ||
889 | if (s->role_val == IVSHMEM_PEER) { | |
f231b88d CR |
890 | error_setg(&s->migration_blocker, |
891 | "Migration is disabled when using feature 'peer mode' in device 'ivshmem'"); | |
38e0735e | 892 | migrate_add_blocker(s->migration_blocker); |
6cbf4c8c CM |
893 | } |
894 | ||
b7578eaa | 895 | pci_conf = dev->config; |
6cbf4c8c | 896 | pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
6cbf4c8c CM |
897 | |
898 | pci_config_set_interrupt_pin(pci_conf, 1); | |
899 | ||
3c161542 | 900 | memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s, |
cb06608e AK |
901 | "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE); |
902 | ||
6cbf4c8c | 903 | /* region for registers*/ |
b7578eaa | 904 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, |
e824b2cc | 905 | &s->ivshmem_mmio); |
cb06608e | 906 | |
3c161542 | 907 | memory_region_init(&s->bar, OBJECT(s), "ivshmem-bar2-container", s->ivshmem_size); |
c08ba66f | 908 | if (s->ivshmem_64bit) { |
9113e3f3 | 909 | attr |= PCI_BASE_ADDRESS_MEM_TYPE_64; |
c08ba66f | 910 | } |
6cbf4c8c | 911 | |
d9453c93 MAL |
912 | if (s->hostmem != NULL) { |
913 | MemoryRegion *mr; | |
914 | ||
915 | IVSHMEM_DPRINTF("using hostmem\n"); | |
916 | ||
917 | mr = host_memory_backend_get_memory(MEMORY_BACKEND(s->hostmem), errp); | |
918 | vmstate_register_ram(mr, DEVICE(s)); | |
919 | memory_region_add_subregion(&s->bar, 0, mr); | |
920 | pci_register_bar(PCI_DEVICE(s), 2, attr, &s->bar); | |
921 | } else if (s->server_chr != NULL) { | |
2825717c | 922 | /* FIXME do not rely on what chr drivers put into filename */ |
36617792 MAL |
923 | if (strncmp(s->server_chr->filename, "unix:", 5)) { |
924 | error_setg(errp, "chardev is not a unix client socket"); | |
925 | return; | |
926 | } | |
927 | ||
6cbf4c8c CM |
928 | /* if we get a UNIX socket as the parameter we will talk |
929 | * to the ivshmem server to receive the memory region */ | |
930 | ||
6cbf4c8c | 931 | IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n", |
dbc464d4 | 932 | s->server_chr->filename); |
6cbf4c8c | 933 | |
fd47bfe5 MAL |
934 | if (ivshmem_setup_interrupts(s) < 0) { |
935 | error_setg(errp, "failed to initialize interrupts"); | |
d58d7e84 | 936 | return; |
6cbf4c8c CM |
937 | } |
938 | ||
f456179f | 939 | /* we allocate enough space for 16 peers and grow as needed */ |
1300b273 | 940 | resize_peers(s, 16); |
6cbf4c8c CM |
941 | s->vm_id = -1; |
942 | ||
9113e3f3 | 943 | pci_register_bar(dev, 2, attr, &s->bar); |
6cbf4c8c | 944 | |
7267c094 | 945 | s->eventfd_chr = g_malloc0(s->vectors * sizeof(CharDriverState *)); |
6cbf4c8c | 946 | |
5105b1d8 DM |
947 | qemu_chr_add_handlers(s->server_chr, ivshmem_can_receive, |
948 | ivshmem_check_version, ivshmem_event, s); | |
6cbf4c8c CM |
949 | } else { |
950 | /* just map the file immediately, we're not using a server */ | |
951 | int fd; | |
952 | ||
6cbf4c8c CM |
953 | IVSHMEM_DPRINTF("using shm_open (shm object = %s)\n", s->shmobj); |
954 | ||
955 | /* try opening with O_EXCL and if it succeeds zero the memory | |
956 | * by truncating to 0 */ | |
957 | if ((fd = shm_open(s->shmobj, O_CREAT|O_RDWR|O_EXCL, | |
958 | S_IRWXU|S_IRWXG|S_IRWXO)) > 0) { | |
959 | /* truncate file to length PCI device's memory */ | |
960 | if (ftruncate(fd, s->ivshmem_size) != 0) { | |
dbc464d4 | 961 | error_report("could not truncate shared file"); |
6cbf4c8c CM |
962 | } |
963 | ||
964 | } else if ((fd = shm_open(s->shmobj, O_CREAT|O_RDWR, | |
965 | S_IRWXU|S_IRWXG|S_IRWXO)) < 0) { | |
d58d7e84 MAL |
966 | error_setg(errp, "could not open shared file"); |
967 | return; | |
6cbf4c8c CM |
968 | } |
969 | ||
d58d7e84 MAL |
970 | if (check_shm_size(s, fd, errp) == -1) { |
971 | return; | |
6cbf4c8c CM |
972 | } |
973 | ||
d58d7e84 | 974 | create_shared_memory_BAR(s, fd, attr, errp); |
6cbf4c8c | 975 | } |
6cbf4c8c CM |
976 | } |
977 | ||
d58d7e84 | 978 | static void pci_ivshmem_exit(PCIDevice *dev) |
6cbf4c8c | 979 | { |
eb3fedf3 | 980 | IVShmemState *s = IVSHMEM(dev); |
f64a078d MAL |
981 | int i; |
982 | ||
983 | fifo8_destroy(&s->incoming_fifo); | |
6cbf4c8c | 984 | |
38e0735e AL |
985 | if (s->migration_blocker) { |
986 | migrate_del_blocker(s->migration_blocker); | |
987 | error_free(s->migration_blocker); | |
988 | } | |
989 | ||
f689d281 | 990 | if (memory_region_is_mapped(&s->ivshmem)) { |
d9453c93 MAL |
991 | if (!s->hostmem) { |
992 | void *addr = memory_region_get_ram_ptr(&s->ivshmem); | |
56a571d9 | 993 | int fd; |
d9453c93 MAL |
994 | |
995 | if (munmap(addr, s->ivshmem_size) == -1) { | |
996 | error_report("Failed to munmap shared memory %s", | |
997 | strerror(errno)); | |
998 | } | |
56a571d9 | 999 | |
8e41fb63 FZ |
1000 | fd = qemu_get_ram_fd(memory_region_get_ram_addr(&s->ivshmem)); |
1001 | if (fd != -1) { | |
56a571d9 | 1002 | close(fd); |
8e41fb63 | 1003 | } |
d9453c93 | 1004 | } |
f64a078d MAL |
1005 | |
1006 | vmstate_unregister_ram(&s->ivshmem, DEVICE(dev)); | |
1007 | memory_region_del_subregion(&s->bar, &s->ivshmem); | |
f64a078d MAL |
1008 | } |
1009 | ||
1010 | if (s->eventfd_chr) { | |
1011 | for (i = 0; i < s->vectors; i++) { | |
1012 | if (s->eventfd_chr[i]) { | |
1013 | qemu_chr_free(s->eventfd_chr[i]); | |
1014 | } | |
1015 | } | |
1016 | g_free(s->eventfd_chr); | |
1017 | } | |
1018 | ||
1019 | if (s->peers) { | |
1020 | for (i = 0; i < s->nb_peers; i++) { | |
f456179f | 1021 | close_peer_eventfds(s, i); |
f64a078d MAL |
1022 | } |
1023 | g_free(s->peers); | |
1024 | } | |
1025 | ||
1026 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
1027 | msix_uninit_exclusive_bar(dev); | |
1028 | } | |
1029 | ||
0f57350e | 1030 | g_free(s->msi_vectors); |
6cbf4c8c CM |
1031 | } |
1032 | ||
1f8552df MAL |
1033 | static bool test_msix(void *opaque, int version_id) |
1034 | { | |
1035 | IVShmemState *s = opaque; | |
1036 | ||
1037 | return ivshmem_has_feature(s, IVSHMEM_MSI); | |
1038 | } | |
1039 | ||
1040 | static bool test_no_msix(void *opaque, int version_id) | |
1041 | { | |
1042 | return !test_msix(opaque, version_id); | |
1043 | } | |
1044 | ||
1045 | static int ivshmem_pre_load(void *opaque) | |
1046 | { | |
1047 | IVShmemState *s = opaque; | |
1048 | ||
1049 | if (s->role_val == IVSHMEM_PEER) { | |
1050 | error_report("'peer' devices are not migratable"); | |
1051 | return -EINVAL; | |
1052 | } | |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | static int ivshmem_post_load(void *opaque, int version_id) | |
1058 | { | |
1059 | IVShmemState *s = opaque; | |
1060 | ||
1061 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
1062 | ivshmem_use_msix(s); | |
1063 | } | |
1064 | ||
1065 | return 0; | |
1066 | } | |
1067 | ||
1068 | static int ivshmem_load_old(QEMUFile *f, void *opaque, int version_id) | |
1069 | { | |
1070 | IVShmemState *s = opaque; | |
1071 | PCIDevice *pdev = PCI_DEVICE(s); | |
1072 | int ret; | |
1073 | ||
1074 | IVSHMEM_DPRINTF("ivshmem_load_old\n"); | |
1075 | ||
1076 | if (version_id != 0) { | |
1077 | return -EINVAL; | |
1078 | } | |
1079 | ||
1080 | if (s->role_val == IVSHMEM_PEER) { | |
1081 | error_report("'peer' devices are not migratable"); | |
1082 | return -EINVAL; | |
1083 | } | |
1084 | ||
1085 | ret = pci_device_load(pdev, f); | |
1086 | if (ret) { | |
1087 | return ret; | |
1088 | } | |
1089 | ||
1090 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
1091 | msix_load(pdev, f); | |
1092 | ivshmem_use_msix(s); | |
1093 | } else { | |
1094 | s->intrstatus = qemu_get_be32(f); | |
1095 | s->intrmask = qemu_get_be32(f); | |
1096 | } | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | static const VMStateDescription ivshmem_vmsd = { | |
1102 | .name = "ivshmem", | |
1103 | .version_id = 1, | |
1104 | .minimum_version_id = 1, | |
1105 | .pre_load = ivshmem_pre_load, | |
1106 | .post_load = ivshmem_post_load, | |
1107 | .fields = (VMStateField[]) { | |
1108 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1109 | ||
1110 | VMSTATE_MSIX_TEST(parent_obj, IVShmemState, test_msix), | |
1111 | VMSTATE_UINT32_TEST(intrstatus, IVShmemState, test_no_msix), | |
1112 | VMSTATE_UINT32_TEST(intrmask, IVShmemState, test_no_msix), | |
1113 | ||
1114 | VMSTATE_END_OF_LIST() | |
1115 | }, | |
1116 | .load_state_old = ivshmem_load_old, | |
1117 | .minimum_version_id_old = 0 | |
1118 | }; | |
1119 | ||
40021f08 AL |
1120 | static Property ivshmem_properties[] = { |
1121 | DEFINE_PROP_CHR("chardev", IVShmemState, server_chr), | |
1122 | DEFINE_PROP_STRING("size", IVShmemState, sizearg), | |
1123 | DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1), | |
1124 | DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, false), | |
1125 | DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true), | |
1126 | DEFINE_PROP_STRING("shm", IVShmemState, shmobj), | |
1127 | DEFINE_PROP_STRING("role", IVShmemState, role), | |
c08ba66f | 1128 | DEFINE_PROP_UINT32("use64", IVShmemState, ivshmem_64bit, 1), |
40021f08 AL |
1129 | DEFINE_PROP_END_OF_LIST(), |
1130 | }; | |
1131 | ||
1132 | static void ivshmem_class_init(ObjectClass *klass, void *data) | |
1133 | { | |
39bffca2 | 1134 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1135 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1136 | ||
d58d7e84 MAL |
1137 | k->realize = pci_ivshmem_realize; |
1138 | k->exit = pci_ivshmem_exit; | |
1139 | k->config_write = ivshmem_write_config; | |
b8ef62a9 PB |
1140 | k->vendor_id = PCI_VENDOR_ID_IVSHMEM; |
1141 | k->device_id = PCI_DEVICE_ID_IVSHMEM; | |
40021f08 | 1142 | k->class_id = PCI_CLASS_MEMORY_RAM; |
39bffca2 AL |
1143 | dc->reset = ivshmem_reset; |
1144 | dc->props = ivshmem_properties; | |
1f8552df | 1145 | dc->vmsd = &ivshmem_vmsd; |
125ee0ed | 1146 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
d383537d | 1147 | dc->desc = "Inter-VM shared memory"; |
40021f08 AL |
1148 | } |
1149 | ||
d9453c93 MAL |
1150 | static void ivshmem_check_memdev_is_busy(Object *obj, const char *name, |
1151 | Object *val, Error **errp) | |
1152 | { | |
1153 | MemoryRegion *mr; | |
1154 | ||
1155 | mr = host_memory_backend_get_memory(MEMORY_BACKEND(val), errp); | |
1156 | if (memory_region_is_mapped(mr)) { | |
1157 | char *path = object_get_canonical_path_component(val); | |
1158 | error_setg(errp, "can't use already busy memdev: %s", path); | |
1159 | g_free(path); | |
1160 | } else { | |
1161 | qdev_prop_allow_set_link_before_realize(obj, name, val, errp); | |
1162 | } | |
1163 | } | |
1164 | ||
1165 | static void ivshmem_init(Object *obj) | |
1166 | { | |
1167 | IVShmemState *s = IVSHMEM(obj); | |
1168 | ||
1d649244 | 1169 | object_property_add_link(obj, "x-memdev", TYPE_MEMORY_BACKEND, |
d9453c93 MAL |
1170 | (Object **)&s->hostmem, |
1171 | ivshmem_check_memdev_is_busy, | |
1172 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | |
1173 | &error_abort); | |
1174 | } | |
1175 | ||
8c43a6f0 | 1176 | static const TypeInfo ivshmem_info = { |
eb3fedf3 | 1177 | .name = TYPE_IVSHMEM, |
39bffca2 AL |
1178 | .parent = TYPE_PCI_DEVICE, |
1179 | .instance_size = sizeof(IVShmemState), | |
d9453c93 | 1180 | .instance_init = ivshmem_init, |
39bffca2 | 1181 | .class_init = ivshmem_class_init, |
6cbf4c8c CM |
1182 | }; |
1183 | ||
83f7d43a | 1184 | static void ivshmem_register_types(void) |
6cbf4c8c | 1185 | { |
39bffca2 | 1186 | type_register_static(&ivshmem_info); |
6cbf4c8c CM |
1187 | } |
1188 | ||
83f7d43a | 1189 | type_init(ivshmem_register_types) |